Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15989822	1			T2	1898		T3	1		T4	1
all_pins[1]	15989822	1			T2	1898		T3	1		T4	1
all_pins[2]	15989822	1			T2	1898		T3	1		T4	1
all_pins[3]	15989822	1			T2	1898		T3	1		T4	1
all_pins[4]	15989822	1			T2	1898		T3	1		T4	1
all_pins[5]	15989822	1			T2	1898		T3	1		T4	1
all_pins[6]	15989822	1			T2	1898		T3	1		T4	1
all_pins[7]	15989822	1			T2	1898		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	127589275	1			T2	15184		T3	8		T4	8
values[0x1]	329301	1			T28	17		T49	17		T53	30946
transitions[0x0=>0x1]	321860	1			T28	13		T49	14		T53	30206
transitions[0x1=>0x0]	321887	1			T28	13		T49	14		T53	30206

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15985991	1			T2	1898		T3	1		T4	1
all_pins[0]	values[0x1]	3831	1			T28	4		T49	2		T53	228
all_pins[0]	transitions[0x0=>0x1]	2709	1			T28	3		T49	1		T53	153
all_pins[0]	transitions[0x1=>0x0]	1194	1			T28	2		T53	9		T152	6
all_pins[1]	values[0x0]	15987506	1			T2	1898		T3	1		T4	1
all_pins[1]	values[0x1]	2316	1			T28	3		T49	1		T53	84
all_pins[1]	transitions[0x0=>0x1]	1960	1			T28	1		T53	76		T136	1
all_pins[1]	transitions[0x1=>0x0]	303	1			T53	3		T120	1		T152	1
all_pins[2]	values[0x0]	15989163	1			T2	1898		T3	1		T4	1
all_pins[2]	values[0x1]	659	1			T28	2		T49	1		T53	11
all_pins[2]	transitions[0x0=>0x1]	588	1			T28	2		T49	1		T53	11
all_pins[2]	transitions[0x1=>0x0]	297	1			T28	1		T49	3		T53	2
all_pins[3]	values[0x0]	15989454	1			T2	1898		T3	1		T4	1
all_pins[3]	values[0x1]	368	1			T28	1		T49	3		T53	2
all_pins[3]	transitions[0x0=>0x1]	270	1			T28	1		T49	3		T53	1
all_pins[3]	transitions[0x1=>0x0]	302	1			T28	3		T49	2		T53	5
all_pins[4]	values[0x0]	15989422	1			T2	1898		T3	1		T4	1
all_pins[4]	values[0x1]	400	1			T28	3		T49	2		T53	6
all_pins[4]	transitions[0x0=>0x1]	317	1			T28	2		T49	1		T53	5
all_pins[4]	transitions[0x1=>0x0]	11532	1			T49	2		T53	654		T136	1
all_pins[5]	values[0x0]	15978207	1			T2	1898		T3	1		T4	1
all_pins[5]	values[0x1]	11615	1			T28	1		T49	3		T53	655
all_pins[5]	transitions[0x0=>0x1]	6103	1			T28	1		T49	3		T53	3
all_pins[5]	transitions[0x1=>0x0]	304218	1			T28	3		T49	2		T53	29303
all_pins[6]	values[0x0]	15680092	1			T2	1898		T3	1		T4	1
all_pins[6]	values[0x1]	309730	1			T28	3		T49	2		T53	29955
all_pins[6]	transitions[0x0=>0x1]	309641	1			T28	3		T49	2		T53	29953
all_pins[6]	transitions[0x1=>0x0]	293	1			T49	3		T53	3		T136	3
all_pins[7]	values[0x0]	15989440	1			T2	1898		T3	1		T4	1
all_pins[7]	values[0x1]	382	1			T49	3		T53	5		T136	3
all_pins[7]	transitions[0x0=>0x1]	272	1			T49	3		T53	4		T136	2
all_pins[7]	transitions[0x1=>0x0]	3748	1			T28	4		T49	2		T53	227