Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9154	1			T5	78		T11	20		T14	47
values[1]	8775	1			T5	88		T11	41		T14	29
values[2]	9115	1			T5	99		T11	144		T14	20
values[3]	9449	1			T14	24		T28	40		T48	22
values[4]	10134	1			T5	20		T11	147		T13	22
values[5]	9723	1			T8	24		T11	50		T12	18
values[6]	9863	1			T5	150		T11	220		T14	88
values[7]	9110	1			T5	62		T11	98		T26	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9479	1			T5	27		T11	142		T14	20
values[1]	9625	1			T5	67		T11	132		T12	18
values[2]	10019	1			T5	105		T23	28		T46	34
values[3]	10374	1			T5	20		T8	24		T11	169
values[4]	9254	1			T5	123		T23	28		T27	51
values[5]	8966	1			T11	56		T23	75		T28	21
values[6]	8310	1			T11	38		T14	33		T47	14
values[7]	9296	1			T5	155		T11	183		T14	24

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74065

1

T5

491

T8

24

T11

704

auto[1]

1258

1

T5

6

T11

16

T14

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	1208	1			T119	20		T220	26		T35	71
auto[0]	values[0]	values[1]	1277	1			T11	20		T14	20		T30	20
auto[0]	values[0]	values[2]	1320	1			T5	58		T23	27		T46	34
auto[0]	values[0]	values[3]	1047	1			T5	20		T14	25		T147	6
auto[0]	values[0]	values[4]	1181	1			T27	51		T29	33		T30	20
auto[0]	values[0]	values[5]	1064	1			T28	21		T228	12		T236	14
auto[0]	values[0]	values[6]	1040	1			T27	107		T28	25		T29	20
auto[0]	values[0]	values[7]	858	1			T32	25		T119	20		T152	26
auto[0]	values[1]	values[0]	743	1			T28	23		T152	20		T191	18
auto[0]	values[1]	values[1]	881	1			T5	27		T11	39		T14	28
auto[0]	values[1]	values[2]	1326	1			T5	20		T119	29		T153	36
auto[0]	values[1]	values[3]	1015	1			T172	21		T207	31		T168	20
auto[0]	values[1]	values[4]	1100	1			T155	83		T223	18		T168	20
auto[0]	values[1]	values[5]	1168	1			T155	62		T120	18		T18	20
auto[0]	values[1]	values[6]	1171	1			T18	20		T237	41		T189	20
auto[0]	values[1]	values[7]	1221	1			T5	40		T27	20		T217	24
auto[0]	values[2]	values[0]	1181	1			T11	32		T194	24		T18	20
auto[0]	values[2]	values[1]	1144	1			T5	20		T27	89		T28	20
auto[0]	values[2]	values[2]	1493	1			T5	26		T28	60		T29	20
auto[0]	values[2]	values[3]	1093	1			T14	20		T29	30		T175	20
auto[0]	values[2]	values[4]	900	1			T32	17		T155	115		T18	24
auto[0]	values[2]	values[5]	1354	1			T29	20		T31	20		T119	35
auto[0]	values[2]	values[6]	746	1			T120	23		T213	4		T174	20
auto[0]	values[2]	values[7]	1050	1			T5	52		T11	108		T45	12
auto[0]	values[3]	values[0]	1057	1			T28	17		T29	21		T119	25
auto[0]	values[3]	values[1]	1428	1			T119	109		T177	81		T123	19
auto[0]	values[3]	values[2]	1305	1			T48	22		T179	48		T18	22
auto[0]	values[3]	values[3]	1663	1			T155	20		T179	30		T152	20
auto[0]	values[3]	values[4]	745	1			T119	34		T120	20		T172	29
auto[0]	values[3]	values[5]	1040	1			T32	29		T229	16		T226	2
auto[0]	values[3]	values[6]	1076	1			T123	26		T153	20		T168	46
auto[0]	values[3]	values[7]	972	1			T14	24		T28	20		T29	48
auto[0]	values[4]	values[0]	1200	1			T11	40		T29	72		T30	22
auto[0]	values[4]	values[1]	1177	1			T5	20		T11	68		T187	8
auto[0]	values[4]	values[2]	1180	1			T28	20		T29	32		T195	10
auto[0]	values[4]	values[3]	1310	1			T13	22		T175	33		T212	10
auto[0]	values[4]	values[4]	1184	1			T32	20		T179	40		T152	53
auto[0]	values[4]	values[5]	1239	1			T11	36		T23	49		T29	123
auto[0]	values[4]	values[6]	1437	1			T172	25		T221	14		T191	39
auto[0]	values[4]	values[7]	1224	1			T177	28		T153	20		T237	26
auto[0]	values[5]	values[0]	1470	1			T11	47		T28	20		T29	23
auto[0]	values[5]	values[1]	1317	1			T12	18		T14	20		T23	62
auto[0]	values[5]	values[2]	898	1			T175	56		T35	24		T153	45
auto[0]	values[5]	values[3]	1592	1			T8	24		T120	20		T172	20
auto[0]	values[5]	values[4]	1076	1			T23	27		T28	24		T148	6
auto[0]	values[5]	values[5]	1404	1			T29	50		T238	12		T168	51
auto[0]	values[5]	values[6]	676	1			T32	22		T36	20		T181	20
auto[0]	values[5]	values[7]	1129	1			T153	61		T191	20		T168	24
auto[0]	values[6]	values[0]	1282	1			T5	26		T175	20		T123	29
auto[0]	values[6]	values[1]	1125	1			T14	33		T44	4		T29	19
auto[0]	values[6]	values[2]	1242	1			T119	20		T230	14		T152	20
auto[0]	values[6]	values[3]	1383	1			T11	128		T14	20		T30	20
auto[0]	values[6]	values[4]	1493	1			T5	120		T32	20		T216	42
auto[0]	values[6]	values[5]	669	1			T23	24		T192	28		T191	20
auto[0]	values[6]	values[6]	1128	1			T11	37		T14	32		T47	14
auto[0]	values[6]	values[7]	1407	1			T11	51		T48	20		T30	21
auto[0]	values[7]	values[0]	1192	1			T11	20		T14	20		T32	20
auto[0]	values[7]	values[1]	1128	1			T26	4		T29	21		T153	20
auto[0]	values[7]	values[2]	1100	1			T120	24		T35	38		T153	35
auto[0]	values[7]	values[3]	1092	1			T11	38		T48	20		T30	21
auto[0]	values[7]	values[4]	1412	1			T48	22		T32	20		T178	18
auto[0]	values[7]	values[5]	847	1			T11	20		T32	25		T119	20
auto[0]	values[7]	values[6]	907	1			T172	22		T168	58		T189	19
auto[0]	values[7]	values[7]	1278	1			T5	62		T11	20		T172	24
auto[1]	values[0]	values[0]	22	1			T239	2		T240	1		T241	1
auto[1]	values[0]	values[1]	20	1			T120	2		T209	1		T242	1
auto[1]	values[0]	values[2]	18	1			T23	1		T27	1		T189	2
auto[1]	values[0]	values[3]	17	1			T14	2		T231	1		T243	2
auto[1]	values[0]	values[4]	25	1			T168	2		T189	1		T206	1
auto[1]	values[0]	values[5]	17	1			T189	2		T240	3		T244	1
auto[1]	values[0]	values[6]	21	1			T27	1		T36	4		T245	3
auto[1]	values[0]	values[7]	19	1			T152	1		T168	1		T231	1
auto[1]	values[1]	values[0]	17	1			T191	2		T246	2		T247	6
auto[1]	values[1]	values[1]	16	1			T11	2		T14	1		T168	2
auto[1]	values[1]	values[2]	25	1			T153	3		T191	2		T215	2
auto[1]	values[1]	values[3]	17	1			T172	1		T248	4		T249	2
auto[1]	values[1]	values[4]	15	1			T239	1		T250	1		T251	2
auto[1]	values[1]	values[5]	25	1			T155	2		T120	2		T232	1
auto[1]	values[1]	values[6]	13	1			T252	1		T206	1		T246	3
auto[1]	values[1]	values[7]	22	1			T5	1		T189	1		T225	1
auto[1]	values[2]	values[0]	25	1			T35	2		T215	1		T242	4
auto[1]	values[2]	values[1]	14	1			T27	1		T30	1		T215	1
auto[1]	values[2]	values[2]	17	1			T5	1		T28	1		T172	1
auto[1]	values[2]	values[3]	15	1			T36	1		T250	2		T253	1
auto[1]	values[2]	values[4]	18	1			T32	3		T202	1		T254	1
auto[1]	values[2]	values[5]	32	1			T29	2		T31	2		T168	4
auto[1]	values[2]	values[6]	14	1			T120	1		T255	2		T256	2
auto[1]	values[2]	values[7]	19	1			T11	4		T29	1		T37	1
auto[1]	values[3]	values[0]	19	1			T28	3		T29	1		T119	1
auto[1]	values[3]	values[1]	19	1			T119	2		T123	1		T252	1
auto[1]	values[3]	values[2]	25	1			T257	2		T254	1		T258	1
auto[1]	values[3]	values[3]	25	1			T188	1		T259	1		T140	1
auto[1]	values[3]	values[4]	20	1			T252	4		T260	1		T36	2
auto[1]	values[3]	values[5]	22	1			T153	1		T261	2		T262	2
auto[1]	values[3]	values[6]	14	1			T168	2		T263	1		T41	3
auto[1]	values[3]	values[7]	19	1			T177	2		T168	1		T215	3
auto[1]	values[4]	values[0]	14	1			T29	1		T35	2		T231	1
auto[1]	values[4]	values[1]	22	1			T11	3		T155	3		T152	1
auto[1]	values[4]	values[2]	17	1			T215	4		T173	2		T209	2
auto[1]	values[4]	values[3]	28	1			T179	2		T169	1		T246	1
auto[1]	values[4]	values[4]	26	1			T152	3		T206	1		T250	1
auto[1]	values[4]	values[5]	34	1			T23	1		T29	2		T153	4
auto[1]	values[4]	values[6]	25	1			T191	2		T215	1		T254	1
auto[1]	values[4]	values[7]	17	1			T231	1		T202	4		T39	1
auto[1]	values[5]	values[0]	25	1			T11	3		T32	1		T155	3
auto[1]	values[5]	values[1]	14	1			T18	2		T35	1		T206	1
auto[1]	values[5]	values[2]	21	1			T175	4		T153	1		T191	1
auto[1]	values[5]	values[3]	29	1			T264	1		T206	2		T202	2
auto[1]	values[5]	values[4]	16	1			T23	1		T28	2		T123	2
auto[1]	values[5]	values[5]	25	1			T29	4		T168	1		T206	7
auto[1]	values[5]	values[6]	10	1			T263	2		T265	1		T266	1
auto[1]	values[5]	values[7]	21	1			T153	1		T181	1		T267	1
auto[1]	values[6]	values[0]	9	1			T5	1		T35	1		T168	1
auto[1]	values[6]	values[1]	22	1			T14	2		T29	1		T179	1
auto[1]	values[6]	values[2]	18	1			T182	2		T239	1		T268	2
auto[1]	values[6]	values[3]	20	1			T11	3		T119	1		T189	1
auto[1]	values[6]	values[4]	21	1			T5	3		T206	1		T70	3
auto[1]	values[6]	values[5]	7	1			T23	1		T269	2		T270	1
auto[1]	values[6]	values[6]	18	1			T11	1		T14	1		T168	1
auto[1]	values[6]	values[7]	19	1			T35	2		T189	2		T215	3
auto[1]	values[7]	values[0]	15	1			T271	4		T272	5		T273	2
auto[1]	values[7]	values[1]	21	1			T168	1		T242	2		T274	3
auto[1]	values[7]	values[2]	14	1			T35	1		T237	1		T258	2
auto[1]	values[7]	values[3]	28	1			T30	1		T172	3		T206	2
auto[1]	values[7]	values[4]	22	1			T179	2		T169	1		T246	2
auto[1]	values[7]	values[5]	19	1			T123	1		T39	1		T274	1
auto[1]	values[7]	values[6]	14	1			T189	1		T275	1		T269	2
auto[1]	values[7]	values[7]	21	1			T37	3		T253	5		T276	2