Summary for Variable cp_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_addr_4b_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3594 |
1 |
|
|
T5 |
9 |
|
T7 |
16 |
|
T9 |
6 |
auto[1] |
3515 |
1 |
|
|
T5 |
7 |
|
T7 |
13 |
|
T9 |
8 |
Summary for Variable cp_prev_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_prev_addr_4b_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3581 |
1 |
|
|
T5 |
8 |
|
T7 |
17 |
|
T9 |
6 |
auto[1] |
3528 |
1 |
|
|
T5 |
8 |
|
T7 |
12 |
|
T9 |
8 |
Summary for Cross cr_all
Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_addr_4b_en | cp_prev_addr_4b_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1903 |
1 |
|
|
T5 |
4 |
|
T7 |
11 |
|
T9 |
3 |
auto[0] |
auto[1] |
1691 |
1 |
|
|
T5 |
5 |
|
T7 |
5 |
|
T9 |
3 |
auto[1] |
auto[0] |
1678 |
1 |
|
|
T5 |
4 |
|
T7 |
6 |
|
T9 |
3 |
auto[1] |
auto[1] |
1837 |
1 |
|
|
T5 |
3 |
|
T7 |
7 |
|
T9 |
5 |