Group : spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_addr_4b_en 2 0 2 100.00 100 1 1 2
cp_prev_addr_4b_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3594 1 T5 9 T7 16 T9 6
auto[1] 3515 1 T5 7 T7 13 T9 8



Summary for Variable cp_prev_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3581 1 T5 8 T7 17 T9 6
auto[1] 3528 1 T5 8 T7 12 T9 8



Summary for Cross cr_all

Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_addr_4b_encp_prev_addr_4b_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1903 1 T5 4 T7 11 T9 3
auto[0] auto[1] 1691 1 T5 5 T7 5 T9 3
auto[1] auto[0] 1678 1 T5 4 T7 6 T9 3
auto[1] auto[1] 1837 1 T5 3 T7 7 T9 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%