Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_prev_wr_en 2 0 2 100.00 100 1 1 2
cp_wr_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_prev_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_wr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5411 1 T5 17 T7 19 T9 11
auto[1] 1634 1 T5 3 T7 6 T9 4



Summary for Variable cp_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3496 1 T5 11 T7 10 T9 6
auto[1] 3549 1 T5 9 T7 15 T9 9



Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_wr_encp_prev_wr_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2756 1 T5 9 T7 9 T9 5
auto[0] auto[1] 740 1 T5 2 T7 1 T9 1
auto[1] auto[0] 2655 1 T5 8 T7 10 T9 6
auto[1] auto[1] 894 1 T5 1 T7 5 T9 3

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