Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5314

1

T3

10

T5

2

T6

2

auto[1]

5144

1

T3

8

T5

3

T6

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5632

1

T5

5

T7

5

T9

2

auto[1]

4826

1

T3

18

T6

5

T7

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8350

1

T3

18

T5

3

T6

5

auto[1]

2108

1

T5

2

T7

5

T14

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	2068	1			T3	3		T5	2		T6	1
valid[1]	2079	1			T3	4		T5	1		T6	2
valid[2]	2163	1			T3	5		T7	1		T14	5
valid[3]	2099	1			T3	3		T5	1		T6	1
valid[4]	2049	1			T3	3		T5	1		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	377	1			T14	3		T34	1		T48	1
auto[0]	auto[0]	valid[0]	auto[1]	483	1			T3	1		T7	1		T83	1
auto[0]	auto[0]	valid[1]	auto[0]	352	1			T11	1		T14	3		T48	1
auto[0]	auto[0]	valid[1]	auto[1]	469	1			T3	3		T6	1		T7	1
auto[0]	auto[0]	valid[2]	auto[0]	372	1			T14	1		T15	1		T24	1
auto[0]	auto[0]	valid[2]	auto[1]	525	1			T3	3		T83	3		T146	1
auto[0]	auto[0]	valid[3]	auto[0]	376	1			T5	1		T14	2		T48	1
auto[0]	auto[0]	valid[3]	auto[1]	480	1			T3	1		T6	1		T34	1
auto[0]	auto[0]	valid[4]	auto[0]	342	1			T14	1		T34	2		T29	4
auto[0]	auto[0]	valid[4]	auto[1]	487	1			T3	2		T15	1		T30	2
auto[0]	auto[1]	valid[0]	auto[0]	335	1			T5	1		T14	1		T34	1
auto[0]	auto[1]	valid[0]	auto[1]	457	1			T3	2		T6	1		T7	1
auto[0]	auto[1]	valid[1]	auto[0]	329	1			T9	2		T11	1		T48	3
auto[0]	auto[1]	valid[1]	auto[1]	492	1			T3	1		T6	1		T146	1
auto[0]	auto[1]	valid[2]	auto[0]	350	1			T14	3		T48	1		T29	4
auto[0]	auto[1]	valid[2]	auto[1]	471	1			T3	2		T28	1		T146	2
auto[0]	auto[1]	valid[3]	auto[0]	337	1			T14	1		T15	1		T48	1
auto[0]	auto[1]	valid[3]	auto[1]	483	1			T3	2		T83	2		T146	2
auto[0]	auto[1]	valid[4]	auto[0]	354	1			T5	1		T34	1		T48	1
auto[0]	auto[1]	valid[4]	auto[1]	479	1			T3	1		T6	1		T7	2
auto[1]	auto[0]	valid[0]	auto[0]	215	1			T5	1		T7	2		T290	1
auto[1]	auto[0]	valid[1]	auto[0]	216	1			T14	1		T34	1		T29	2
auto[1]	auto[0]	valid[2]	auto[0]	222	1			T34	1		T48	2		T30	1
auto[1]	auto[0]	valid[3]	auto[0]	213	1			T48	3		T290	1		T30	1
auto[1]	auto[0]	valid[4]	auto[0]	185	1			T48	1		T29	1		T293	1
auto[1]	auto[1]	valid[0]	auto[0]	201	1			T34	1		T290	3		T30	1
auto[1]	auto[1]	valid[1]	auto[0]	221	1			T5	1		T15	1		T48	2
auto[1]	auto[1]	valid[2]	auto[0]	223	1			T7	1		T14	1		T34	1
auto[1]	auto[1]	valid[3]	auto[0]	210	1			T34	1		T48	2		T29	1
auto[1]	auto[1]	valid[4]	auto[0]	202	1			T7	2		T14	1		T15	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal