Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143230

1

T5

54

T7

128

T9

148

auto[1]

50130

1

T3

18

T6

5

T7

49

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141340

1

T3

18

T5

37

T6

5

auto[1]

52020

1

T5

17

T7

62

T9

61

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	99816	1			T3	18		T5	29		T6	5
others[1]	16422	1			T5	6		T7	11		T9	21
others[2]	16401	1			T5	3		T7	16		T9	12
others[3]	18329	1			T5	4		T7	18		T9	15
interest[1]	10685	1			T5	3		T7	7		T9	9
interest[4]	65490	1			T3	18		T5	17		T6	5
interest[64]	31707	1			T5	9		T7	37		T9	31

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	46833	1			T5	22		T7	34		T9	54
auto[0]	auto[0]	others[1]	7788	1			T5	4		T7	4		T9	7
auto[0]	auto[0]	others[2]	7795	1			T5	1		T7	6		T9	3
auto[0]	auto[0]	others[3]	8710	1			T5	3		T7	9		T9	4
auto[0]	auto[0]	interest[1]	5102	1			T5	2		T7	2		T9	5
auto[0]	auto[0]	interest[4]	30513	1			T5	13		T7	23		T9	36
auto[0]	auto[0]	interest[64]	14982	1			T5	5		T7	11		T9	14
auto[0]	auto[1]	others[0]	26255	1			T3	18		T6	5		T7	24
auto[0]	auto[1]	others[1]	4161	1			T7	4		T9	6		T11	1
auto[0]	auto[1]	others[2]	4197	1			T7	5		T9	4		T11	2
auto[0]	auto[1]	others[3]	4623	1			T7	4		T9	7		T11	2
auto[0]	auto[1]	interest[1]	2698	1			T7	1		T9	1		T11	2
auto[0]	auto[1]	interest[4]	17485	1			T3	18		T6	5		T7	14
auto[0]	auto[1]	interest[64]	8196	1			T7	11		T9	10		T11	3
auto[1]	auto[0]	others[0]	26728	1			T5	7		T7	30		T9	34
auto[1]	auto[0]	others[1]	4473	1			T5	2		T7	3		T9	8
auto[1]	auto[0]	others[2]	4409	1			T5	2		T7	5		T9	5
auto[1]	auto[0]	others[3]	4996	1			T5	1		T7	5		T9	4
auto[1]	auto[0]	interest[1]	2885	1			T5	1		T7	4		T9	3
auto[1]	auto[0]	interest[4]	17492	1			T5	4		T7	20		T9	23
auto[1]	auto[0]	interest[64]	8529	1			T5	4		T7	15		T9	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal