Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1605	1			T28	8		T49	11		T53	21
all_values[1]	1605	1			T28	8		T49	11		T53	21
all_values[2]	1605	1			T28	8		T49	11		T53	21
all_values[3]	1605	1			T28	8		T49	11		T53	21
all_values[4]	1605	1			T28	8		T49	11		T53	21
all_values[5]	1605	1			T28	8		T49	11		T53	21
all_values[6]	1605	1			T28	8		T49	11		T53	21
all_values[7]	1605	1			T28	8		T49	11		T53	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6854

1

T28

34

T49

50

T53

86

auto[1]

5986

1

T28

30

T49

38

T53

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5297

1

T28

28

T49

42

T53

72

auto[1]

7543

1

T28

36

T49

46

T53

96

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7474

1

T28

40

T49

57

T53

94

auto[1]

5366

1

T28

24

T49

31

T53

74

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	333	1			T28	1		T49	4		T53	4
all_values[0]	auto[0]	auto[0]	auto[1]	144	1			T28	1		T49	1		T53	3
all_values[0]	auto[0]	auto[1]	auto[0]	289	1			T49	3		T53	4		T136	1
all_values[0]	auto[0]	auto[1]	auto[1]	158	1			T28	2		T53	3		T136	3
all_values[0]	auto[1]	auto[0]	auto[1]	352	1			T28	4		T49	1		T53	3
all_values[0]	auto[1]	auto[1]	auto[1]	329	1			T49	2		T53	4		T136	2
all_values[1]	auto[0]	auto[0]	auto[0]	315	1			T49	3		T53	6		T136	2
all_values[1]	auto[0]	auto[0]	auto[1]	147	1			T28	1		T49	3		T53	1
all_values[1]	auto[0]	auto[1]	auto[0]	293	1			T28	1		T53	2		T152	1
all_values[1]	auto[0]	auto[1]	auto[1]	160	1			T28	1		T49	1		T53	2
all_values[1]	auto[1]	auto[0]	auto[1]	386	1			T28	3		T49	3		T53	3
all_values[1]	auto[1]	auto[1]	auto[1]	304	1			T28	2		T49	1		T53	7
all_values[2]	auto[0]	auto[0]	auto[0]	357	1			T28	5		T49	7		T53	5
all_values[2]	auto[0]	auto[0]	auto[1]	154	1			T152	3		T153	2		T137	2
all_values[2]	auto[0]	auto[1]	auto[0]	290	1			T49	1		T53	7		T136	6
all_values[2]	auto[0]	auto[1]	auto[1]	151	1			T28	1		T53	1		T154	2
all_values[2]	auto[1]	auto[0]	auto[1]	370	1			T28	1		T49	3		T53	5
all_values[2]	auto[1]	auto[1]	auto[1]	283	1			T28	1		T53	3		T152	5
all_values[3]	auto[0]	auto[0]	auto[0]	342	1			T28	2		T49	1		T53	4
all_values[3]	auto[0]	auto[0]	auto[1]	172	1			T28	1		T49	1		T53	2
all_values[3]	auto[0]	auto[1]	auto[0]	280	1			T28	2		T49	2		T53	5
all_values[3]	auto[0]	auto[1]	auto[1]	132	1			T49	1		T120	1		T152	1
all_values[3]	auto[1]	auto[0]	auto[1]	355	1			T28	1		T49	2		T53	9
all_values[3]	auto[1]	auto[1]	auto[1]	324	1			T28	2		T49	4		T53	1
all_values[4]	auto[0]	auto[0]	auto[0]	326	1			T49	3		T53	4		T136	4
all_values[4]	auto[0]	auto[0]	auto[1]	164	1			T28	2		T53	1		T152	1
all_values[4]	auto[0]	auto[1]	auto[0]	282	1			T28	2		T49	3		T53	3
all_values[4]	auto[0]	auto[1]	auto[1]	164	1			T28	2		T49	1		T53	2
all_values[4]	auto[1]	auto[0]	auto[1]	365	1			T49	2		T53	8		T136	1
all_values[4]	auto[1]	auto[1]	auto[1]	304	1			T28	2		T49	2		T53	3
all_values[5]	auto[0]	auto[0]	auto[0]	490	1			T28	1		T49	1		T53	6
all_values[5]	auto[0]	auto[1]	auto[0]	440	1			T28	5		T49	4		T53	7
all_values[5]	auto[1]	auto[0]	auto[1]	358	1			T28	1		T49	3		T53	7
all_values[5]	auto[1]	auto[1]	auto[1]	317	1			T28	1		T49	3		T53	1
all_values[6]	auto[0]	auto[0]	auto[0]	340	1			T28	3		T49	2		T53	4
all_values[6]	auto[0]	auto[0]	auto[1]	160	1			T49	2		T53	1		T120	2
all_values[6]	auto[0]	auto[1]	auto[0]	289	1			T49	4		T53	4		T136	4
all_values[6]	auto[0]	auto[1]	auto[1]	154	1			T28	1		T49	1		T53	3
all_values[6]	auto[1]	auto[0]	auto[1]	359	1			T28	1		T49	1		T53	2
all_values[6]	auto[1]	auto[1]	auto[1]	303	1			T28	3		T49	1		T53	7
all_values[7]	auto[0]	auto[0]	auto[0]	351	1			T28	5		T49	3		T53	1
all_values[7]	auto[0]	auto[0]	auto[1]	152	1			T49	2		T53	1		T152	3
all_values[7]	auto[0]	auto[1]	auto[0]	280	1			T28	1		T49	1		T53	6
all_values[7]	auto[0]	auto[1]	auto[1]	165	1			T49	2		T53	2		T136	2
all_values[7]	auto[1]	auto[0]	auto[1]	362	1			T28	1		T49	2		T53	6
all_values[7]	auto[1]	auto[1]	auto[1]	295	1			T28	1		T49	1		T53	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal