Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
72.73 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 1 4 80.00
Crosses 6 2 4 66.67


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 2 4 66.67 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] 188958 1 T2 23 T3 18 T6 5
auto[PassthroughMode] 147652 1 T5 551 T8 30 T11 865


Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54321 1 T2 23 T8 30 T12 24
auto[1] 282289 1 T3 18 T5 551 T6 5


Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 2 4 66.67 2


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Covered bins
cp_modecp_tpm_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] auto[0] 22800 1 T2 23 T25 145 T151 534
auto[FlashMode] auto[1] 166158 1 T3 18 T6 5 T7 829
auto[PassthroughMode] auto[0] 31521 1 T8 30 T12 24 T13 36
auto[PassthroughMode] auto[1] 116131 1 T5 551 T11 865 T14 713

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%