SPI_DEVICE/1R1W Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.490m 113.995ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.410s 101.837us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.820s 407.469us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 41.190s 26.951ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 16.190s 14.386ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.090s 58.870us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.820s 407.469us 20 20 100.00
spi_device_csr_aliasing 16.190s 14.386ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 13.600us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.910s 48.299us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.900s 31.592us 50 50 100.00
V2 mem_parity spi_device_mem_parity 0.730s 2.428us 0 20 0.00
V2 mem_cfg spi_device_ram_cfg 0.810s 53.862us 20 20 100.00
V2 tpm_read spi_device_tpm_rw 11.320s 574.162us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 11.320s 574.162us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 41.010s 14.263ms 50 50 100.00
spi_device_tpm_sts_read 1.100s 112.943us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.399m 15.270ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 34.380s 12.077ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 37.780s 31.289ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 37.780s 31.289ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 14.750s 3.915ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 14.750s 3.915ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 14.750s 3.915ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 14.750s 3.915ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 14.750s 3.915ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 42.790s 15.190ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.059m 90.438ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.059m 90.438ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.059m 90.438ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.267m 75.304ms 50 50 100.00
spi_device_read_buffer_direct 8.870s 2.513ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.059m 90.438ms 50 50 100.00
spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.148m 97.513ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 9.960s 11.872ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 9.960s 11.872ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.490m 113.995ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 13.438m 111.647ms 47 50 94.00
V2 stress_all spi_device_stress_all 31.815m 1.038s 48 50 96.00
V2 alert_test spi_device_alert_test 0.820s 180.441us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 57.617us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.900s 204.449us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.900s 204.449us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.410s 101.837us 5 5 100.00
spi_device_csr_rw 2.820s 407.469us 20 20 100.00
spi_device_csr_aliasing 16.190s 14.386ms 5 5 100.00
spi_device_same_csr_outstanding 3.910s 382.472us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.410s 101.837us 5 5 100.00
spi_device_csr_rw 2.820s 407.469us 20 20 100.00
spi_device_csr_aliasing 16.190s 14.386ms 5 5 100.00
spi_device_same_csr_outstanding 3.910s 382.472us 20 20 100.00
V2 TOTAL 955 980 97.45
V2S tl_intg_err spi_device_sec_cm 1.180s 304.315us 5 5 100.00
spi_device_tl_intg_err 23.310s 2.064ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 23.310s 2.064ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1095 1120 97.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 19 86.36
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.31 94.34 98.61 89.36 97.00 95.84 98.22

Failure Buckets

Past Results