e3ca274e77
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_device_flash_and_tpm | 12.490m | 113.995ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.410s | 101.837us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_device_csr_rw | 2.820s | 407.469us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_device_csr_bit_bash | 41.190s | 26.951ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_device_csr_aliasing | 16.190s | 14.386ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.090s | 58.870us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.820s | 407.469us | 20 | 20 | 100.00 |
spi_device_csr_aliasing | 16.190s | 14.386ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_device_mem_walk | 0.670s | 13.600us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_device_mem_partial_access | 1.910s | 48.299us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | csb_read | spi_device_csb_read | 0.900s | 31.592us | 50 | 50 | 100.00 |
V2 | mem_parity | spi_device_mem_parity | 0.730s | 2.428us | 0 | 20 | 0.00 |
V2 | mem_cfg | spi_device_ram_cfg | 0.810s | 53.862us | 20 | 20 | 100.00 |
V2 | tpm_read | spi_device_tpm_rw | 11.320s | 574.162us | 50 | 50 | 100.00 |
V2 | tpm_write | spi_device_tpm_rw | 11.320s | 574.162us | 50 | 50 | 100.00 |
V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 41.010s | 14.263ms | 50 | 50 | 100.00 |
spi_device_tpm_sts_read | 1.100s | 112.943us | 50 | 50 | 100.00 | ||
V2 | tpm_fully_random_case | spi_device_tpm_all | 1.399m | 15.270ms | 50 | 50 | 100.00 |
V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 34.380s | 12.077ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 37.780s | 31.289ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 37.780s | 31.289ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_info_slots | spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 |
V2 | cmd_read_status | spi_device_intercept | 14.750s | 3.915ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_jedec | spi_device_intercept | 14.750s | 3.915ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_sfdp | spi_device_intercept | 14.750s | 3.915ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_fast_read | spi_device_intercept | 14.750s | 3.915ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_pipeline | spi_device_intercept | 14.750s | 3.915ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | flash_cmd_upload | spi_device_upload | 42.790s | 15.190ms | 50 | 50 | 100.00 |
V2 | mailbox_command | spi_device_mailbox | 1.059m | 90.438ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.059m | 90.438ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.059m | 90.438ms | 50 | 50 | 100.00 |
V2 | cmd_read_buffer | spi_device_flash_mode | 1.267m | 75.304ms | 50 | 50 | 100.00 |
spi_device_read_buffer_direct | 8.870s | 2.513ms | 50 | 50 | 100.00 | ||
V2 | cmd_dummy_cycle | spi_device_mailbox | 1.059m | 90.438ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 | ||
V2 | quad_spi | spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 |
V2 | dual_spi | spi_device_flash_all | 8.148m | 97.513ms | 50 | 50 | 100.00 |
V2 | 4b_3b_feature | spi_device_cfg_cmd | 9.960s | 11.872ms | 50 | 50 | 100.00 |
V2 | write_enable_disable | spi_device_cfg_cmd | 9.960s | 11.872ms | 50 | 50 | 100.00 |
V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 12.490m | 113.995ms | 50 | 50 | 100.00 |
V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 13.438m | 111.647ms | 47 | 50 | 94.00 |
V2 | stress_all | spi_device_stress_all | 31.815m | 1.038s | 48 | 50 | 96.00 |
V2 | alert_test | spi_device_alert_test | 0.820s | 180.441us | 50 | 50 | 100.00 |
V2 | intr_test | spi_device_intr_test | 0.820s | 57.617us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.900s | 204.449us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_device_tl_errors | 4.900s | 204.449us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.410s | 101.837us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.820s | 407.469us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 16.190s | 14.386ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 3.910s | 382.472us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.410s | 101.837us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.820s | 407.469us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 16.190s | 14.386ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 3.910s | 382.472us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 955 | 980 | 97.45 | |||
V2S | tl_intg_err | spi_device_sec_cm | 1.180s | 304.315us | 5 | 5 | 100.00 |
spi_device_tl_intg_err | 23.310s | 2.064ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.310s | 2.064ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1095 | 1120 | 97.77 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 22 | 22 | 19 | 86.36 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 0 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
95.95 | 98.31 | 94.34 | 98.61 | 89.36 | 97.00 | 95.84 | 98.22 |
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])
has 20 failures:
0.spi_device_mem_parity.20368188255362522844017847268292726679257967412543388763714305174892515083037
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 921877 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[5])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 921877 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 921877 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[901])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.76894489269236455712618858565913966140557069570342832333744933170501202624185
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1601493 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[79])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1601493 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1601493 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[975])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1101) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp *
has 5 failures:
1.spi_device_flash_and_tpm_min_idle.1217989236901429729276425037939160309638428023755541713102240319957627528889
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 62966436920 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
UVM_INFO @ 63377226512 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/13
UVM_INFO @ 68691663976 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/13
UVM_INFO @ 73987665424 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/13
UVM_INFO @ 80559991600 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 12/13
6.spi_device_flash_and_tpm_min_idle.29526860060888792605244821419718952681555108374627908933202955846225967946296
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 5324434973 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
UVM_INFO @ 5879274973 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/17
UVM_INFO @ 5960154973 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/12
UVM_INFO @ 8257205121 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/12
UVM_INFO @ 8420074973 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/17
... and 1 more failures.
11.spi_device_stress_all.24327541399524205486645321631952957719221450209888678002653695275342386965501
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest/run.log
UVM_ERROR @ 26383885422 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
UVM_INFO @ 55420249422 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/17
UVM_INFO @ 107712296390 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/17
UVM_INFO @ 114270858188 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/17
UVM_INFO @ 142884333132 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/17
44.spi_device_stress_all.25574141605042019101913858346346600990779853207110754835566648185091491852358
Line 272, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest/run.log
UVM_ERROR @ 63507041890 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
UVM_INFO @ 66128057864 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/17
UVM_INFO @ 67378600203 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/15
UVM_INFO @ 69867901456 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/17
UVM_INFO @ 76966327072 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/15