Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.23	94.03	67.24			91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul2sram_egress	78.16	94.03	62.07			70.83	85.71
tb.dut.u_tlul2sram_ingress	87.44	94.03	72.41			83.33	100.00

---

Module Instance : tb.dut.u_tlul2sram_egress

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.16	94.03	62.07			70.83	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.34	81.67	59.93			62.50	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	67.62	76.92	68.57			25.00	100.00
u_reqfifo	88.33	95.00	75.00			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	61.36	85.00	45.45			55.00	60.00
u_sram_byte	100.00	100.00
u_sramreqfifo	61.32	82.50	47.22			55.56	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tlul2sram_ingress

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.44	94.03	72.41			83.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.12	85.42	72.66			78.41	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	88.33	95.00	75.00			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	89.32	95.00	77.27			85.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	87.64	95.00	72.22			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
78.16	94.03

tb.dut.u_tlul2sram_egress

	Line No.	Total	Covered	Percent
TOTAL		67	63	94.03
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	433	3	3	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
125	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	0	1
239	1	1
242	1	1
249	1	1
251	1	1
252	1	1
253	0	1
255	1	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
433	1	1
434	1	1
435	1	1
439	1	1
442	1	1
447	1	1
452	0	1

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
87.44	94.03

tb.dut.u_tlul2sram_ingress

	Line No.	Total	Covered	Percent
TOTAL		67	63	94.03
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	433	3	3	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
433	1	1
434	1	1
435	1	1
439	1	1
442	1	1
447	1	1
452	0	1

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
78.16	62.07

tb.dut.u_tlul2sram_egress

	Total	Covered	Percent
Conditions	116	72	62.07
Logical	116	72	62.07
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T2,T3,T4
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T10
1	1	Covered	T2,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
87.44	72.41

tb.dut.u_tlul2sram_ingress

	Total	Covered	Percent
Conditions	116	84	72.41
Logical	116	84	72.41
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T6,T12
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T6,T12

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T2,T6,T12

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T12

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T12

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T6,T12

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T19,T20
1	0	1	Covered	T2,T14,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T6,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T12

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	2	2	100.00
IF	231	4	3	75.00
IF	251	3	3	100.00
IF	357	2	2	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T2,T6,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T2,T6,T12
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T6,T12
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1092775564	1092605942	0	0
DataIntgOptions_A	1842	1842	0	0
ReqOutKnown_A	1092775564	1092605942	0	0
SramDwHasByteGranularity_A	1842	1842	0	0
SramDwIsMultipleOfTlulWidth_A	1842	1842	0	0
TlOutKnown_A	1092775564	1092605942	0	0
TlOutPayloadKnown_A	1092775564	3671394	0	0
TlOutPayloadKnown_AKnownEnable	1092775564	1092605942	0	0
WdataOutKnown_A	1092775564	1092605942	0	0
WeOutKnown_A	1092775564	1092605942	0	0
WmaskOutKnown_A	1092775564	1092605942	0	0
adapterNoReadOrWrite	1842	1842	0	0
rvalidHighReqFifoEmpty	1092775564	208758	0	0
rvalidHighWhenRspFifoFull	1092775564	208758	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1842	1842	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1842	1842	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1842	1842	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	3671394	0	0
T2	1127048	17533	0	0
T3	536052	832	0	0
T4	215154	7096	0	0
T5	1819378	2880	0	0
T6	1952684	17603	0	0
T7	528938	832	0	0
T8	69534	1344	0	0
T9	10858	0	0	0
T10	55402	3863	0	0
T11	232612	832	0	0
T12	0	21760	0	0
T13	0	57	0	0
T14	0	3519	0	0
T16	0	97	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	8053	0	0
T24	0	479	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	1092605942	0	0
T1	2792	2620	0	0
T2	1127048	1126636	0	0
T3	536052	535908	0	0
T4	215154	215140	0	0
T5	1819378	1819228	0	0
T6	1952684	1952666	0	0
T7	528938	528778	0	0
T8	69534	69360	0	0
T9	10858	10588	0	0
T10	55402	55220	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1842	1842	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	208758	0	0
T2	563524	925	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	1795	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T12	0	1792	0	0
T13	0	57	0	0
T14	0	746	0	0
T16	0	34	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	1768	0	0
T24	0	109	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092775564	208758	0	0
T2	563524	925	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	1795	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T12	0	1792	0	0
T13	0	57	0	0
T14	0	746	0	0
T16	0	34	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	1768	0	0
T24	0	109	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress

	Line No.	Total	Covered	Percent
TOTAL		67	63	94.03
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	433	3	3	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
125	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	0	1
239	1	1
242	1	1
249	1	1
251	1	1
252	1	1
253	0	1
255	1	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
433	1	1
434	1	1
435	1	1
439	1	1
442	1	1
447	1	1
452	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress

	Total	Covered	Percent
Conditions	116	72	62.07
Logical	116	72	62.07
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T2,T3,T4
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T10
1	1	Covered	T2,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress

	Line No.	Total	Covered	Percent
Branches		24	17	70.83
TERNARY	107	2	2	100.00
TERNARY	291	2	1	50.00
TERNARY	297	3	1	33.33
TERNARY	324	2	2	100.00
TERNARY	447	2	1	50.00
IF	93	2	2	100.00
IF	231	4	2	50.00
IF	251	3	2	66.67
IF	357	2	2	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	12	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	12	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	546387782	546302971	0	0
DataIntgOptions_A	921	921	0	0
ReqOutKnown_A	546387782	546302971	0	0
SramDwHasByteGranularity_A	921	921	0	0
SramDwIsMultipleOfTlulWidth_A	921	921	0	0
TlOutKnown_A	546387782	546302971	0	0
TlOutPayloadKnown_A	546387782	3209022	0	0
TlOutPayloadKnown_AKnownEnable	546387782	546302971	0	0
WdataOutKnown_A	546387782	546302971	0	0
WeOutKnown_A	546387782	546302971	0	0
WmaskOutKnown_A	546387782	546302971	0	0
adapterNoReadOrWrite	921	921	0	0
rvalidHighReqFifoEmpty	546387782	0	0	0
rvalidHighWhenRspFifoFull	546387782	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	3209022	0	0
T2	563524	13285	0	0
T3	268026	832	0	0
T4	107577	7096	0	0
T5	909689	2880	0	0
T6	976342	15808	0	0
T7	264469	832	0	0
T8	34767	1344	0	0
T9	5429	0	0	0
T10	27701	3863	0	0
T11	116306	832	0	0
T12	0	19968	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress

	Line No.	Total	Covered	Percent
TOTAL		67	63	94.03
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	433	3	3	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
433	1	1
434	1	1
435	1	1
439	1	1
442	1	1
447	1	1
452	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress

	Total	Covered	Percent
Conditions	116	84	72.41
Logical	116	84	72.41
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T6,T12
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T6,T12

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T2,T6,T12

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T12

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T12

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T6,T12

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T19,T20
1	0	1	Covered	T2,T14,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T6,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T12

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Not Covered

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T12

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	2	2	100.00
IF	231	4	2	50.00
IF	251	3	2	66.67
IF	357	2	2	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T2,T6,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T2,T6,T12
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T6,T12
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	546387782	546302971	0	0
DataIntgOptions_A	921	921	0	0
ReqOutKnown_A	546387782	546302971	0	0
SramDwHasByteGranularity_A	921	921	0	0
SramDwIsMultipleOfTlulWidth_A	921	921	0	0
TlOutKnown_A	546387782	546302971	0	0
TlOutPayloadKnown_A	546387782	462372	0	0
TlOutPayloadKnown_AKnownEnable	546387782	546302971	0	0
WdataOutKnown_A	546387782	546302971	0	0
WeOutKnown_A	546387782	546302971	0	0
WmaskOutKnown_A	546387782	546302971	0	0
adapterNoReadOrWrite	921	921	0	0
rvalidHighReqFifoEmpty	546387782	208758	0	0
rvalidHighWhenRspFifoFull	546387782	208758	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	462372	0	0
T2	563524	4248	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	1795	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T12	0	1792	0	0
T13	0	57	0	0
T14	0	3519	0	0
T16	0	97	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	8053	0	0
T24	0	479	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	546302971	0	0
T1	1396	1310	0	0
T2	563524	563318	0	0
T3	268026	267954	0	0
T4	107577	107570	0	0
T5	909689	909614	0	0
T6	976342	976333	0	0
T7	264469	264389	0	0
T8	34767	34680	0	0
T9	5429	5294	0	0
T10	27701	27610	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	921	921	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	208758	0	0
T2	563524	925	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	1795	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T12	0	1792	0	0
T13	0	57	0	0
T14	0	746	0	0
T16	0	34	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	1768	0	0
T24	0	109	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	546387782	208758	0	0
T2	563524	925	0	0
T3	268026	0	0	0
T4	107577	0	0	0
T5	909689	0	0	0
T6	976342	1795	0	0
T7	264469	0	0	0
T8	34767	0	0	0
T9	5429	0	0	0
T10	27701	0	0	0
T11	116306	0	0	0
T12	0	1792	0	0
T13	0	57	0	0
T14	0	746	0	0
T16	0	34	0	0
T21	0	695	0	0
T22	0	61	0	0
T23	0	1768	0	0
T24	0	109	0	0