Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.03	90.27	78.43	96.94		78.12	86.36	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	656	656	0	0
OutputsKnown_A	113744254	113685586	0	0
gen_no_flops.OutputDelay_A	113744254	113685586	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656	656	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0