Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	90.27	78.43	96.94		78.12	86.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.03	90.27	78.43	96.94		78.12	86.36

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	90.27	78.43	96.94		78.12	86.36

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.77	97.50	92.83	98.61	80.85	95.89	90.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	90.44	94.44	86.59		87.50	83.67	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	97.92	100.00	91.67			100.00	100.00
u_intr_payload_not_empty	97.92	100.00	91.67			100.00	100.00
u_intr_payload_overflow	97.92	100.00	91.67			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.73	100.00	71.43			67.50	100.00
u_passthrough	89.42	92.20	88.24		75.00	91.67	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.12	93.62	89.40		87.50	84.15	90.91
u_reg	99.65	99.53	99.35	100.00		99.35	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.68	99.28	84.99		91.67	95.32	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	93.75	100.00	75.00			100.00	100.00
u_spid_status	96.98	96.95	97.83			93.15	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	88.46	100.00	76.47			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.25	81.97	59.04			63.33	80.65
u_tlul2sram_ingress	83.85	85.66	70.85			78.89	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	42.60	82.94	34.96		0.00	61.18	33.93

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		226	204	90.27
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
ALWAYS	568	0	0
ALWAYS	568	2	2	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	582	0	0
ALWAYS	582	12	12	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	784	3	3	100.00
ALWAYS	790	8	6	75.00
ALWAYS	828	9	9	100.00
ALWAYS	852	24	20	83.33
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	963	5	3	60.00
ALWAYS	974	13	13	100.00
ALWAYS	1011	3	3	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1154	1	1	100.00
CONT_ASSIGN	1155	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1158	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1162	1	1	100.00
CONT_ASSIGN	1208	1	0	0.00
CONT_ASSIGN	1238	1	0	0.00
CONT_ASSIGN	1321	1	0	0.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1327	1	0	0.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1338	1	0	0.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1341	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
CONT_ASSIGN	1508	1	0	0.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1517	1	1	100.00
CONT_ASSIGN	1518	1	1	100.00
CONT_ASSIGN	1519	1	1	100.00
CONT_ASSIGN	1520	1	1	100.00
CONT_ASSIGN	1523	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1541	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1544	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
ALWAYS	1638	4	4	100.00
ALWAYS	1647	0	0
ALWAYS	1647	9	9	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1665	1	1	100.00
CONT_ASSIGN	1665	1	1	100.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1666	1	1	100.00
CONT_ASSIGN	1666	1	1	100.00
CONT_ASSIGN	1666	1	0	0.00
CONT_ASSIGN	1666	1	0	0.00
CONT_ASSIGN	1666	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	0	0.00
CONT_ASSIGN	1667	1	0	0.00
CONT_ASSIGN	1667	1	0	0.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1712	1	1	100.00
CONT_ASSIGN	1714	1	1	100.00
CONT_ASSIGN	1715	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1717	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
CONT_ASSIGN	1720	1	1	100.00
CONT_ASSIGN	1721	1	1	100.00
CONT_ASSIGN	1722	1	1	100.00
CONT_ASSIGN	1778	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
308	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
393	1	1
526	1	1
533	1	1
535	1	1
538	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
546	1	1
552	1	1
553	1	1
558	1	1
559	1	1
563	1	1
568	1	1
569	1	1
573	1	1
574	1	1
582	1	1
583	1	1
602	1	1
603	1	1
607	1	1
608	1	1
610	1	1
611	1	1
613	1	1
614	1	1
616	1	1
617	1	1
646	1	1
647	1	1
648	1	1
784	2	2
785	1	1
790	1	1
792	1	1
793	1	1
800	1	1
804	1	1
805	1	1
809	0	1
810	0	1
828	1	1
830	1	1
835	1	1
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
846	1	1
			MISSING_ELSE
852	1	1
853	1	1
854	1	1
855	1	1
857	1	1
859	1	1
861	1	1
863	1	1
867	1	1
869	1	1
870	1	1
871	1	1
874	1	1
876	1	1
877	1	1
878	1	1
883	1	1
885	1	1
886	1	1
887	1	1
891	0	1
893	0	1
894	0	1
895	0	1
919	1	1
920	1	1
963	1	1
964	0	1
965	0	1
967	1	1
968	1	1
974	1	1
975	1	1
977	1	1
979	1	1
980	1	1
984	1	1
986	1	1
987	1	1
991	1	1
992	1	1
993	1	1
995	1	1
996	1	1
1011	2	2
1012	1	1
1147	1	1
1150	1	1
1154	1	1
1155	1	1
1156	1	1
1158	1	1
1159	1	1
1162	1	1
1208	0	1
1238	0	1
1321	0	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1327	0	1
1331	1	1
1338	0	1
1339	1	1
1341	1	1
1345	1	1
1348	1	1
1351	1	1
1354	1	1
1357	1	1
1360	1	1
1367	1	1
1368	1	1
1407	1	1
1508	0	1
1516	1	1
1517	1	1
1518	1	1
1519	1	1
1520	1	1
1523	1	1
1530	1	1
1537	5	5
1540	1	1
1541	1	1
1542	1	1
1543	1	1
1544	1	1
1545	1	1
1547	1	1
1551	1	1
1553	1	1
1554	1	1
1561	1	1
1563	1	1
1564	1	1
1573	1	1
1574	1	1
1575	1	1
1576	1	1
1631	1	1
1633	1	1
1638	1	1
1639	1	1
1640	1	1
1641	1	1
			MISSING_ELSE
1647	1	1
1648	1	1
1650	1	1
1653	1	1
1654	1	1
1655	1	1
1656	1	1
1658	1	1
1659	1	1
1664	5	5
1665	2	5
1666	3	5
1667	2	5
1669	5	5
1670	5	5
1671	5	5
1712	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1718	1	1
1720	1	1
1721	1	1
1722	1	1
1778	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	40	78.43
Logical	51	40	78.43
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       701
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       712
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T13

 LINE       814
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       841
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       977
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T21
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       1147
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T8

 LINE       1158
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1159
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       1367
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T29

 LINE       1368
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T28

 LINE       1530
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T18,T19

 LINE       1640
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1640
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1640
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1712
 EXPRESSION (tpm_rst_n | rst_spi_n)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T13

 LINE       1778
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T32

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T21,T33,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T16,T5,T32	Yes	T16,T5,T32	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T16,T4	Yes	T2,T16,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T16	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T5,T12	Yes	T3,T5,T12	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T16	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T16	Yes	T1,T2,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T17,T32	Yes	T16,T17,T32	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T17,T32	Yes	T16,T17,T32	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
cio_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sd_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
cio_tpm_csb_i	Yes	Yes	T3,T12,T13	Yes	T3,T12,T13	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T35,T36,T38	Yes	T1,T2,T4	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T21,T39,T40	Yes	T21,T39,T40	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T21,T34,T39	Yes	T21,T34,T39	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T41	Yes	T41	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T41	Yes	T41	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	25	78.12
IF	538	3	3	100.00
IF	784	2	2	100.00
CASE	800	4	2	50.00
IF	841	3	3	100.00
CASE	857	7	4	57.14
IF	963	2	1	50.00
IF	977	5	4	80.00
IF	1011	2	2	100.00
IF	1640	2	2	100.00
IF	1650	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	538	if ((!rst_ni))
-2-:	540	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	784	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	800	case (cmd_dp_sel)
-2-:	814	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T1,T2,T4
DpUpload	-	Not Covered
default	1	Not Covered
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	841	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	844	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	857	case (spi_mode)
-2-:	859	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T1,T2,T4
FlashMode PassThrough	DpReadStatus	Covered	T5,T9,T42
FlashMode PassThrough	DpReadJEDEC	Covered	T5,T42,T43
FlashMode PassThrough	DpUpload	Not Covered
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	963	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	977	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	984	case (spi_mode)
-3-:	991	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T12,T13,T14
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T5,T7,T9
0	PassThrough	0	Covered	T1,T2,T4
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1011	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	1640	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1650	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	19	86.36
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	19	86.36

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	113744254	113685586	0	0
CioSdoEnOKnown	113744254	113685586	0	0
CioSdoEnOffWhenInactive	113744254	113685586	0	0
FpvSecCmRegWeOnehotCheck_A	113744254	100	0	0
InterceptLevel_M	39756675	0	0	0
IntrReadbufFlipOKnown	113744254	113685586	0	0
IntrReadbufWatermarkOKnown	113744254	113685586	0	0
IntrTpmHeaderNotEmptyOKnown	113744254	113685586	0	0
IntrTpmRdfifoCmdEndOKnown	113744254	113685586	0	0
IntrTpmRdfifoDropOKnown	113744254	113685586	0	0
IntrUploadCmdfifoNotEmptyOKnown	113744254	113685586	0	0
IntrUploadPayloadNotEmptyOKnown	113744254	113685586	0	0
IntrUploadPayloadOverflowOKnown	113744254	113685586	0	0
PayloadStartIdxWidthMatch_A	656	656	0	0
SpiModeKnown_A	113744254	113685586	0	0
TpmEnableWhenTpmCsbIdle_M	113744254	200	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	113744254	346752	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	113744254	44867	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	113744254	0	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	113744254	0	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	113744254	74580	0	0
scanmodeKnown	113744254	113744254	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	100	0	0
T44	5968	20	0	0
T45	0	10	0	0
T46	0	10	0	0
T47	0	30	0	0
T48	0	30	0	0
T49	4629	0	0	0
T50	11224	0	0	0
T51	1878	0	0	0
T52	45778	0	0	0
T53	806032	0	0	0
T54	134940	0	0	0
T55	9907	0	0	0
T56	8033	0	0	0
T57	349280	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756675	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656	656	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	200	0	0
T6	534240	0	0	0
T7	38306	0	0	0
T8	101192	0	0	0
T9	148545	0	0	0
T12	76052	1	0	0
T13	8805	1	0	0
T14	51829	1	0	0
T15	5904	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	2031	0	0	0
T23	0	1	0	0
T32	1244	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	346752	0	0
T1	34015	832	0	0
T2	758407	832	0	0
T3	1861	0	0	0
T4	905554	832	0	0
T5	30531	832	0	0
T6	534240	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T11	0	832	0	0
T12	76052	0	0	0
T13	8805	0	0	0
T16	994	0	0	0
T17	711	0	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	44867	0	0
T6	534240	0	0	0
T7	38306	0	0	0
T8	101192	0	0	0
T9	148545	0	0	0
T12	76052	414	0	0
T13	8805	0	0	0
T14	51829	0	0	0
T15	5904	0	0	0
T18	0	977	0	0
T19	0	36	0	0
T20	2031	0	0	0
T32	1244	0	0	0
T58	0	1688	0	0
T60	0	350	0	0
T61	0	861	0	0
T62	0	1357	0	0
T63	0	17	0	0
T64	0	477	0	0
T65	0	10	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	74580	0	0
T6	534240	0	0	0
T7	38306	0	0	0
T8	101192	0	0	0
T9	148545	0	0	0
T12	76052	632	0	0
T13	8805	0	0	0
T14	51829	0	0	0
T15	5904	0	0	0
T18	0	2199	0	0
T19	0	22	0	0
T20	2031	0	0	0
T32	1244	0	0	0
T58	0	2146	0	0
T60	0	706	0	0
T61	0	1949	0	0
T62	0	2931	0	0
T63	0	30	0	0
T64	0	885	0	0
T65	0	52	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113744254	0	0
T1	34015	34015	0	0
T2	758407	758407	0	0
T3	1861	1861	0	0
T4	905554	905554	0	0
T5	30531	30531	0	0
T6	534240	534240	0	0
T12	76052	76052	0	0
T13	8805	8805	0	0
T16	994	994	0	0
T17	711	711	0	0