Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3362 |
0 |
0 |
T35 |
94181 |
2 |
0 |
0 |
T36 |
55082 |
3 |
0 |
0 |
T37 |
11102 |
181 |
0 |
0 |
T108 |
4551 |
167 |
0 |
0 |
T109 |
4819 |
4 |
0 |
0 |
T114 |
18338 |
4 |
0 |
0 |
T115 |
7008 |
250 |
0 |
0 |
T120 |
11345 |
163 |
0 |
0 |
T124 |
12534 |
7 |
0 |
0 |
T127 |
30351 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3818 |
0 |
0 |
T35 |
94181 |
67 |
0 |
0 |
T125 |
156702 |
269 |
0 |
0 |
T128 |
94822 |
97 |
0 |
0 |
T132 |
122496 |
733 |
0 |
0 |
T133 |
181070 |
460 |
0 |
0 |
T135 |
36576 |
237 |
0 |
0 |
T146 |
18597 |
37 |
0 |
0 |
T155 |
82952 |
558 |
0 |
0 |
T156 |
105771 |
129 |
0 |
0 |
T157 |
13532 |
40 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3804 |
0 |
0 |
T35 |
94181 |
63 |
0 |
0 |
T125 |
156702 |
242 |
0 |
0 |
T128 |
94822 |
96 |
0 |
0 |
T132 |
122496 |
725 |
0 |
0 |
T133 |
181070 |
430 |
0 |
0 |
T135 |
36576 |
215 |
0 |
0 |
T146 |
18597 |
9 |
0 |
0 |
T155 |
82952 |
547 |
0 |
0 |
T156 |
105771 |
109 |
0 |
0 |
T157 |
13532 |
23 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4391 |
0 |
0 |
T35 |
94181 |
107 |
0 |
0 |
T125 |
156702 |
275 |
0 |
0 |
T128 |
94822 |
205 |
0 |
0 |
T132 |
122496 |
722 |
0 |
0 |
T133 |
181070 |
471 |
0 |
0 |
T135 |
36576 |
215 |
0 |
0 |
T146 |
18597 |
35 |
0 |
0 |
T155 |
82952 |
493 |
0 |
0 |
T156 |
105771 |
266 |
0 |
0 |
T157 |
13532 |
24 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
10167 |
0 |
0 |
T35 |
94181 |
971 |
0 |
0 |
T125 |
156702 |
270 |
0 |
0 |
T128 |
94822 |
1378 |
0 |
0 |
T132 |
122496 |
744 |
0 |
0 |
T133 |
181070 |
395 |
0 |
0 |
T135 |
36576 |
263 |
0 |
0 |
T146 |
18597 |
21 |
0 |
0 |
T155 |
82952 |
499 |
0 |
0 |
T156 |
105771 |
1835 |
0 |
0 |
T157 |
13532 |
39 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
10054 |
0 |
0 |
T35 |
94181 |
754 |
0 |
0 |
T125 |
156702 |
256 |
0 |
0 |
T128 |
94822 |
2005 |
0 |
0 |
T132 |
122496 |
803 |
0 |
0 |
T133 |
181070 |
398 |
0 |
0 |
T135 |
36576 |
215 |
0 |
0 |
T146 |
18597 |
12 |
0 |
0 |
T155 |
82952 |
532 |
0 |
0 |
T156 |
105771 |
1284 |
0 |
0 |
T157 |
13532 |
18 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
9777 |
0 |
0 |
T35 |
94181 |
1069 |
0 |
0 |
T125 |
156702 |
263 |
0 |
0 |
T128 |
94822 |
1785 |
0 |
0 |
T132 |
122496 |
724 |
0 |
0 |
T133 |
181070 |
445 |
0 |
0 |
T135 |
36576 |
233 |
0 |
0 |
T146 |
18597 |
25 |
0 |
0 |
T155 |
82952 |
530 |
0 |
0 |
T156 |
105771 |
1437 |
0 |
0 |
T157 |
13532 |
12 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
10648 |
0 |
0 |
T35 |
94181 |
898 |
0 |
0 |
T125 |
156702 |
304 |
0 |
0 |
T128 |
94822 |
1557 |
0 |
0 |
T132 |
122496 |
779 |
0 |
0 |
T133 |
181070 |
434 |
0 |
0 |
T135 |
36576 |
261 |
0 |
0 |
T146 |
18597 |
32 |
0 |
0 |
T155 |
82952 |
509 |
0 |
0 |
T156 |
105771 |
2120 |
0 |
0 |
T157 |
13532 |
4 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
9949 |
0 |
0 |
T35 |
94181 |
983 |
0 |
0 |
T125 |
156702 |
203 |
0 |
0 |
T128 |
94822 |
1347 |
0 |
0 |
T132 |
122496 |
730 |
0 |
0 |
T133 |
181070 |
403 |
0 |
0 |
T135 |
36576 |
234 |
0 |
0 |
T146 |
18597 |
23 |
0 |
0 |
T155 |
82952 |
477 |
0 |
0 |
T156 |
105771 |
1732 |
0 |
0 |
T157 |
13532 |
73 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
10139 |
0 |
0 |
T35 |
94181 |
975 |
0 |
0 |
T125 |
156702 |
253 |
0 |
0 |
T128 |
94822 |
1690 |
0 |
0 |
T132 |
122496 |
739 |
0 |
0 |
T133 |
181070 |
428 |
0 |
0 |
T135 |
36576 |
222 |
0 |
0 |
T146 |
18597 |
40 |
0 |
0 |
T155 |
82952 |
506 |
0 |
0 |
T156 |
105771 |
2007 |
0 |
0 |
T157 |
13532 |
28 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
11403 |
0 |
0 |
T35 |
94181 |
868 |
0 |
0 |
T125 |
156702 |
259 |
0 |
0 |
T128 |
94822 |
1748 |
0 |
0 |
T132 |
122496 |
800 |
0 |
0 |
T133 |
181070 |
458 |
0 |
0 |
T135 |
36576 |
215 |
0 |
0 |
T146 |
18597 |
21 |
0 |
0 |
T155 |
82952 |
607 |
0 |
0 |
T156 |
105771 |
2215 |
0 |
0 |
T157 |
13532 |
57 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
11618 |
0 |
0 |
T35 |
94181 |
1191 |
0 |
0 |
T125 |
156702 |
317 |
0 |
0 |
T128 |
94822 |
1802 |
0 |
0 |
T132 |
122496 |
750 |
0 |
0 |
T133 |
181070 |
414 |
0 |
0 |
T135 |
36576 |
230 |
0 |
0 |
T146 |
18597 |
72 |
0 |
0 |
T155 |
82952 |
545 |
0 |
0 |
T156 |
105771 |
2276 |
0 |
0 |
T157 |
13532 |
9 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6455 |
0 |
0 |
T35 |
94181 |
354 |
0 |
0 |
T125 |
156702 |
280 |
0 |
0 |
T128 |
94822 |
961 |
0 |
0 |
T132 |
122496 |
726 |
0 |
0 |
T133 |
181070 |
386 |
0 |
0 |
T135 |
36576 |
201 |
0 |
0 |
T146 |
18597 |
9 |
0 |
0 |
T155 |
82952 |
579 |
0 |
0 |
T156 |
105771 |
836 |
0 |
0 |
T157 |
13532 |
29 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6607 |
0 |
0 |
T35 |
94181 |
371 |
0 |
0 |
T125 |
156702 |
265 |
0 |
0 |
T128 |
94822 |
910 |
0 |
0 |
T132 |
122496 |
730 |
0 |
0 |
T133 |
181070 |
411 |
0 |
0 |
T135 |
36576 |
262 |
0 |
0 |
T146 |
18597 |
47 |
0 |
0 |
T155 |
82952 |
482 |
0 |
0 |
T156 |
105771 |
982 |
0 |
0 |
T157 |
13532 |
29 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6407 |
0 |
0 |
T35 |
94181 |
424 |
0 |
0 |
T125 |
156702 |
287 |
0 |
0 |
T128 |
94822 |
670 |
0 |
0 |
T132 |
122496 |
839 |
0 |
0 |
T133 |
181070 |
411 |
0 |
0 |
T135 |
36576 |
251 |
0 |
0 |
T146 |
18597 |
33 |
0 |
0 |
T155 |
82952 |
561 |
0 |
0 |
T156 |
105771 |
798 |
0 |
0 |
T157 |
13532 |
22 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6303 |
0 |
0 |
T35 |
94181 |
321 |
0 |
0 |
T125 |
156702 |
257 |
0 |
0 |
T128 |
94822 |
797 |
0 |
0 |
T132 |
122496 |
791 |
0 |
0 |
T133 |
181070 |
459 |
0 |
0 |
T135 |
36576 |
225 |
0 |
0 |
T146 |
18597 |
57 |
0 |
0 |
T155 |
82952 |
515 |
0 |
0 |
T156 |
105771 |
654 |
0 |
0 |
T157 |
13532 |
42 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6888 |
0 |
0 |
T35 |
94181 |
475 |
0 |
0 |
T125 |
156702 |
307 |
0 |
0 |
T128 |
94822 |
893 |
0 |
0 |
T132 |
122496 |
812 |
0 |
0 |
T133 |
181070 |
497 |
0 |
0 |
T135 |
36576 |
225 |
0 |
0 |
T146 |
18597 |
52 |
0 |
0 |
T155 |
82952 |
532 |
0 |
0 |
T156 |
105771 |
660 |
0 |
0 |
T157 |
13532 |
78 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6173 |
0 |
0 |
T35 |
94181 |
514 |
0 |
0 |
T125 |
156702 |
216 |
0 |
0 |
T128 |
94822 |
542 |
0 |
0 |
T132 |
122496 |
777 |
0 |
0 |
T133 |
181070 |
442 |
0 |
0 |
T135 |
36576 |
226 |
0 |
0 |
T146 |
18597 |
22 |
0 |
0 |
T155 |
82952 |
481 |
0 |
0 |
T156 |
105771 |
768 |
0 |
0 |
T157 |
13532 |
15 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6354 |
0 |
0 |
T35 |
94181 |
509 |
0 |
0 |
T125 |
156702 |
232 |
0 |
0 |
T128 |
94822 |
712 |
0 |
0 |
T132 |
122496 |
736 |
0 |
0 |
T133 |
181070 |
413 |
0 |
0 |
T135 |
36576 |
228 |
0 |
0 |
T146 |
18597 |
42 |
0 |
0 |
T155 |
82952 |
544 |
0 |
0 |
T156 |
105771 |
641 |
0 |
0 |
T157 |
13532 |
67 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6335 |
0 |
0 |
T35 |
94181 |
437 |
0 |
0 |
T125 |
156702 |
307 |
0 |
0 |
T128 |
94822 |
740 |
0 |
0 |
T132 |
122496 |
765 |
0 |
0 |
T133 |
181070 |
429 |
0 |
0 |
T135 |
36576 |
257 |
0 |
0 |
T146 |
18597 |
28 |
0 |
0 |
T155 |
82952 |
558 |
0 |
0 |
T156 |
105771 |
613 |
0 |
0 |
T157 |
13532 |
42 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6440 |
0 |
0 |
T35 |
94181 |
412 |
0 |
0 |
T125 |
156702 |
246 |
0 |
0 |
T128 |
94822 |
540 |
0 |
0 |
T132 |
122496 |
792 |
0 |
0 |
T133 |
181070 |
482 |
0 |
0 |
T135 |
36576 |
232 |
0 |
0 |
T146 |
18597 |
45 |
0 |
0 |
T155 |
82952 |
564 |
0 |
0 |
T156 |
105771 |
782 |
0 |
0 |
T157 |
13532 |
14 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6477 |
0 |
0 |
T35 |
94181 |
505 |
0 |
0 |
T125 |
156702 |
241 |
0 |
0 |
T128 |
94822 |
765 |
0 |
0 |
T132 |
122496 |
754 |
0 |
0 |
T133 |
181070 |
448 |
0 |
0 |
T135 |
36576 |
210 |
0 |
0 |
T146 |
18597 |
31 |
0 |
0 |
T155 |
82952 |
535 |
0 |
0 |
T156 |
105771 |
891 |
0 |
0 |
T157 |
13532 |
27 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6182 |
0 |
0 |
T35 |
94181 |
404 |
0 |
0 |
T125 |
156702 |
250 |
0 |
0 |
T128 |
94822 |
842 |
0 |
0 |
T132 |
122496 |
687 |
0 |
0 |
T133 |
181070 |
440 |
0 |
0 |
T135 |
36576 |
240 |
0 |
0 |
T146 |
18597 |
14 |
0 |
0 |
T155 |
82952 |
514 |
0 |
0 |
T156 |
105771 |
798 |
0 |
0 |
T157 |
13532 |
55 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6004 |
0 |
0 |
T35 |
94181 |
352 |
0 |
0 |
T125 |
156702 |
251 |
0 |
0 |
T128 |
94822 |
696 |
0 |
0 |
T132 |
122496 |
823 |
0 |
0 |
T133 |
181070 |
429 |
0 |
0 |
T135 |
36576 |
235 |
0 |
0 |
T146 |
18597 |
26 |
0 |
0 |
T155 |
82952 |
472 |
0 |
0 |
T156 |
105771 |
600 |
0 |
0 |
T157 |
13532 |
53 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6425 |
0 |
0 |
T35 |
94181 |
461 |
0 |
0 |
T125 |
156702 |
298 |
0 |
0 |
T128 |
94822 |
707 |
0 |
0 |
T132 |
122496 |
832 |
0 |
0 |
T133 |
181070 |
475 |
0 |
0 |
T135 |
36576 |
237 |
0 |
0 |
T146 |
18597 |
94 |
0 |
0 |
T155 |
82952 |
511 |
0 |
0 |
T156 |
105771 |
541 |
0 |
0 |
T157 |
13532 |
26 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6232 |
0 |
0 |
T35 |
94181 |
454 |
0 |
0 |
T125 |
156702 |
273 |
0 |
0 |
T128 |
94822 |
780 |
0 |
0 |
T132 |
122496 |
871 |
0 |
0 |
T133 |
181070 |
439 |
0 |
0 |
T135 |
36576 |
195 |
0 |
0 |
T146 |
18597 |
29 |
0 |
0 |
T155 |
82952 |
509 |
0 |
0 |
T156 |
105771 |
744 |
0 |
0 |
T157 |
13532 |
62 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6799 |
0 |
0 |
T35 |
94181 |
386 |
0 |
0 |
T125 |
156702 |
313 |
0 |
0 |
T128 |
94822 |
978 |
0 |
0 |
T132 |
122496 |
814 |
0 |
0 |
T133 |
181070 |
391 |
0 |
0 |
T135 |
36576 |
248 |
0 |
0 |
T146 |
18597 |
19 |
0 |
0 |
T155 |
82952 |
489 |
0 |
0 |
T156 |
105771 |
989 |
0 |
0 |
T157 |
13532 |
50 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6558 |
0 |
0 |
T35 |
94181 |
350 |
0 |
0 |
T125 |
156702 |
255 |
0 |
0 |
T128 |
94822 |
930 |
0 |
0 |
T132 |
122496 |
798 |
0 |
0 |
T133 |
181070 |
487 |
0 |
0 |
T135 |
36576 |
244 |
0 |
0 |
T146 |
18597 |
44 |
0 |
0 |
T155 |
82952 |
551 |
0 |
0 |
T156 |
105771 |
844 |
0 |
0 |
T157 |
13532 |
2 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6784 |
0 |
0 |
T35 |
94181 |
370 |
0 |
0 |
T125 |
156702 |
239 |
0 |
0 |
T128 |
94822 |
821 |
0 |
0 |
T132 |
122496 |
813 |
0 |
0 |
T133 |
181070 |
466 |
0 |
0 |
T135 |
36576 |
280 |
0 |
0 |
T146 |
18597 |
43 |
0 |
0 |
T155 |
82952 |
527 |
0 |
0 |
T156 |
105771 |
912 |
0 |
0 |
T157 |
13532 |
76 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6080 |
0 |
0 |
T35 |
94181 |
378 |
0 |
0 |
T125 |
156702 |
227 |
0 |
0 |
T128 |
94822 |
588 |
0 |
0 |
T132 |
122496 |
756 |
0 |
0 |
T133 |
181070 |
456 |
0 |
0 |
T135 |
36576 |
280 |
0 |
0 |
T146 |
18597 |
30 |
0 |
0 |
T155 |
82952 |
491 |
0 |
0 |
T156 |
105771 |
698 |
0 |
0 |
T157 |
13532 |
36 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6642 |
0 |
0 |
T35 |
94181 |
508 |
0 |
0 |
T125 |
156702 |
258 |
0 |
0 |
T128 |
94822 |
747 |
0 |
0 |
T132 |
122496 |
740 |
0 |
0 |
T133 |
181070 |
482 |
0 |
0 |
T135 |
36576 |
190 |
0 |
0 |
T146 |
18597 |
77 |
0 |
0 |
T155 |
82952 |
547 |
0 |
0 |
T156 |
105771 |
740 |
0 |
0 |
T157 |
13532 |
103 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6890 |
0 |
0 |
T35 |
94181 |
569 |
0 |
0 |
T125 |
156702 |
276 |
0 |
0 |
T128 |
94822 |
867 |
0 |
0 |
T132 |
122496 |
780 |
0 |
0 |
T133 |
181070 |
415 |
0 |
0 |
T135 |
36576 |
233 |
0 |
0 |
T146 |
18597 |
43 |
0 |
0 |
T155 |
82952 |
528 |
0 |
0 |
T156 |
105771 |
1117 |
0 |
0 |
T157 |
13532 |
53 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6441 |
0 |
0 |
T35 |
94181 |
533 |
0 |
0 |
T125 |
156702 |
300 |
0 |
0 |
T128 |
94822 |
849 |
0 |
0 |
T132 |
122496 |
707 |
0 |
0 |
T133 |
181070 |
489 |
0 |
0 |
T135 |
36576 |
225 |
0 |
0 |
T146 |
18597 |
23 |
0 |
0 |
T155 |
82952 |
461 |
0 |
0 |
T156 |
105771 |
824 |
0 |
0 |
T157 |
13532 |
46 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6428 |
0 |
0 |
T35 |
94181 |
344 |
0 |
0 |
T125 |
156702 |
261 |
0 |
0 |
T128 |
94822 |
813 |
0 |
0 |
T132 |
122496 |
779 |
0 |
0 |
T133 |
181070 |
452 |
0 |
0 |
T135 |
36576 |
230 |
0 |
0 |
T146 |
18597 |
28 |
0 |
0 |
T155 |
82952 |
563 |
0 |
0 |
T156 |
105771 |
780 |
0 |
0 |
T157 |
13532 |
50 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6192 |
0 |
0 |
T35 |
94181 |
407 |
0 |
0 |
T125 |
156702 |
256 |
0 |
0 |
T128 |
94822 |
647 |
0 |
0 |
T132 |
122496 |
808 |
0 |
0 |
T133 |
181070 |
502 |
0 |
0 |
T135 |
36576 |
229 |
0 |
0 |
T146 |
18597 |
30 |
0 |
0 |
T155 |
82952 |
495 |
0 |
0 |
T156 |
105771 |
639 |
0 |
0 |
T157 |
13532 |
66 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
6461 |
0 |
0 |
T35 |
94181 |
394 |
0 |
0 |
T125 |
156702 |
281 |
0 |
0 |
T128 |
94822 |
686 |
0 |
0 |
T132 |
122496 |
739 |
0 |
0 |
T133 |
181070 |
411 |
0 |
0 |
T135 |
36576 |
191 |
0 |
0 |
T146 |
18597 |
68 |
0 |
0 |
T155 |
82952 |
513 |
0 |
0 |
T156 |
105771 |
795 |
0 |
0 |
T157 |
13532 |
66 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3944 |
0 |
0 |
T35 |
94181 |
95 |
0 |
0 |
T125 |
156702 |
246 |
0 |
0 |
T128 |
94822 |
164 |
0 |
0 |
T132 |
122496 |
765 |
0 |
0 |
T133 |
181070 |
527 |
0 |
0 |
T135 |
36576 |
176 |
0 |
0 |
T146 |
18597 |
34 |
0 |
0 |
T155 |
82952 |
455 |
0 |
0 |
T156 |
105771 |
154 |
0 |
0 |
T157 |
13532 |
10 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3922 |
0 |
0 |
T35 |
94181 |
121 |
0 |
0 |
T125 |
156702 |
287 |
0 |
0 |
T128 |
94822 |
134 |
0 |
0 |
T132 |
122496 |
713 |
0 |
0 |
T133 |
181070 |
447 |
0 |
0 |
T135 |
36576 |
250 |
0 |
0 |
T146 |
18597 |
39 |
0 |
0 |
T155 |
82952 |
491 |
0 |
0 |
T156 |
105771 |
178 |
0 |
0 |
T157 |
13532 |
51 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3937 |
0 |
0 |
T35 |
94181 |
74 |
0 |
0 |
T125 |
156702 |
262 |
0 |
0 |
T128 |
94822 |
146 |
0 |
0 |
T132 |
122496 |
777 |
0 |
0 |
T133 |
181070 |
440 |
0 |
0 |
T135 |
36576 |
234 |
0 |
0 |
T146 |
18597 |
46 |
0 |
0 |
T155 |
82952 |
534 |
0 |
0 |
T156 |
105771 |
182 |
0 |
0 |
T157 |
13532 |
23 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4131 |
0 |
0 |
T35 |
94181 |
74 |
0 |
0 |
T125 |
156702 |
243 |
0 |
0 |
T128 |
94822 |
229 |
0 |
0 |
T132 |
122496 |
767 |
0 |
0 |
T133 |
181070 |
499 |
0 |
0 |
T135 |
36576 |
191 |
0 |
0 |
T146 |
18597 |
47 |
0 |
0 |
T155 |
82952 |
517 |
0 |
0 |
T156 |
105771 |
176 |
0 |
0 |
T157 |
13532 |
41 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4384 |
0 |
0 |
T35 |
94181 |
174 |
0 |
0 |
T125 |
156702 |
305 |
0 |
0 |
T128 |
94822 |
281 |
0 |
0 |
T132 |
122496 |
836 |
0 |
0 |
T133 |
181070 |
464 |
0 |
0 |
T135 |
36576 |
223 |
0 |
0 |
T146 |
18597 |
25 |
0 |
0 |
T155 |
82952 |
527 |
0 |
0 |
T156 |
105771 |
253 |
0 |
0 |
T157 |
13532 |
18 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
5688 |
0 |
0 |
T35 |
0 |
228 |
0 |
0 |
T49 |
4629 |
49 |
0 |
0 |
T50 |
11224 |
0 |
0 |
0 |
T51 |
1878 |
0 |
0 |
0 |
T52 |
45778 |
0 |
0 |
0 |
T53 |
806032 |
0 |
0 |
0 |
T54 |
134940 |
0 |
0 |
0 |
T55 |
9907 |
0 |
0 |
0 |
T56 |
8033 |
0 |
0 |
0 |
T57 |
349280 |
0 |
0 |
0 |
T125 |
0 |
283 |
0 |
0 |
T132 |
0 |
735 |
0 |
0 |
T146 |
0 |
31 |
0 |
0 |
T155 |
0 |
503 |
0 |
0 |
T158 |
0 |
36 |
0 |
0 |
T159 |
0 |
5 |
0 |
0 |
T160 |
0 |
17 |
0 |
0 |
T161 |
0 |
26 |
0 |
0 |
T162 |
90419 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4142 |
0 |
0 |
T35 |
94181 |
101 |
0 |
0 |
T125 |
156702 |
317 |
0 |
0 |
T128 |
94822 |
173 |
0 |
0 |
T132 |
122496 |
708 |
0 |
0 |
T133 |
181070 |
481 |
0 |
0 |
T135 |
36576 |
233 |
0 |
0 |
T146 |
18597 |
69 |
0 |
0 |
T155 |
82952 |
565 |
0 |
0 |
T156 |
105771 |
169 |
0 |
0 |
T157 |
13532 |
75 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4140 |
0 |
0 |
T35 |
94181 |
125 |
0 |
0 |
T125 |
156702 |
256 |
0 |
0 |
T128 |
94822 |
136 |
0 |
0 |
T132 |
122496 |
824 |
0 |
0 |
T133 |
181070 |
483 |
0 |
0 |
T135 |
36576 |
208 |
0 |
0 |
T146 |
18597 |
47 |
0 |
0 |
T155 |
82952 |
520 |
0 |
0 |
T156 |
105771 |
141 |
0 |
0 |
T157 |
13532 |
60 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3703 |
0 |
0 |
T35 |
94181 |
71 |
0 |
0 |
T125 |
156702 |
252 |
0 |
0 |
T128 |
94822 |
99 |
0 |
0 |
T132 |
122496 |
746 |
0 |
0 |
T133 |
181070 |
434 |
0 |
0 |
T135 |
36576 |
252 |
0 |
0 |
T146 |
18597 |
43 |
0 |
0 |
T155 |
82952 |
531 |
0 |
0 |
T156 |
105771 |
112 |
0 |
0 |
T157 |
13532 |
20 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3807 |
0 |
0 |
T35 |
94181 |
54 |
0 |
0 |
T125 |
156702 |
295 |
0 |
0 |
T128 |
94822 |
114 |
0 |
0 |
T132 |
122496 |
720 |
0 |
0 |
T133 |
181070 |
458 |
0 |
0 |
T135 |
36576 |
230 |
0 |
0 |
T146 |
18597 |
53 |
0 |
0 |
T155 |
82952 |
515 |
0 |
0 |
T156 |
105771 |
114 |
0 |
0 |
T157 |
13532 |
47 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3903 |
0 |
0 |
T35 |
94181 |
80 |
0 |
0 |
T125 |
156702 |
224 |
0 |
0 |
T128 |
94822 |
145 |
0 |
0 |
T132 |
122496 |
761 |
0 |
0 |
T133 |
181070 |
428 |
0 |
0 |
T135 |
36576 |
232 |
0 |
0 |
T146 |
18597 |
14 |
0 |
0 |
T155 |
82952 |
572 |
0 |
0 |
T156 |
105771 |
126 |
0 |
0 |
T157 |
13532 |
46 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3726 |
0 |
0 |
T35 |
94181 |
53 |
0 |
0 |
T125 |
156702 |
281 |
0 |
0 |
T128 |
94822 |
107 |
0 |
0 |
T132 |
122496 |
680 |
0 |
0 |
T133 |
181070 |
433 |
0 |
0 |
T135 |
36576 |
213 |
0 |
0 |
T146 |
18597 |
62 |
0 |
0 |
T155 |
82952 |
550 |
0 |
0 |
T156 |
105771 |
124 |
0 |
0 |
T157 |
13532 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4469 |
0 |
0 |
T35 |
94181 |
130 |
0 |
0 |
T125 |
156702 |
277 |
0 |
0 |
T128 |
94822 |
191 |
0 |
0 |
T132 |
122496 |
706 |
0 |
0 |
T133 |
181070 |
459 |
0 |
0 |
T135 |
36576 |
220 |
0 |
0 |
T146 |
18597 |
50 |
0 |
0 |
T155 |
82952 |
522 |
0 |
0 |
T156 |
105771 |
267 |
0 |
0 |
T157 |
13532 |
32 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3891 |
0 |
0 |
T35 |
94181 |
57 |
0 |
0 |
T125 |
156702 |
285 |
0 |
0 |
T128 |
94822 |
107 |
0 |
0 |
T132 |
122496 |
796 |
0 |
0 |
T133 |
181070 |
466 |
0 |
0 |
T135 |
36576 |
221 |
0 |
0 |
T146 |
18597 |
28 |
0 |
0 |
T155 |
82952 |
526 |
0 |
0 |
T156 |
105771 |
140 |
0 |
0 |
T157 |
13532 |
70 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
4693 |
0 |
0 |
T35 |
94181 |
160 |
0 |
0 |
T125 |
156702 |
282 |
0 |
0 |
T128 |
94822 |
376 |
0 |
0 |
T132 |
122496 |
774 |
0 |
0 |
T133 |
181070 |
478 |
0 |
0 |
T135 |
36576 |
214 |
0 |
0 |
T146 |
18597 |
25 |
0 |
0 |
T155 |
82952 |
487 |
0 |
0 |
T156 |
105771 |
324 |
0 |
0 |
T157 |
13532 |
39 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3886 |
0 |
0 |
T35 |
94181 |
76 |
0 |
0 |
T125 |
156702 |
244 |
0 |
0 |
T128 |
94822 |
169 |
0 |
0 |
T132 |
122496 |
672 |
0 |
0 |
T133 |
181070 |
471 |
0 |
0 |
T135 |
36576 |
226 |
0 |
0 |
T146 |
18597 |
19 |
0 |
0 |
T155 |
82952 |
528 |
0 |
0 |
T156 |
105771 |
178 |
0 |
0 |
T157 |
13532 |
43 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3979 |
0 |
0 |
T35 |
94181 |
49 |
0 |
0 |
T125 |
156702 |
256 |
0 |
0 |
T128 |
94822 |
125 |
0 |
0 |
T132 |
122496 |
700 |
0 |
0 |
T133 |
181070 |
520 |
0 |
0 |
T135 |
36576 |
258 |
0 |
0 |
T146 |
18597 |
33 |
0 |
0 |
T155 |
82952 |
606 |
0 |
0 |
T156 |
105771 |
134 |
0 |
0 |
T157 |
13532 |
46 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3857 |
0 |
0 |
T35 |
94181 |
58 |
0 |
0 |
T125 |
156702 |
284 |
0 |
0 |
T128 |
94822 |
125 |
0 |
0 |
T132 |
122496 |
794 |
0 |
0 |
T133 |
181070 |
420 |
0 |
0 |
T135 |
36576 |
219 |
0 |
0 |
T146 |
18597 |
37 |
0 |
0 |
T155 |
82952 |
542 |
0 |
0 |
T156 |
105771 |
91 |
0 |
0 |
T157 |
13532 |
28 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3554 |
0 |
0 |
T35 |
94181 |
38 |
0 |
0 |
T125 |
156702 |
204 |
0 |
0 |
T128 |
94822 |
118 |
0 |
0 |
T132 |
122496 |
726 |
0 |
0 |
T133 |
181070 |
471 |
0 |
0 |
T135 |
36576 |
214 |
0 |
0 |
T146 |
18597 |
30 |
0 |
0 |
T155 |
82952 |
484 |
0 |
0 |
T156 |
105771 |
121 |
0 |
0 |
T157 |
13532 |
4 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3717 |
0 |
0 |
T35 |
94181 |
73 |
0 |
0 |
T125 |
156702 |
246 |
0 |
0 |
T128 |
94822 |
80 |
0 |
0 |
T132 |
122496 |
739 |
0 |
0 |
T133 |
181070 |
475 |
0 |
0 |
T135 |
36576 |
194 |
0 |
0 |
T146 |
18597 |
41 |
0 |
0 |
T155 |
82952 |
498 |
0 |
0 |
T156 |
105771 |
111 |
0 |
0 |
T157 |
13532 |
56 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3820 |
0 |
0 |
T35 |
94181 |
63 |
0 |
0 |
T125 |
156702 |
258 |
0 |
0 |
T128 |
94822 |
110 |
0 |
0 |
T132 |
122496 |
813 |
0 |
0 |
T133 |
181070 |
403 |
0 |
0 |
T135 |
36576 |
235 |
0 |
0 |
T146 |
18597 |
45 |
0 |
0 |
T155 |
82952 |
539 |
0 |
0 |
T156 |
105771 |
116 |
0 |
0 |
T157 |
13532 |
22 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116495173 |
3845 |
0 |
0 |
T35 |
94181 |
79 |
0 |
0 |
T125 |
156702 |
258 |
0 |
0 |
T128 |
94822 |
96 |
0 |
0 |
T132 |
122496 |
818 |
0 |
0 |
T133 |
181070 |
442 |
0 |
0 |
T135 |
36576 |
247 |
0 |
0 |
T146 |
18597 |
42 |
0 |
0 |
T155 |
82952 |
497 |
0 |
0 |
T156 |
105771 |
110 |
0 |
0 |
T157 |
13532 |
40 |
0 |
0 |