Unified Coverage Report :: Module :: spi_passthrough

Module : spi_passthrough

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.95	91.50	87.63		75.00	90.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough	88.95	91.50	87.63		75.00	90.62	100.00

---

Module Instance : tb.dut.u_passthrough

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.95	91.50	87.63		75.00	90.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.42	92.20	88.24		75.00	91.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.97	89.91	80.39	96.94		81.25	86.36	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pt_sck_cg	100.00	100.00	100.00			100.00
u_read_half_cycle	100.00	100.00				100.00
u_read_pipe_oe_stg1	100.00	100.00				100.00
u_read_pipe_oe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
TOTAL		200	183	91.50
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	335	4	4	100.00
ALWAYS	344	4	4	100.00
ALWAYS	348	3	3	100.00
CONT_ASSIGN	354	1	1	100.00
ALWAYS	359	4	4	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
ALWAYS	375	4	4	100.00
ALWAYS	399	8	8	100.00
ALWAYS	413	4	4	100.00
ALWAYS	424	4	4	100.00
CONT_ASSIGN	438	0	0
ALWAYS	448	4	4	100.00
CONT_ASSIGN	462	1	1	100.00
ALWAYS	465	3	3	100.00
CONT_ASSIGN	474	1	1	100.00
ALWAYS	477	3	3	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	505	3	3	100.00
ALWAYS	519	4	4	100.00
ALWAYS	527	3	3	100.00
ALWAYS	532	6	6	100.00
ALWAYS	538	3	3	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	581	6	6	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	595	6	4	66.67
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	608	1	1	100.00
ALWAYS	612	3	3	100.00
CONT_ASSIGN	615	1	1	100.00
ALWAYS	684	13	7	53.85
ALWAYS	712	3	3	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
ALWAYS	744	3	3	100.00
ALWAYS	752	68	59	86.76

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
270	1	1
275	1	1
325	1	1
332	1	1
335	1	1
336	1	1
337	1	1
338	1	1
			MISSING_ELSE
344	2	2
345	2	2
			MISSING_ELSE
348	2	2
349	1	1
354	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
371	1	1
372	1	1
375	1	1
376	1	1
377	1	1
385	1	1
			MISSING_ELSE
399	1	1
400	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
413	1	1
414	1	1
415	1	1
418	1	1
			MISSING_ELSE
424	1	1
425	1	1
426	1	1
429	1	1
			MISSING_ELSE
438		unreachable
448	1	1
450	1	1
453	1	1
455	1	1
			MISSING_ELSE
462	1	1
465	1	1
466	1	1
467	1	1
			MISSING_ELSE
474	1	1
477	1	1
478	1	1
480	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
496	1	1
505	2	2
506	1	1
519	1	1
520	1	1
521	1	1
522	1	1
			MISSING_ELSE
527	2	2
528	1	1
532	2	2
533	2	2
534	2	2
			MISSING_ELSE
538	2	2
539	1	1
542	1	1
545	1	1
560	1	1
561	1	1
562	1	1
564	1	1
565	1	1
569	1	1
571	1	1
574	1	1
575	1	1
581	2	2
582	1	1
583	1	1
584	1	1
585	1	1
			MISSING_ELSE
588	1	1
595	1	1
596	1	1
597	1	1
598	0	1
599	1	1
600	0	1
			MISSING_ELSE
603	1	1
608	1	1
612	2	2
613	1	1
615	1	1
684	1	1
685	1	1
686	1	1
688	1	1
689	1	1
690	1	1
692	1	1
694	0	1
695	0	1
696	0	1
699	0	1
700	0	1
701	0	1
712	2	2
713	1	1
727	1	1
733	1	1
736	1	1
744	1	1
745	1	1
747	1	1
752	1	1
755	1	1
758	1	1
761	1	1
764	1	1
767	1	1
770	1	1
771	1	1
774	1	1
775	1	1
777	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
786	1	1
787	1	1
797	1	1
798	1	1
800	1	1
801	1	1
802	1	1
804	1	1
805	1	1
806	1	1
808	1	1
809	1	1
811	1	1
813	1	1
			MISSING_ELSE
817	1	1
819	1	1
820	1	1
			MISSING_ELSE
825	0	1
826	0	1
828	0	1
829	0	1
831	0	1
837	1	1
838	1	1
839	1	1
844	1	1
847	1	1
848	1	1
853	1	1
856	1	1
857	1	1
861	1	1
862	1	1
863	1	1
865	1	1
866	1	1
867	0	1
869	0	1
			MISSING_ELSE
875	1	1
876	1	1
877	0	1
879	0	1
880	1	1
881	1	1
883	1	1
884	1	1
885	1	1
887	1	1
888	1	1
890	1	1
892	1	1
895	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spi_passthrough

	Total	Covered	Percent
Conditions	97	85	87.63
Logical	97	85	87.63
Non-Logical	0	0
Event	0	0

 LINE       270
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       354
 SUB-EXPRESSION (filter | csb_deassert)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       361
 EXPRESSION (bitcnt != '1)
            -------1------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       371
 EXPRESSION (bitcnt == 6'(6))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       372
 EXPRESSION (bitcnt == 6'(7))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       403
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b1})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       405
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b0})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T8

 LINE       466
 EXPRESSION (addr_mode == Addr4B)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       474
 EXPRESSION (st == StAddress)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       489
 EXPRESSION (addrcnt_outclk != '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T6

 LINE       496
 EXPRESSION (cfg_addr_mask_i[addrcnt_outclk] ? cfg_addr_value_i[addrcnt_outclk] : host_s_i[0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       521
 EXPRESSION ((payloadcnt != '0) && payload_replace)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T66
1	0	Covered	T1,T4,T5
1	1	Covered	T9,T12,T66

 LINE       521
 SUB-EXPRESSION (payloadcnt != '0)
                ---------1--------

-1-	Status	Tests
0	Covered	T9,T12,T66
1	Covered	T1,T4,T5

 LINE       542
 EXPRESSION (payloadcnt == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T12,T66

 LINE       545
 EXPRESSION (cfg_payload_mask_i[payloadcnt_outclk] ? cfg_payload_data_i[payloadcnt_outclk] : host_s_i[0])
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       569
 EXPRESSION (addr_phase_outclk & cmd_info_addr_swap_en_outclk)
             --------1--------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T12,T66
1	0	Covered	T1,T5,T8
1	1	Covered	T6,T12,T66

 LINE       571
 EXPRESSION (payload_replace_outclk & cmd_info_payload_swap_en_outclk)
             -----------1----------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T66,T67
1	0	Covered	T8,T9,T26
1	1	Covered	T12,T66,T67

 LINE       574
 EXPRESSION (addr_swap_en | payload_swap_en)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T66,T67
1	0	Covered	T6,T12,T66

 LINE       575
 EXPRESSION (addr_swap_en ? addr_swap : payload_swap)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T66

 LINE       584
 EXPRESSION (st == StHighZ)
            -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T6

 LINE       588
 EXPRESSION (dummycnt == '0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       599
 EXPRESSION (st == StMByte)
            -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       603
 EXPRESSION (mbyte_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (swap_en ? ({host_s_i[3:1], swap_data}) : host_s_i)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T66

 LINE       733
 EXPRESSION (host_csb_i | csb_deassert_outclk)
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       736
 EXPRESSION (is_active && ((!passthrough_block_i)))
             ----1----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T6

 LINE       781
 EXPRESSION (cmd_8th && cmd_filter[host_s_i[0]])
             ---1---    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       786
 EXPRESSION (cmd_8th && cmd_info_d.valid)
             ---1---    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       797
 EXPRESSION (cmd_info_d.addr_mode != AddrDisabled)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T5,T6

 LINE       806
 EXPRESSION (cmd_info_d.payload_en != 4'b0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T68,T53,T69
1	Covered	T5,T6,T8

 LINE       808
 EXPRESSION (cmd_info_d.payload_dir == PayloadOut)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T8,T9,T26
1	Covered	T5,T6,T8

 LINE       863
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadOut))
             ------1------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T5,T6

 LINE       863
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T6

 LINE       866
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadIn))
             ------1------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       866
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       875
 EXPRESSION (addrcnt_outclk == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       885
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))
             --------------1--------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T68,T70,T71
1	0	Covered	T12,T66,T67
1	1	Covered	T1,T8,T9

 LINE       885
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T68,T70,T71
1	Covered	T1,T8,T9

 LINE       885
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T12,T66,T67
1	Covered	T1,T8,T9

 LINE       888
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn))
             --------------1--------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T12,T66,T67

 LINE       888
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T68,T70,T71
1	Covered	T12,T66,T67

 LINE       888
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T68,T70,T71
1	Covered	T12,T66,T67

---

FSM Coverage for Module : spi_passthrough

Summary for FSM :: st

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	12	9	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddress	798	Covered	T1,T5,T6
StDriving	811	Covered	T8,T9,T12
StFilter	782	Covered	T1,T5,T6
StHighZ	802	Covered	T1,T5,T6
StIdle	780	Covered	T1,T2,T3
StMByte	831	Not Covered
StWait	809	Covered	T1,T5,T6

transitions	Line No.	Covered	Tests
StAddress->StDriving	890	Covered	T12,T66,T67
StAddress->StHighZ	881	Covered	T1,T5,T6
StAddress->StMByte	877	Not Covered
StAddress->StWait	887	Covered	T1,T8,T9
StHighZ->StDriving	867	Not Covered
StHighZ->StWait	865	Covered	T1,T5,T6
StIdle->StAddress	798	Covered	T1,T5,T6
StIdle->StDriving	811	Covered	T8,T9,T26
StIdle->StFilter	782	Covered	T1,T5,T6
StIdle->StHighZ	802	Covered	T6,T67,T72
StIdle->StWait	809	Covered	T5,T6,T8
StMByte->StHighZ	826	Not Covered

---

Branch Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
Branches		96	87	90.62
TERNARY	496	2	2	100.00
TERNARY	545	2	2	100.00
TERNARY	575	2	2	100.00
TERNARY	608	2	2	100.00
IF	335	3	3	100.00
IF	344	3	3	100.00
IF	348	2	2	100.00
IF	359	3	3	100.00
IF	375	3	3	100.00
IF	400	2	2	100.00
IF	413	3	3	100.00
IF	424	3	3	100.00
IF	450	2	2	100.00
IF	466	2	2	100.00
IF	477	2	2	100.00
IF	485	4	4	100.00
IF	505	2	2	100.00
IF	519	3	3	100.00
IF	527	2	2	100.00
IF	532	4	4	100.00
IF	538	2	2	100.00
IF	560	2	2	100.00
IF	581	4	4	100.00
IF	595	4	2	50.00
IF	612	2	2	100.00
CASE	692	3	1	33.33
IF	712	2	2	100.00
IF	744	2	2	100.00
CASE	777	24	19	79.17

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	496	(cfg_addr_mask_i[addrcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	545	(cfg_payload_mask_i[payloadcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	575	(addr_swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T66
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	608	(swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T66
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	if ((!rst_ni))
-2-:	337	if ((bitcnt < 6'(8)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	344	if ((!rst_ni))
-2-:	345	if (filter)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	348	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	361	if ((bitcnt != '1))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	375	if ((!rst_ni))
-2-:	377	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	400	if (cmd_7th)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if ((!rst_ni))
-2-:	415	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	424	if ((!rst_ni))
-2-:	426	if (cmd_info_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	450	if (cmd_8th)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	466	if ((addr_mode == Addr4B))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (addr_set_q)
-3-:	489	if ((addrcnt_outclk != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	505	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	519	if ((!rst_ni))
-2-:	521	if (((payloadcnt != '0) && payload_replace))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T12,T66
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	527	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	532	if ((!rst_ni))
-2-:	533	if (payload_replace_set)
-3-:	534	if (payload_replace_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T9,T12
0	0	1	Covered	T9,T12,T66
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	538	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	560	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	581	if ((!rst_ni))
-2-:	582	if (dummy_set)
-3-:	584	if ((st == StHighZ))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	595	if ((!rst_ni))
-2-:	597	if (mbyte_set)
-3-:	599	if ((st == StMByte))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	692	case (cmd_info.read_pipeline_mode)

Branches:

-1-	Status	Tests
RdPipeTwoStageFullCycle	Not Covered
RdPipeTwoStageHalfCycle	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	712	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	744	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	777	case (st)
-2-:	779	if ((!is_active))
-3-:	781	if ((cmd_8th && cmd_filter[host_s_i[0]]))
-4-:	786	if ((cmd_8th && cmd_info_d.valid))
-5-:	797	if ((cmd_info_d.addr_mode != AddrDisabled))
-6-:	801	if (cmd_info_d.dummy_en)
-7-:	806	if ((cmd_info_d.payload_en != 4'b0))
-8-:	808	if ((cmd_info_d.payload_dir == PayloadOut))
-9-:	817	if (cmd_8th)
-10-:	825	if (mbytecnt_zero)
-11-:	863	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadOut)))
-12-:	866	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadIn)))
-13-:	875	if ((addrcnt_outclk == '0))
-14-:	876	if (cmd_info.mbyte_en)
-15-:	880	if (cmd_info.dummy_en)
-16-:	885	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut)))
-17-:	888	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StIdle	0	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StIdle	0	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T67,T72
StIdle	0	0	1	0	0	1	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T8
StIdle	0	0	1	0	0	1	0	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T26
StIdle	0	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T68,T53,T69
StIdle	0	0	0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StIdle	0	0	0	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StMByte	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMByte	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StFilter	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StDriving	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T12
StHighZ	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T5,T6
StHighZ	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Not Covered
StHighZ	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T6
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	Covered	T1,T5,T6
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	Covered	T1,T8,T9
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	1	Covered	T12,T66,T67
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	0	Covered	T68,T70,T71
StAddress	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_passthrough

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PassThroughStKnown_A	39014337	25666160	0	0
PayloadSwapConstraint_M	39014337	171176	0	0

PassThroughStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	25666160	0	0
T1	160162	160162	0	0
T2	144	0	0	0
T3	1760	0	0	0
T4	82517	82044	0	0
T5	71078	69778	0	0
T6	201598	201598	0	0
T8	104368	104008	0	0
T9	125712	125522	0	0
T10	58990	58990	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	135128	0	0	0

PayloadSwapConstraint_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	171176	0	0
T12	158855	29032	0	0
T13	12949	0	0	0
T19	91787	0	0	0
T21	9097	0	0	0
T25	192	0	0	0
T26	74314	0	0	0
T60	1488	0	0	0
T61	106986	0	0	0
T62	189193	0	0	0
T66	150359	19464	0	0
T67	0	8360	0	0
T72	0	48	0	0
T73	0	2072	0	0
T74	0	18248	0	0
T75	0	24	0	0
T76	0	12808	0	0
T77	0	4144	0	0
T78	0	2048	0	0