Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.97	89.91	80.39	96.94		81.25	86.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.97	89.91	80.39	96.94		81.25	86.36

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.97	89.91	80.39	96.94		81.25	86.36

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.82	97.61	92.93	98.61	80.85	96.01	90.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	91.22	96.30	86.59		87.50	85.71	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	97.92	100.00	91.67			100.00	100.00
u_intr_payload_not_empty	97.92	100.00	91.67			100.00	100.00
u_intr_payload_overflow	97.92	100.00	91.67			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.73	100.00	71.43			67.50	100.00
u_passthrough	89.42	92.20	88.24		75.00	91.67	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_intercept_pipe_stg1	100.00	100.00				100.00
u_read_intercept_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.12	93.62	89.40		87.50	84.15	90.91
u_reg	99.64	99.53	99.33	100.00		99.35	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.68	99.28	84.99		91.67	95.32	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	93.75	100.00	75.00			100.00	100.00
u_spid_status	97.51	97.71	97.83			94.52	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	88.46	100.00	76.47			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.25	81.97	59.04			63.33	80.65
u_tlul2sram_ingress	83.85	85.66	70.85			78.89	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	44.14	85.05	38.21		0.00	63.53	33.93

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		228	205	89.91
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
ALWAYS	568	0	0
ALWAYS	568	2	2	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	582	0	0
ALWAYS	582	12	12	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	784	3	3	100.00
ALWAYS	790	8	6	75.00
ALWAYS	828	9	9	100.00
ALWAYS	852	24	20	83.33
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
ALWAYS	984	7	4	57.14
ALWAYS	997	13	13	100.00
ALWAYS	1034	3	3	100.00
CONT_ASSIGN	1170	1	1	100.00
CONT_ASSIGN	1173	1	1	100.00
CONT_ASSIGN	1177	1	1	100.00
CONT_ASSIGN	1178	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1231	1	0	0.00
CONT_ASSIGN	1261	1	0	0.00
CONT_ASSIGN	1344	1	0	0.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1350	1	0	0.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1361	1	0	0.00
CONT_ASSIGN	1362	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1383	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1531	1	0	0.00
CONT_ASSIGN	1539	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1541	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1565	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1567	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1587	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1598	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1656	1	1	100.00
ALWAYS	1661	4	4	100.00
ALWAYS	1670	0	0
ALWAYS	1670	9	9	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1688	1	1	100.00
CONT_ASSIGN	1688	1	1	100.00
CONT_ASSIGN	1688	1	0	0.00
CONT_ASSIGN	1688	1	0	0.00
CONT_ASSIGN	1688	1	0	0.00
CONT_ASSIGN	1689	1	1	100.00
CONT_ASSIGN	1689	1	1	100.00
CONT_ASSIGN	1689	1	0	0.00
CONT_ASSIGN	1689	1	0	0.00
CONT_ASSIGN	1689	1	1	100.00
CONT_ASSIGN	1690	1	1	100.00
CONT_ASSIGN	1690	1	1	100.00
CONT_ASSIGN	1690	1	0	0.00
CONT_ASSIGN	1690	1	0	0.00
CONT_ASSIGN	1690	1	0	0.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1693	1	1	100.00
CONT_ASSIGN	1693	1	1	100.00
CONT_ASSIGN	1693	1	1	100.00
CONT_ASSIGN	1693	1	1	100.00
CONT_ASSIGN	1693	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
CONT_ASSIGN	1694	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1737	1	1	100.00
CONT_ASSIGN	1738	1	1	100.00
CONT_ASSIGN	1739	1	1	100.00
CONT_ASSIGN	1740	1	1	100.00
CONT_ASSIGN	1741	1	1	100.00
CONT_ASSIGN	1743	1	1	100.00
CONT_ASSIGN	1744	1	1	100.00
CONT_ASSIGN	1745	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
308	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
393	1	1
526	1	1
533	1	1
535	1	1
538	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
546	1	1
552	1	1
553	1	1
558	1	1
559	1	1
563	1	1
568	1	1
569	1	1
573	1	1
574	1	1
582	1	1
583	1	1
602	1	1
603	1	1
607	1	1
608	1	1
610	1	1
611	1	1
613	1	1
614	1	1
616	1	1
617	1	1
646	1	1
647	1	1
648	1	1
784	2	2
785	1	1
790	1	1
792	1	1
793	1	1
800	1	1
804	1	1
805	1	1
809	0	1
810	0	1
828	1	1
830	1	1
835	1	1
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
846	1	1
			MISSING_ELSE
852	1	1
853	1	1
854	1	1
855	1	1
857	1	1
859	1	1
861	1	1
863	1	1
867	1	1
869	1	1
870	1	1
871	1	1
874	1	1
876	1	1
877	1	1
878	1	1
883	1	1
885	1	1
886	1	1
887	1	1
891	0	1
893	0	1
894	0	1
895	0	1
920	1	1
921	1	1
984	1	1
985	0	1
986	0	1
987	0	1
989	1	1
990	1	1
991	1	1
997	1	1
998	1	1
1000	1	1
1002	1	1
1003	1	1
1007	1	1
1009	1	1
1010	1	1
1014	1	1
1015	1	1
1016	1	1
1018	1	1
1019	1	1
1034	2	2
1035	1	1
1170	1	1
1173	1	1
1177	1	1
1178	1	1
1179	1	1
1181	1	1
1182	1	1
1185	1	1
1231	0	1
1261	0	1
1344	0	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1350	0	1
1354	1	1
1361	0	1
1362	1	1
1364	1	1
1368	1	1
1371	1	1
1374	1	1
1377	1	1
1380	1	1
1383	1	1
1390	1	1
1391	1	1
1430	1	1
1531	0	1
1539	1	1
1540	1	1
1541	1	1
1542	1	1
1543	1	1
1546	1	1
1553	1	1
1560	5	5
1563	1	1
1564	1	1
1565	1	1
1566	1	1
1567	1	1
1568	1	1
1570	1	1
1574	1	1
1576	1	1
1577	1	1
1584	1	1
1586	1	1
1587	1	1
1596	1	1
1597	1	1
1598	1	1
1599	1	1
1654	1	1
1656	1	1
1661	1	1
1662	1	1
1663	1	1
1664	1	1
			MISSING_ELSE
1670	1	1
1671	1	1
1673	1	1
1676	1	1
1677	1	1
1678	1	1
1679	1	1
1681	1	1
1682	1	1
1687	5	5
1688	2	5
1689	3	5
1690	2	5
1692	5	5
1693	5	5
1694	5	5
1735	1	1
1737	1	1
1738	1	1
1739	1	1
1740	1	1
1741	1	1
1743	1	1
1744	1	1
1745	1	1
1801	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	41	80.39
Logical	51	41	80.39
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       701
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       712
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       814
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7

 LINE       841
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       841
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       1000
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T2,T3,T14
1	1	Covered	T2,T3,T14

 LINE       1170
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       1181
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1182
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       1390
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T25,T26

 LINE       1391
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T29

 LINE       1553
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T15,T16

 LINE       1663
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1663
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1663
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1735
 EXPRESSION (tpm_rst_n | rst_spi_n)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T3,T14

 LINE       1801
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T10,T13	Yes	T6,T10,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T30,T31,T34	Yes	T30,T31,T34	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T30,T31,T34	Yes	T30,T31,T34	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
cio_sd_o[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T1,*T5,*T6	Yes	T1,T5,T6	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T39,T40,T41	Yes	T1,T5,T6	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T33,T35,T42	Yes	T33,T35,T42	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T43	Yes	T43	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T43	Yes	T43	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	26	81.25
IF	538	3	3	100.00
IF	784	2	2	100.00
CASE	800	4	3	75.00
IF	841	3	3	100.00
CASE	857	7	4	57.14
IF	984	2	1	50.00
IF	1000	5	4	80.00
IF	1034	2	2	100.00
IF	1663	2	2	100.00
IF	1673	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	538	if ((!rst_ni))
-2-:	540	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	784	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	800	case (cmd_dp_sel)
-2-:	814	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T1,T4,T5
DpUpload	-	Not Covered
default	1	Covered	T7
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	841	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	844	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T2,T3,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	857	case (spi_mode)
-2-:	859	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T1,T4,T5
FlashMode PassThrough	DpReadStatus	Covered	T5,T26,T27
FlashMode PassThrough	DpReadJEDEC	Covered	T44,T45,T46
FlashMode PassThrough	DpUpload	Not Covered
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	984	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1000	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1007	case (spi_mode)
-3-:	1014	if (intercept_en_out)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T14
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T1,T5,T26
0	PassThrough	0	Covered	T1,T5,T6
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1034	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	1663	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1673	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	19	86.36
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	19	86.36

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	121474548	121414305	0	0
CioSdoEnOKnown	121474548	121414305	0	0
CioSdoEnOffWhenInactive	121474548	121414305	0	0
FpvSecCmRegWeOnehotCheck_A	121474548	120	0	0
InterceptLevel_M	39014977	0	0	0
IntrReadbufFlipOKnown	121474548	121414305	0	0
IntrReadbufWatermarkOKnown	121474548	121414305	0	0
IntrTpmHeaderNotEmptyOKnown	121474548	121414305	0	0
IntrTpmRdfifoCmdEndOKnown	121474548	121414305	0	0
IntrTpmRdfifoDropOKnown	121474548	121414305	0	0
IntrUploadCmdfifoNotEmptyOKnown	121474548	121414305	0	0
IntrUploadPayloadNotEmptyOKnown	121474548	121414305	0	0
IntrUploadPayloadOverflowOKnown	121474548	121414305	0	0
PayloadStartIdxWidthMatch_A	659	659	0	0
SpiModeKnown_A	121474548	121414305	0	0
TpmEnableWhenTpmCsbIdle_M	121474548	200	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	121474548	365440	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	121474548	43029	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	121474548	0	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	121474548	0	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	121474548	75693	0	0
scanmodeKnown	121474548	121474548	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	120	0	0
T34	5500	20	0	0
T47	0	30	0	0
T48	0	30	0	0
T49	0	30	0	0
T50	0	10	0	0
T51	501405	0	0	0
T52	169870	0	0	0
T53	161823	0	0	0
T54	11760	0	0	0
T55	21273	0	0	0
T56	24252	0	0	0
T57	679844	0	0	0
T58	742	0	0	0
T59	1871	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014977	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	200	0	0
T2	1549	1	0	0
T3	4799	1	0	0
T4	88191	0	0	0
T5	51612	0	0	0
T6	101513	0	0	0
T8	631962	0	0	0
T9	131405	0	0	0
T10	305106	0	0	0
T14	87494	1	0	0
T15	1092	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	365440	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	0	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	87494	0	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	43029	0	0
T3	4799	11	0	0
T4	88191	0	0	0
T5	51612	0	0	0
T6	101513	0	0	0
T8	631962	0	0	0
T9	131405	0	0	0
T10	305106	0	0	0
T14	87494	0	0	0
T15	1092	4	0	0
T16	3661	10	0	0
T19	0	731	0	0
T55	0	36	0	0
T57	0	792	0	0
T60	0	20	0	0
T62	0	1117	0	0
T63	0	12	0	0
T64	0	16	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	75693	0	0
T3	4799	33	0	0
T4	88191	0	0	0
T5	51612	0	0	0
T6	101513	0	0	0
T8	631962	0	0	0
T9	131405	0	0	0
T10	305106	0	0	0
T14	87494	0	0	0
T15	1092	10	0	0
T16	3661	18	0	0
T19	0	1203	0	0
T55	0	30	0	0
T57	0	1575	0	0
T60	0	21	0	0
T62	0	1797	0	0
T63	0	11	0	0
T65	0	615	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121474548	0	0
T1	57235	57235	0	0
T2	1549	1549	0	0
T3	4799	4799	0	0
T4	88191	88191	0	0
T5	51612	51612	0	0
T6	101513	101513	0	0
T8	631962	631962	0	0
T9	131405	131405	0	0
T10	305106	305106	0	0
T14	87494	87494	0	0