Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.97	89.91	80.39	96.94		81.25	86.36	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123414033	3637	0	0
addr_swap_data_rd_A	123414033	1382	0	0
addr_swap_mask_rd_A	123414033	1402	0	0
cfg_rd_A	123414033	1547	0	0
cmd_filter_0_rd_A	123414033	8396	0	0
cmd_filter_1_rd_A	123414033	7207	0	0
cmd_filter_2_rd_A	123414033	6484	0	0
cmd_filter_3_rd_A	123414033	7690	0	0
cmd_filter_4_rd_A	123414033	7651	0	0
cmd_filter_5_rd_A	123414033	6196	0	0
cmd_filter_6_rd_A	123414033	6943	0	0
cmd_filter_7_rd_A	123414033	6380	0	0
cmd_info_0_rd_A	123414033	4044	0	0
cmd_info_10_rd_A	123414033	3964	0	0
cmd_info_11_rd_A	123414033	3742	0	0
cmd_info_12_rd_A	123414033	3598	0	0
cmd_info_13_rd_A	123414033	3350	0	0
cmd_info_14_rd_A	123414033	3807	0	0
cmd_info_15_rd_A	123414033	3658	0	0
cmd_info_16_rd_A	123414033	3543	0	0
cmd_info_17_rd_A	123414033	3871	0	0
cmd_info_18_rd_A	123414033	3534	0	0
cmd_info_19_rd_A	123414033	4027	0	0
cmd_info_1_rd_A	123414033	3382	0	0
cmd_info_20_rd_A	123414033	3603	0	0
cmd_info_21_rd_A	123414033	3700	0	0
cmd_info_22_rd_A	123414033	3462	0	0
cmd_info_23_rd_A	123414033	3381	0	0
cmd_info_2_rd_A	123414033	3457	0	0
cmd_info_3_rd_A	123414033	3256	0	0
cmd_info_4_rd_A	123414033	3557	0	0
cmd_info_5_rd_A	123414033	3971	0	0
cmd_info_6_rd_A	123414033	3540	0	0
cmd_info_7_rd_A	123414033	3295	0	0
cmd_info_8_rd_A	123414033	3628	0	0
cmd_info_9_rd_A	123414033	3539	0	0
cmd_info_en4b_rd_A	123414033	1734	0	0
cmd_info_ex4b_rd_A	123414033	1475	0	0
cmd_info_wrdi_rd_A	123414033	1563	0	0
cmd_info_wren_rd_A	123414033	1510	0	0
intercept_en_rd_A	123414033	2133	0	0
intr_enable_rd_A	123414033	3365	0	0
jedec_cc_rd_A	123414033	1658	0	0
jedec_id_rd_A	123414033	1563	0	0
mailbox_addr_rd_A	123414033	1419	0	0
payload_swap_data_rd_A	123414033	1424	0	0
payload_swap_mask_rd_A	123414033	1467	0	0
read_threshold_rd_A	123414033	1442	0	0
tpm_access_0_rd_A	123414033	1961	0	0
tpm_access_1_rd_A	123414033	1361	0	0
tpm_cfg_rd_A	123414033	2090	0	0
tpm_did_vid_rd_A	123414033	1625	0	0
tpm_int_enable_rd_A	123414033	1416	0	0
tpm_int_status_rd_A	123414033	1469	0	0
tpm_int_vector_rd_A	123414033	1465	0	0
tpm_intf_capability_rd_A	123414033	1357	0	0
tpm_rid_rd_A	123414033	1316	0	0
tpm_sts_rd_A	123414033	1372	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3637	0	0
T36	3650	57	0	0
T37	80248	6	0	0
T38	11126	4	0	0
T114	7179	96	0	0
T115	3983	118	0	0
T119	29016	2	0	0
T120	10340	2	0	0
T121	5039	3	0	0
T131	5124	1	0	0
T140	16596	9	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1382	0	0
T38	11126	16	0	0
T39	9998	1	0	0
T40	12481	5	0	0
T138	5756	7	0	0
T140	16596	15	0	0
T144	6258	12	0	0
T158	7624	54	0	0
T163	83764	499	0	0
T164	13952	16	0	0
T165	8651	15	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1402	0	0
T38	11126	15	0	0
T39	9998	11	0	0
T40	12481	9	0	0
T138	5756	7	0	0
T139	12879	5	0	0
T140	16596	21	0	0
T158	7624	39	0	0
T163	83764	543	0	0
T164	13952	20	0	0
T165	8651	14	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1547	0	0
T38	11126	35	0	0
T39	9998	23	0	0
T40	12481	14	0	0
T138	5756	2	0	0
T139	12879	19	0	0
T140	16596	22	0	0
T144	6258	10	0	0
T163	83764	532	0	0
T164	13952	19	0	0
T165	8651	35	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	8396	0	0
T38	11126	136	0	0
T39	9998	393	0	0
T40	12481	95	0	0
T138	5756	101	0	0
T140	16596	284	0	0
T144	6258	78	0	0
T158	7624	25	0	0
T163	83764	526	0	0
T164	13952	139	0	0
T165	8651	103	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	7207	0	0
T38	11126	159	0	0
T39	9998	226	0	0
T40	12481	119	0	0
T138	5756	98	0	0
T140	16596	269	0	0
T144	6258	116	0	0
T158	7624	39	0	0
T163	83764	519	0	0
T164	13952	12	0	0
T165	8651	129	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	6484	0	0
T38	11126	136	0	0
T39	9998	14	0	0
T40	12481	239	0	0
T138	5756	114	0	0
T140	16596	211	0	0
T144	6258	57	0	0
T158	7624	1	0	0
T163	83764	508	0	0
T164	13952	94	0	0
T165	8651	219	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	7690	0	0
T38	11126	280	0	0
T39	9998	9	0	0
T40	12481	228	0	0
T138	5756	12	0	0
T140	16596	130	0	0
T144	6258	40	0	0
T158	7624	31	0	0
T163	83764	469	0	0
T164	13952	16	0	0
T165	8651	107	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	7651	0	0
T38	11126	274	0	0
T39	9998	194	0	0
T40	12481	252	0	0
T138	5756	11	0	0
T139	12879	73	0	0
T140	16596	280	0	0
T144	6258	5	0	0
T163	83764	540	0	0
T164	13952	187	0	0
T165	8651	158	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	6196	0	0
T38	11126	125	0	0
T39	9998	237	0	0
T40	12481	398	0	0
T138	5756	2	0	0
T140	16596	292	0	0
T144	6258	85	0	0
T158	7624	33	0	0
T163	83764	563	0	0
T164	13952	11	0	0
T165	8651	124	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	6943	0	0
T38	11126	150	0	0
T39	9998	14	0	0
T40	12481	134	0	0
T138	5756	14	0	0
T139	12879	100	0	0
T140	16596	265	0	0
T158	7624	59	0	0
T163	83764	563	0	0
T164	13952	179	0	0
T165	8651	121	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	6380	0	0
T38	11126	284	0	0
T39	9998	7	0	0
T40	12481	156	0	0
T138	5756	97	0	0
T140	16596	413	0	0
T144	6258	6	0	0
T158	7624	58	0	0
T163	83764	576	0	0
T164	13952	135	0	0
T165	8651	130	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	4044	0	0
T38	11126	63	0	0
T39	9998	73	0	0
T40	12481	154	0	0
T138	5756	61	0	0
T140	16596	111	0	0
T144	6258	15	0	0
T158	7624	21	0	0
T163	83764	472	0	0
T164	13952	87	0	0
T165	8651	6	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3964	0	0
T38	11126	49	0	0
T39	9998	70	0	0
T40	12481	125	0	0
T138	5756	22	0	0
T140	16596	121	0	0
T144	6258	3	0	0
T158	7624	25	0	0
T163	83764	550	0	0
T164	13952	35	0	0
T165	8651	92	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3742	0	0
T38	11126	84	0	0
T39	9998	84	0	0
T40	12481	56	0	0
T138	5756	64	0	0
T140	16596	123	0	0
T144	6258	31	0	0
T158	7624	7	0	0
T163	83764	532	0	0
T164	13952	87	0	0
T165	8651	128	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3598	0	0
T38	11126	44	0	0
T39	9998	37	0	0
T40	12481	115	0	0
T138	5756	9	0	0
T140	16596	66	0	0
T144	6258	16	0	0
T158	7624	23	0	0
T163	83764	555	0	0
T164	13952	14	0	0
T165	8651	79	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3350	0	0
T38	11126	65	0	0
T39	9998	48	0	0
T40	12481	120	0	0
T138	5756	6	0	0
T140	16596	99	0	0
T144	6258	4	0	0
T158	7624	41	0	0
T163	83764	465	0	0
T164	13952	59	0	0
T165	8651	6	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3807	0	0
T38	11126	103	0	0
T39	9998	137	0	0
T40	12481	116	0	0
T138	5756	56	0	0
T140	16596	32	0	0
T144	6258	63	0	0
T158	7624	23	0	0
T163	83764	553	0	0
T164	13952	25	0	0
T165	8651	121	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3658	0	0
T38	11126	101	0	0
T39	9998	114	0	0
T40	12481	110	0	0
T138	5756	47	0	0
T139	12879	20	0	0
T140	16596	132	0	0
T144	6258	1	0	0
T163	83764	514	0	0
T164	13952	32	0	0
T165	8651	86	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3543	0	0
T38	11126	47	0	0
T39	9998	101	0	0
T40	12481	63	0	0
T138	5756	59	0	0
T140	16596	23	0	0
T144	6258	72	0	0
T158	7624	12	0	0
T163	83764	482	0	0
T164	13952	86	0	0
T165	8651	59	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3871	0	0
T38	11126	68	0	0
T39	9998	97	0	0
T40	12481	81	0	0
T138	5756	63	0	0
T139	12879	38	0	0
T140	16596	60	0	0
T158	7624	43	0	0
T163	83764	518	0	0
T164	13952	28	0	0
T165	8651	65	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3534	0	0
T38	11126	136	0	0
T39	9998	65	0	0
T40	12481	41	0	0
T138	5756	41	0	0
T140	16596	89	0	0
T144	6258	48	0	0
T158	7624	58	0	0
T163	83764	533	0	0
T164	13952	54	0	0
T165	8651	52	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	4027	0	0
T38	11126	83	0	0
T39	9998	113	0	0
T40	12481	91	0	0
T138	5756	40	0	0
T140	16596	116	0	0
T144	6258	34	0	0
T158	7624	32	0	0
T163	83764	543	0	0
T164	13952	79	0	0
T165	8651	86	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3382	0	0
T38	11126	19	0	0
T39	9998	65	0	0
T40	12481	56	0	0
T138	5756	8	0	0
T140	16596	123	0	0
T144	6258	55	0	0
T158	7624	9	0	0
T163	83764	471	0	0
T164	13952	43	0	0
T165	8651	108	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3603	0	0
T38	11126	21	0	0
T39	9998	48	0	0
T40	12481	75	0	0
T138	5756	34	0	0
T140	16596	104	0	0
T144	6258	39	0	0
T158	7624	13	0	0
T163	83764	506	0	0
T164	13952	37	0	0
T165	8651	66	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3700	0	0
T38	11126	37	0	0
T39	9998	124	0	0
T40	12481	99	0	0
T138	5756	26	0	0
T140	16596	120	0	0
T144	6258	17	0	0
T158	7624	9	0	0
T163	83764	573	0	0
T164	13952	2	0	0
T165	8651	76	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3462	0	0
T38	11126	9	0	0
T39	9998	8	0	0
T40	12481	56	0	0
T138	5756	9	0	0
T140	16596	99	0	0
T144	6258	38	0	0
T158	7624	24	0	0
T163	83764	539	0	0
T164	13952	76	0	0
T165	8651	55	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3381	0	0
T38	11126	55	0	0
T39	9998	39	0	0
T40	12481	54	0	0
T138	5756	14	0	0
T139	12879	36	0	0
T140	16596	22	0	0
T158	7624	7	0	0
T163	83764	544	0	0
T164	13952	58	0	0
T165	8651	9	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3457	0	0
T38	11126	108	0	0
T39	9998	62	0	0
T40	12481	12	0	0
T139	12879	92	0	0
T140	16596	63	0	0
T144	6258	29	0	0
T158	7624	3	0	0
T163	83764	520	0	0
T164	13952	50	0	0
T165	8651	102	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3256	0	0
T38	11126	109	0	0
T39	9998	48	0	0
T40	12481	156	0	0
T138	5756	8	0	0
T140	16596	62	0	0
T144	6258	16	0	0
T158	7624	17	0	0
T163	83764	552	0	0
T164	13952	24	0	0
T165	8651	13	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3557	0	0
T38	11126	10	0	0
T39	9998	66	0	0
T40	12481	15	0	0
T138	5756	10	0	0
T140	16596	113	0	0
T144	6258	28	0	0
T158	7624	2	0	0
T163	83764	601	0	0
T164	13952	37	0	0
T165	8651	9	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3971	0	0
T38	11126	103	0	0
T39	9998	116	0	0
T40	12481	112	0	0
T138	5756	7	0	0
T140	16596	87	0	0
T144	6258	42	0	0
T158	7624	29	0	0
T163	83764	541	0	0
T164	13952	36	0	0
T165	8651	120	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3540	0	0
T38	11126	70	0	0
T39	9998	49	0	0
T40	12481	128	0	0
T138	5756	7	0	0
T140	16596	114	0	0
T144	6258	24	0	0
T158	7624	28	0	0
T163	83764	504	0	0
T164	13952	64	0	0
T165	8651	15	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3295	0	0
T38	11126	74	0	0
T39	9998	86	0	0
T40	12481	98	0	0
T138	5756	6	0	0
T140	16596	25	0	0
T144	6258	6	0	0
T158	7624	21	0	0
T163	83764	471	0	0
T164	13952	52	0	0
T165	8651	97	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3628	0	0
T38	11126	73	0	0
T39	9998	51	0	0
T40	12481	152	0	0
T138	5756	5	0	0
T140	16596	60	0	0
T144	6258	18	0	0
T158	7624	34	0	0
T163	83764	543	0	0
T164	13952	8	0	0
T165	8651	42	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3539	0	0
T38	11126	82	0	0
T39	9998	86	0	0
T40	12481	152	0	0
T138	5756	46	0	0
T140	16596	70	0	0
T144	6258	8	0	0
T158	7624	9	0	0
T163	83764	509	0	0
T164	13952	86	0	0
T165	8651	12	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1734	0	0
T38	11126	25	0	0
T39	9998	31	0	0
T40	12481	33	0	0
T138	5756	17	0	0
T140	16596	19	0	0
T144	6258	2	0	0
T158	7624	17	0	0
T163	83764	559	0	0
T164	13952	23	0	0
T165	8651	19	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1475	0	0
T38	11126	25	0	0
T39	9998	30	0	0
T40	12481	25	0	0
T138	5756	13	0	0
T139	12879	16	0	0
T140	16596	16	0	0
T158	7624	17	0	0
T163	83764	480	0	0
T164	13952	14	0	0
T165	8651	3	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1563	0	0
T38	11126	24	0	0
T39	9998	5	0	0
T40	12481	24	0	0
T138	5756	7	0	0
T140	16596	24	0	0
T144	6258	9	0	0
T158	7624	10	0	0
T163	83764	496	0	0
T164	13952	9	0	0
T165	8651	14	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1510	0	0
T38	11126	27	0	0
T39	9998	12	0	0
T40	12481	27	0	0
T138	5756	8	0	0
T140	16596	45	0	0
T144	6258	13	0	0
T158	7624	12	0	0
T163	83764	507	0	0
T164	13952	20	0	0
T165	8651	9	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	2133	0	0
T38	11126	30	0	0
T39	9998	16	0	0
T40	12481	46	0	0
T138	5756	14	0	0
T139	12879	4	0	0
T140	16596	46	0	0
T158	7624	13	0	0
T163	83764	531	0	0
T164	13952	23	0	0
T165	8651	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3365	0	0
T38	0	19	0	0
T39	0	66	0	0
T40	0	129	0	0
T113	30976	0	0	0
T140	0	87	0	0
T158	0	12	0	0
T166	5628	51	0	0
T167	0	8	0	0
T168	0	15	0	0
T169	0	34	0	0
T170	0	24	0	0
T171	30736	0	0	0
T172	41541	0	0	0
T173	111611	0	0	0
T174	1289	0	0	0
T175	8061	0	0	0
T176	30831	0	0	0
T177	2185	0	0	0
T178	1224	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1658	0	0
T38	11126	25	0	0
T39	9998	19	0	0
T40	12481	29	0	0
T138	5756	12	0	0
T140	16596	34	0	0
T144	6258	9	0	0
T158	7624	18	0	0
T163	83764	527	0	0
T164	13952	24	0	0
T165	8651	12	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1563	0	0
T38	11126	27	0	0
T40	12481	13	0	0
T138	5756	6	0	0
T139	12879	8	0	0
T140	16596	31	0	0
T158	7624	37	0	0
T163	83764	512	0	0
T164	13952	28	0	0
T165	8651	11	0	0
T179	36697	64	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1419	0	0
T38	11126	19	0	0
T39	9998	20	0	0
T40	12481	19	0	0
T138	5756	5	0	0
T140	16596	30	0	0
T144	6258	2	0	0
T158	7624	22	0	0
T163	83764	533	0	0
T164	13952	10	0	0
T165	8651	3	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1424	0	0
T38	11126	15	0	0
T39	9998	10	0	0
T40	12481	11	0	0
T138	5756	6	0	0
T139	12879	9	0	0
T140	16596	30	0	0
T158	7624	5	0	0
T163	83764	476	0	0
T164	13952	4	0	0
T165	8651	10	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1467	0	0
T38	11126	22	0	0
T39	9998	7	0	0
T40	12481	17	0	0
T138	5756	8	0	0
T140	16596	22	0	0
T144	6258	4	0	0
T158	7624	20	0	0
T163	83764	509	0	0
T164	13952	15	0	0
T165	8651	5	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1442	0	0
T38	11126	22	0	0
T39	9998	15	0	0
T40	12481	7	0	0
T138	5756	1	0	0
T140	16596	40	0	0
T144	6258	4	0	0
T158	7624	7	0	0
T163	83764	495	0	0
T164	13952	20	0	0
T165	8651	10	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1961	0	0
T38	11126	19	0	0
T39	9998	34	0	0
T40	12481	24	0	0
T138	5756	18	0	0
T140	16596	36	0	0
T144	6258	17	0	0
T158	7624	2	0	0
T163	83764	597	0	0
T164	13952	17	0	0
T165	8651	17	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1361	0	0
T38	11126	19	0	0
T39	9998	6	0	0
T40	12481	7	0	0
T138	5756	1	0	0
T140	16596	27	0	0
T144	6258	4	0	0
T158	7624	2	0	0
T163	83764	480	0	0
T164	13952	24	0	0
T165	8651	6	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	2090	0	0
T38	11126	29	0	0
T39	9998	55	0	0
T40	12481	32	0	0
T138	5756	8	0	0
T140	16596	75	0	0
T144	6258	8	0	0
T158	7624	22	0	0
T163	83764	542	0	0
T164	13952	27	0	0
T165	8651	26	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1625	0	0
T38	11126	20	0	0
T39	9998	25	0	0
T40	12481	35	0	0
T138	5756	16	0	0
T140	16596	21	0	0
T144	6258	6	0	0
T158	7624	10	0	0
T163	83764	538	0	0
T164	13952	20	0	0
T165	8651	7	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1416	0	0
T38	11126	18	0	0
T39	9998	13	0	0
T40	12481	5	0	0
T138	5756	7	0	0
T139	12879	13	0	0
T140	16596	26	0	0
T158	7624	41	0	0
T163	83764	561	0	0
T164	13952	17	0	0
T165	8651	10	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1469	0	0
T38	11126	16	0	0
T39	9998	26	0	0
T40	12481	16	0	0
T138	5756	2	0	0
T140	16596	31	0	0
T144	6258	9	0	0
T158	7624	13	0	0
T163	83764	576	0	0
T164	13952	5	0	0
T165	8651	5	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1465	0	0
T38	11126	16	0	0
T39	9998	21	0	0
T40	12481	13	0	0
T138	5756	11	0	0
T140	16596	19	0	0
T144	6258	7	0	0
T158	7624	39	0	0
T163	83764	607	0	0
T164	13952	12	0	0
T165	8651	4	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1357	0	0
T38	11126	25	0	0
T39	9998	2	0	0
T40	12481	17	0	0
T138	5756	9	0	0
T140	16596	23	0	0
T144	6258	4	0	0
T158	7624	37	0	0
T163	83764	451	0	0
T164	13952	6	0	0
T165	8651	6	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1316	0	0
T38	11126	5	0	0
T39	9998	10	0	0
T40	12481	14	0	0
T138	5756	8	0	0
T140	16596	8	0	0
T144	6258	1	0	0
T158	7624	23	0	0
T163	83764	494	0	0
T164	13952	13	0	0
T165	8651	4	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	1372	0	0
T38	11126	15	0	0
T39	9998	8	0	0
T40	12481	8	0	0
T138	5756	1	0	0
T140	16596	22	0	0
T144	6258	3	0	0
T158	7624	24	0	0
T163	83764	572	0	0
T164	13952	4	0	0
T165	8651	3	0	0