Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8
1	1	Covered	T1,T5,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8
1	1	Covered	T1,T5,T8

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1237668603	2308	0	0
SrcPulseCheck_M	395824239	2308	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237668603	2308	0	0
T1	79578	4	0	0
T2	7625	0	0	0
T3	10028	0	0	0
T4	47239	0	0	0
T5	1177642	3	0	0
T6	1882	0	0	0
T7	6290	0	0	0
T8	1551748	6	0	0
T9	943728	10	0	0
T10	3548	0	0	0
T11	559382	11	0	0
T13	107716	7	0	0
T14	347451	0	0	0
T15	4023	0	0	0
T16	519761	8	0	0
T17	319377	0	0	0
T22	0	5	0	0
T28	0	19	0	0
T29	0	7	0	0
T30	5730	0	0	0
T31	122600	2	0	0
T37	80340	0	0	0
T40	0	7	0	0
T41	0	3	0	0
T57	1379	0	0	0
T105	21911	0	0	0
T132	0	2	0	0
T133	0	7	0	0
T134	0	7	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	6	0	0
T139	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395824239	2308	0	0
T1	75890	4	0	0
T3	2244	0	0	0
T4	14604	0	0	0
T5	385664	3	0	0
T6	144	0	0	0
T7	1832	0	0	0
T8	1539086	6	0	0
T9	1850936	10	0	0
T11	1586590	11	0	0
T12	171504	0	0	0
T13	28728	7	0	0
T14	138516	0	0	0
T15	896	0	0	0
T16	512688	8	0	0
T17	74232	0	0	0
T21	121696	0	0	0
T22	0	5	0	0
T28	0	19	0	0
T29	0	7	0	0
T31	230436	2	0	0
T37	9541	0	0	0
T40	0	7	0	0
T41	0	3	0	0
T105	63954	0	0	0
T132	0	2	0	0
T133	0	7	0	0
T134	0	7	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	6	0	0
T139	0	2	0	0
T140	10272	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T13,T40,T41
1	0	Covered	T13,T40,T41
1	1	Covered	T13,T40,T41

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T40,T41
1	0	Covered	T13,T40,T41
1	1	Covered	T13,T40,T41

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	412556201	165	0	0
SrcPulseCheck_M	131941413	165	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	165	0	0
T13	53858	2	0	0
T14	347451	0	0	0
T15	4023	0	0	0
T16	519761	0	0	0
T17	319377	0	0	0
T30	2865	0	0	0
T31	122600	0	0	0
T37	80340	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T57	1379	0	0	0
T105	21911	0	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	6	0	0
T139	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	165	0	0
T13	14364	2	0	0
T14	69258	0	0	0
T15	896	0	0	0
T16	512688	0	0	0
T17	74232	0	0	0
T21	121696	0	0	0
T31	115218	0	0	0
T37	9541	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T105	63954	0	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	6	0	0
T139	0	2	0	0
T140	10272	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T13,T40
1	0	Covered	T1,T13,T40
1	1	Covered	T1,T13,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T40
1	0	Covered	T1,T13,T40
1	1	Covered	T1,T13,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	412556201	317	0	0
SrcPulseCheck_M	131941413	317	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	317	0	0
T1	79578	4	0	0
T2	7625	0	0	0
T3	10028	0	0	0
T4	47239	0	0	0
T5	588821	0	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	0	0	0
T9	471864	0	0	0
T10	1774	0	0	0
T13	0	5	0	0
T40	0	5	0	0
T41	0	1	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	317	0	0
T1	75890	4	0	0
T3	2244	0	0	0
T4	14604	0	0	0
T5	192832	0	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	0	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	0	5	0	0
T40	0	5	0	0
T41	0	1	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	412556201	1826	0	0
SrcPulseCheck_M	131941413	1826	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1826	0	0
T5	588821	3	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	6	0	0
T9	471864	10	0	0
T10	1774	0	0	0
T11	559382	11	0	0
T12	31801	0	0	0
T13	53858	0	0	0
T16	0	8	0	0
T22	0	5	0	0
T26	0	1	0	0
T28	0	19	0	0
T29	0	7	0	0
T30	2865	0	0	0
T31	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	1826	0	0
T5	192832	3	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	6	0	0
T9	925468	10	0	0
T11	793295	11	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	8	0	0
T22	0	5	0	0
T26	0	1	0	0
T28	0	19	0	0
T29	0	7	0	0
T31	115218	2	0	0