Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3663975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3948259

1

T1

5372

T2

1806

T3

1031

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4280727	1			T1	8606		T2	1901		T3	265
values[0x0]	1664700	1			T1	579		T2	449		T3	462
values[0x1]	1666807	1			T1	562		T2	436		T3	425

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2588718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5023516

1

T1

6235

T2

1992

T3

1057

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27997	1			T3	5		T4	4		T9	2
valid_sources[0x01]	27093	1			T3	3		T9	2		T11	154
valid_sources[0x02]	27913	1			T3	4		T6	1		T9	6
valid_sources[0x03]	28650	1			T3	5		T6	1		T9	3
valid_sources[0x04]	27185	1			T4	10		T9	2		T11	158
valid_sources[0x05]	28289	1			T3	4		T9	2		T10	3
valid_sources[0x06]	31403	1			T3	6		T4	2		T6	3
valid_sources[0x07]	44866	1			T3	3		T6	1		T9	1
valid_sources[0x08]	30470	1			T3	8		T9	3		T11	130
valid_sources[0x09]	29281	1			T4	16		T9	2		T11	152
valid_sources[0x0a]	27284	1			T3	12		T9	3		T11	151
valid_sources[0x0b]	26771	1			T3	6		T9	3		T11	152
valid_sources[0x0c]	28728	1			T3	3		T5	1		T9	5
valid_sources[0x0d]	28335	1			T3	5		T4	6		T9	4
valid_sources[0x0e]	52443	1			T3	2		T4	7		T9	1
valid_sources[0x0f]	28108	1			T3	1		T9	4		T11	161
valid_sources[0x10]	28651	1			T1	313		T3	6		T9	6
valid_sources[0x11]	26808	1			T3	2		T6	1		T9	4
valid_sources[0x12]	32261	1			T3	1		T6	2		T9	7
valid_sources[0x13]	29733	1			T3	4		T9	7		T11	155
valid_sources[0x14]	30393	1			T3	1		T9	2		T11	171
valid_sources[0x15]	30296	1			T3	5		T6	1		T9	1
valid_sources[0x16]	36172	1			T3	2		T4	4		T9	2
valid_sources[0x17]	28382	1			T3	13		T9	3		T11	190
valid_sources[0x18]	28306	1			T3	2		T4	25		T9	4
valid_sources[0x19]	30555	1			T3	2		T9	2		T11	166
valid_sources[0x1a]	28462	1			T3	2		T9	5		T11	175
valid_sources[0x1b]	25550	1			T3	3		T6	1		T9	2
valid_sources[0x1c]	27560	1			T3	1		T9	3		T11	153
valid_sources[0x1d]	28015	1			T3	7		T11	159		T12	29
valid_sources[0x1e]	28588	1			T3	1		T9	3		T11	140
valid_sources[0x1f]	28312	1			T3	3		T4	2		T9	6
valid_sources[0x20]	31485	1			T3	4		T5	3		T9	3
valid_sources[0x21]	26798	1			T3	1		T4	12		T5	1
valid_sources[0x22]	29377	1			T3	4		T4	2		T5	1
valid_sources[0x23]	31249	1			T3	7		T11	164		T12	31
valid_sources[0x24]	28967	1			T3	4		T4	20		T7	11
valid_sources[0x25]	29010	1			T3	2		T9	4		T11	171
valid_sources[0x26]	26681	1			T3	6		T6	1		T9	1
valid_sources[0x27]	26963	1			T3	5		T4	1		T9	1
valid_sources[0x28]	29476	1			T3	3		T4	5		T6	1
valid_sources[0x29]	29065	1			T3	1		T11	160		T12	26
valid_sources[0x2a]	27244	1			T3	9		T5	2		T9	5
valid_sources[0x2b]	32699	1			T6	1		T9	4		T11	152
valid_sources[0x2c]	25713	1			T3	8		T4	11		T9	10
valid_sources[0x2d]	27459	1			T3	3		T4	28		T9	4
valid_sources[0x2e]	29507	1			T3	5		T4	3		T5	1
valid_sources[0x2f]	28984	1			T3	4		T6	1		T9	6
valid_sources[0x30]	34195	1			T3	2		T6	1		T9	5
valid_sources[0x31]	28432	1			T3	4		T9	8		T11	146
valid_sources[0x32]	33658	1			T3	4		T9	3		T11	157
valid_sources[0x33]	29759	1			T3	7		T9	6		T11	140
valid_sources[0x34]	27072	1			T3	7		T9	6		T11	151
valid_sources[0x35]	27527	1			T3	6		T9	2		T11	155
valid_sources[0x36]	26609	1			T3	2		T4	2		T9	4
valid_sources[0x37]	30219	1			T3	5		T9	1		T11	141
valid_sources[0x38]	28552	1			T3	8		T9	8		T11	149
valid_sources[0x39]	28396	1			T8	1		T9	4		T11	163
valid_sources[0x3a]	29046	1			T3	8		T4	1		T9	5
valid_sources[0x3b]	26097	1			T3	5		T4	4		T9	5
valid_sources[0x3c]	28991	1			T3	1		T5	1		T9	1
valid_sources[0x3d]	28343	1			T3	9		T9	5		T11	154
valid_sources[0x3e]	27305	1			T3	6		T4	2		T9	7
valid_sources[0x3f]	28539	1			T3	7		T9	4		T11	151
valid_sources[0x40]	29231	1			T3	7		T4	4		T6	1
valid_sources[0x41]	32488	1			T3	3		T6	1		T9	3
valid_sources[0x42]	25058	1			T3	5		T9	2		T11	144
valid_sources[0x43]	27103	1			T3	5		T4	13		T9	2
valid_sources[0x44]	29086	1			T1	1		T3	1		T4	5
valid_sources[0x45]	29383	1			T3	9		T9	6		T11	141
valid_sources[0x46]	33472	1			T1	2428		T9	6		T10	836
valid_sources[0x47]	30073	1			T3	8		T9	5		T11	162
valid_sources[0x48]	28066	1			T3	7		T9	4		T11	154
valid_sources[0x49]	29279	1			T3	3		T9	4		T11	180
valid_sources[0x4a]	29865	1			T5	1		T6	1		T9	6
valid_sources[0x4b]	27906	1			T3	4		T9	9		T11	145
valid_sources[0x4c]	28055	1			T3	3		T4	5		T9	7
valid_sources[0x4d]	29523	1			T3	5		T9	5		T11	152
valid_sources[0x4e]	50159	1			T3	3		T4	6		T9	4
valid_sources[0x4f]	32724	1			T3	6		T5	2		T9	4
valid_sources[0x50]	26609	1			T3	1		T9	3		T11	141
valid_sources[0x51]	28663	1			T3	2		T4	8		T9	6
valid_sources[0x52]	27339	1			T3	6		T9	2		T11	157
valid_sources[0x53]	35458	1			T3	1		T9	1		T11	144
valid_sources[0x54]	27249	1			T3	2		T9	6		T11	130
valid_sources[0x55]	30209	1			T3	5		T9	7		T11	177
valid_sources[0x56]	26656	1			T3	4		T8	1		T9	5
valid_sources[0x57]	29039	1			T3	4		T6	1		T9	2
valid_sources[0x58]	27528	1			T9	5		T11	162		T12	45
valid_sources[0x59]	34691	1			T3	3		T6	1		T9	5
valid_sources[0x5a]	30339	1			T3	1		T6	1		T9	1
valid_sources[0x5b]	26898	1			T3	3		T4	24		T9	6
valid_sources[0x5c]	27481	1			T3	5		T7	2		T9	7
valid_sources[0x5d]	28439	1			T3	4		T9	2		T11	150
valid_sources[0x5e]	27468	1			T3	6		T4	1		T7	3
valid_sources[0x5f]	25958	1			T3	5		T9	3		T10	151
valid_sources[0x60]	29087	1			T3	4		T6	1		T9	6
valid_sources[0x61]	27580	1			T3	7		T4	14		T5	3
valid_sources[0x62]	27456	1			T3	9		T9	5		T11	171
valid_sources[0x63]	27143	1			T3	5		T4	4		T9	1
valid_sources[0x64]	32433	1			T3	5		T4	9		T9	1
valid_sources[0x65]	29153	1			T3	11		T4	1		T6	2
valid_sources[0x66]	38447	1			T3	1		T9	4		T11	173
valid_sources[0x67]	25864	1			T3	5		T9	7		T11	156
valid_sources[0x68]	26105	1			T3	3		T9	3		T11	144
valid_sources[0x69]	28392	1			T3	5		T9	8		T11	151
valid_sources[0x6a]	28446	1			T3	3		T6	1		T9	1
valid_sources[0x6b]	28397	1			T3	6		T5	1		T6	1
valid_sources[0x6c]	35578	1			T4	2		T5	1		T9	3
valid_sources[0x6d]	29156	1			T3	10		T7	2		T9	4
valid_sources[0x6e]	31178	1			T3	3		T4	4		T9	4
valid_sources[0x6f]	30519	1			T9	1		T11	162		T12	41
valid_sources[0x70]	26985	1			T3	9		T9	8		T10	543
valid_sources[0x71]	27903	1			T3	3		T8	1		T9	4
valid_sources[0x72]	27816	1			T1	451		T3	9		T9	5
valid_sources[0x73]	25847	1			T3	10		T4	9		T6	1
valid_sources[0x74]	28877	1			T3	3		T4	9		T6	1
valid_sources[0x75]	29368	1			T3	9		T8	1		T9	2
valid_sources[0x76]	27669	1			T3	3		T9	4		T10	2
valid_sources[0x77]	28538	1			T3	3		T9	3		T11	157
valid_sources[0x78]	29798	1			T3	11		T6	1		T9	5
valid_sources[0x79]	28947	1			T3	3		T4	22		T9	3
valid_sources[0x7a]	28315	1			T3	1		T6	2		T9	3
valid_sources[0x7b]	26257	1			T3	5		T6	1		T9	3
valid_sources[0x7c]	28068	1			T3	3		T9	3		T11	161
valid_sources[0x7d]	29200	1			T3	11		T4	29		T5	1
valid_sources[0x7e]	27983	1			T3	7		T9	2		T11	127
valid_sources[0x7f]	26448	1			T9	3		T11	160		T12	26
valid_sources[0x80]	28925	1			T3	5		T4	12		T9	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

957342

1

T1

4237

T2

924

T3

147

values[0x0]

all_enables

biggest_size

1507293

1

T1

577

T2

448

T3

460

values[0x1]

all_enables

biggest_size

1483624

1

T1

558

T2

434

T3

424