Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3682880

1

T1

4375

T2

980

T3

121

full_word

3949353

1

T1

5372

T2

1806

T3

1031

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7631773	1			T1	9747		T2	2786		T3	1152
auto[TlIntgErrCmd]	152	1			T71	8		T94	2		T96	12
auto[TlIntgErrData]	149	1			T71	7		T94	3		T96	8
auto[TlIntgErrBoth]	159	1			T71	15		T94	15		T96	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4283873

1

T1

8606

T2

1901

T3

265

auto[1]

3348360

1

T1

1141

T2

885

T3

887

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3326081	1			T1	4369		T2	977		T3	118
auto[TlIntgErrNone]	partial	auto[1]	356381	1			T1	6		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	957592	1			T1	4237		T2	924		T3	147
auto[TlIntgErrNone]	full_word	auto[1]	2991719	1			T1	1135		T2	882		T3	884
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T71	2		T94	2		T96	7
auto[TlIntgErrCmd]	partial	auto[1]	91	1			T71	5		T96	5		T167	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T166	1		T169	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T71	1		T168	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T71	2		T94	1		T96	4
auto[TlIntgErrData]	partial	auto[1]	58	1			T71	3		T94	1		T96	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T94	1		T168	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	13	1			T71	2		T96	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T71	9		T94	3		T96	5
auto[TlIntgErrBoth]	partial	auto[1]	89	1			T71	6		T94	12		T96	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T167	1		T164	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T169	1		T170	2		T171	1