Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T12 |
1 | 0 | Covered | T1,T11,T12 |
1 | 1 | Covered | T11,T12,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T12 |
1 | 0 | Covered | T11,T12,T15 |
1 | 1 | Covered | T1,T11,T12 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1214148429 |
2340 |
0 |
0 |
T1 |
429026 |
2 |
0 |
0 |
T2 |
73916 |
0 |
0 |
0 |
T3 |
391996 |
0 |
0 |
0 |
T4 |
209624 |
0 |
0 |
0 |
T5 |
2404 |
0 |
0 |
0 |
T6 |
2692 |
0 |
0 |
0 |
T7 |
6678 |
0 |
0 |
0 |
T8 |
6210 |
0 |
0 |
0 |
T9 |
1597542 |
0 |
0 |
0 |
T10 |
1329106 |
0 |
0 |
0 |
T11 |
191740 |
8 |
0 |
0 |
T12 |
138595 |
7 |
0 |
0 |
T13 |
201053 |
0 |
0 |
0 |
T14 |
62220 |
0 |
0 |
0 |
T15 |
8064 |
5 |
0 |
0 |
T16 |
35441 |
2 |
0 |
0 |
T17 |
10380 |
0 |
0 |
0 |
T18 |
72217 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T28 |
10927 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T32 |
0 |
7 |
0 |
0 |
T36 |
0 |
7 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T45 |
0 |
7 |
0 |
0 |
T47 |
0 |
11 |
0 |
0 |
T52 |
36416 |
7 |
0 |
0 |
T65 |
0 |
15 |
0 |
0 |
T79 |
0 |
7 |
0 |
0 |
T140 |
0 |
7 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
7 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
382217289 |
2340 |
0 |
0 |
T1 |
71010 |
2 |
0 |
0 |
T2 |
9696 |
0 |
0 |
0 |
T3 |
94680 |
0 |
0 |
0 |
T4 |
416404 |
0 |
0 |
0 |
T7 |
1008 |
0 |
0 |
0 |
T8 |
1082 |
0 |
0 |
0 |
T9 |
201478 |
0 |
0 |
0 |
T10 |
223362 |
0 |
0 |
0 |
T11 |
808998 |
8 |
0 |
0 |
T12 |
50598 |
7 |
0 |
0 |
T13 |
38128 |
0 |
0 |
0 |
T14 |
18702 |
0 |
0 |
0 |
T15 |
9769 |
5 |
0 |
0 |
T16 |
107264 |
2 |
0 |
0 |
T17 |
2081 |
0 |
0 |
0 |
T18 |
229035 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
189225 |
0 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T32 |
0 |
7 |
0 |
0 |
T36 |
0 |
7 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T45 |
0 |
7 |
0 |
0 |
T47 |
0 |
11 |
0 |
0 |
T52 |
14390 |
7 |
0 |
0 |
T65 |
0 |
15 |
0 |
0 |
T79 |
0 |
7 |
0 |
0 |
T140 |
0 |
7 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
7 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T12,T15 |
1 | 0 | Covered | T1,T12,T15 |
1 | 1 | Covered | T12,T15,T52 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T12,T15 |
1 | 0 | Covered | T12,T15,T52 |
1 | 1 | Covered | T1,T12,T15 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404716143 |
171 |
0 |
0 |
T1 |
214513 |
1 |
0 |
0 |
T2 |
36958 |
0 |
0 |
0 |
T3 |
195998 |
0 |
0 |
0 |
T4 |
104812 |
0 |
0 |
0 |
T5 |
1202 |
0 |
0 |
0 |
T6 |
1346 |
0 |
0 |
0 |
T7 |
3339 |
0 |
0 |
0 |
T8 |
3105 |
0 |
0 |
0 |
T9 |
798771 |
0 |
0 |
0 |
T10 |
664553 |
0 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
6 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T79 |
0 |
2 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127405763 |
171 |
0 |
0 |
T1 |
35505 |
1 |
0 |
0 |
T2 |
4848 |
0 |
0 |
0 |
T3 |
47340 |
0 |
0 |
0 |
T4 |
208202 |
0 |
0 |
0 |
T7 |
504 |
0 |
0 |
0 |
T8 |
541 |
0 |
0 |
0 |
T9 |
100739 |
0 |
0 |
0 |
T10 |
111681 |
0 |
0 |
0 |
T11 |
269666 |
0 |
0 |
0 |
T12 |
16866 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
6 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T79 |
0 |
2 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T12,T15 |
1 | 0 | Covered | T1,T12,T15 |
1 | 1 | Covered | T12,T15,T52 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T12,T15 |
1 | 0 | Covered | T12,T15,T52 |
1 | 1 | Covered | T1,T12,T15 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404716143 |
318 |
0 |
0 |
T1 |
214513 |
1 |
0 |
0 |
T2 |
36958 |
0 |
0 |
0 |
T3 |
195998 |
0 |
0 |
0 |
T4 |
104812 |
0 |
0 |
0 |
T5 |
1202 |
0 |
0 |
0 |
T6 |
1346 |
0 |
0 |
0 |
T7 |
3339 |
0 |
0 |
0 |
T8 |
3105 |
0 |
0 |
0 |
T9 |
798771 |
0 |
0 |
0 |
T10 |
664553 |
0 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T47 |
0 |
5 |
0 |
0 |
T52 |
0 |
5 |
0 |
0 |
T79 |
0 |
5 |
0 |
0 |
T140 |
0 |
5 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
5 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127405763 |
318 |
0 |
0 |
T1 |
35505 |
1 |
0 |
0 |
T2 |
4848 |
0 |
0 |
0 |
T3 |
47340 |
0 |
0 |
0 |
T4 |
208202 |
0 |
0 |
0 |
T7 |
504 |
0 |
0 |
0 |
T8 |
541 |
0 |
0 |
0 |
T9 |
100739 |
0 |
0 |
0 |
T10 |
111681 |
0 |
0 |
0 |
T11 |
269666 |
0 |
0 |
0 |
T12 |
16866 |
5 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T47 |
0 |
5 |
0 |
0 |
T52 |
0 |
5 |
0 |
0 |
T79 |
0 |
5 |
0 |
0 |
T140 |
0 |
5 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T11,T16,T25 |
1 | 0 | Covered | T11,T16,T25 |
1 | 1 | Covered | T11,T16,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T11,T16,T25 |
1 | 0 | Covered | T11,T16,T25 |
1 | 1 | Covered | T11,T16,T25 |
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404716143 |
1851 |
0 |
0 |
T11 |
191740 |
8 |
0 |
0 |
T12 |
138595 |
0 |
0 |
0 |
T13 |
201053 |
0 |
0 |
0 |
T14 |
62220 |
0 |
0 |
0 |
T15 |
8064 |
0 |
0 |
0 |
T16 |
35441 |
2 |
0 |
0 |
T17 |
10380 |
0 |
0 |
0 |
T18 |
72217 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T28 |
10927 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T32 |
0 |
7 |
0 |
0 |
T36 |
0 |
7 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T52 |
36416 |
0 |
0 |
0 |
T65 |
0 |
15 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127405763 |
1851 |
0 |
0 |
T11 |
269666 |
8 |
0 |
0 |
T12 |
16866 |
0 |
0 |
0 |
T13 |
38128 |
0 |
0 |
0 |
T14 |
18702 |
0 |
0 |
0 |
T15 |
9769 |
0 |
0 |
0 |
T16 |
107264 |
2 |
0 |
0 |
T17 |
2081 |
0 |
0 |
0 |
T18 |
229035 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
189225 |
0 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T32 |
0 |
7 |
0 |
0 |
T36 |
0 |
7 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T52 |
14390 |
0 |
0 |
0 |
T65 |
0 |
15 |
0 |
0 |