Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	2526072	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	2526072	0	0
T1	214513	2178	0	0
T2	36958	1663	0	0
T3	195998	1663	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	0	0	0
T11	0	7484	0	0
T12	0	1663	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	2685	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	2721033	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	2721033	0	0
T1	214513	1092	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	0	0	0
T11	0	4160	0	0
T12	0	832	0	0
T13	0	3675	0	0
T14	0	832	0	0
T15	0	1344	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	164669	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	164669	0	0
T10	664553	912	0	0
T11	191740	1081	0	0
T12	138595	0	0	0
T13	201053	0	0	0
T14	62220	0	0	0
T15	8064	0	0	0
T16	35441	128	0	0
T17	10380	1	0	0
T18	72217	369	0	0
T20	0	35	0	0
T21	0	39	0	0
T25	0	65	0	0
T26	0	23	0	0
T27	0	582	0	0
T28	10927	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	354804	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	354804	0	0
T10	664553	912	0	0
T11	191740	1081	0	0
T12	138595	0	0	0
T13	201053	0	0	0
T14	62220	0	0	0
T15	8064	0	0	0
T16	35441	128	0	0
T17	10380	1	0	0
T18	72217	1644	0	0
T20	0	35	0	0
T21	0	176	0	0
T25	0	217	0	0
T26	0	23	0	0
T27	0	1719	0	0
T28	10927	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	6209028	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	6209028	0	0
T1	214513	8666	0	0
T2	36958	1954	0	0
T3	195998	320	0	0
T4	104812	73	0	0
T5	1202	25	0	0
T6	1346	71	0	0
T7	3339	23	0	0
T8	3105	11	0	0
T9	798771	961	0	0
T10	664553	11675	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406916588	11998772	0	0
DepthKnown_A	406916588	406782894	0	0
RvalidKnown_A	406916588	406782894	0	0
WreadyKnown_A	406916588	406782894	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	11998772	0	0
T1	214513	26631	0	0
T2	36958	1954	0	0
T3	195998	320	0	0
T4	104812	73	0	0
T5	1202	25	0	0
T6	1346	71	0	0
T7	3339	23	0	0
T8	3105	11	0	0
T9	798771	961	0	0
T10	664553	11625	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406916588	406782894	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0