Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T17
1	0	Covered	T10,T11,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Covered	T10,T11,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T16,T25

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T25
1	0	Covered	T11,T16,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T11,T16,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T17
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	659527669	530725706	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	659527669	3189301	0	0
GntImpliesValid_A	659527669	3189301	0	0
GrantKnown_A	659527669	530725706	0	0
IdxKnown_A	659527669	530725706	0	0
IndexIsCorrect_A	659527669	3189301	0	0
LockArbDecision_A	659527669	0	0	0
NoReadyValidNoGrant_A	659527669	0	0	0
ReadyAndValidImplyGrant_A	659527669	3189301	0	0
ReqAndReadyImplyGrant_A	659527669	3189301	0	0
ReqImpliesValid_A	659527669	3189301	0	0
ReqStaysHighUntilGranted0_M	659527669	0	0	0
RoundRobin_A	659527669	3	0	906
ValidKnown_A	659527669	530725706	0	0
gen_data_port_assertion.DataFlow_A	659527669	3189301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	530725706	0	0
T1	250018	249243	0	0
T2	41806	41732	0	0
T3	243338	243258	0	0
T4	313014	312205	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	4347	3784	0	0
T8	4187	3246	0	0
T9	1000249	894408	0	0
T10	887915	772057	0	0
T11	539332	262981	0	0
T12	33732	16866	0	0
T13	38128	38128	0	0
T14	18702	18288	0	0
T15	9769	9769	0	0
T16	0	107264	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	530725706	0	0
T1	250018	249243	0	0
T2	41806	41732	0	0
T3	243338	243258	0	0
T4	313014	312205	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	4347	3784	0	0
T8	4187	3246	0	0
T9	1000249	894408	0	0
T10	887915	772057	0	0
T11	539332	262981	0	0
T12	33732	16866	0	0
T13	38128	38128	0	0
T14	18702	18288	0	0
T15	9769	9769	0	0
T16	0	107264	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	530725706	0	0
T1	250018	249243	0	0
T2	41806	41732	0	0
T3	243338	243258	0	0
T4	313014	312205	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	4347	3784	0	0
T8	4187	3246	0	0
T9	1000249	894408	0	0
T10	887915	772057	0	0
T11	539332	262981	0	0
T12	33732	16866	0	0
T13	38128	38128	0	0
T14	18702	18288	0	0
T15	9769	9769	0	0
T16	0	107264	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3	0	906
T53	896833	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	454938	0	0	1
T57	571017	0	0	1
T58	94457	0	0	1
T59	1200	0	0	1
T60	10116	0	0	1
T61	305724	0	0	1
T62	1257	0	0	1
T63	984796	0	0	1
T64	87985	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	530725706	0	0
T1	250018	249243	0	0
T2	41806	41732	0	0
T3	243338	243258	0	0
T4	313014	312205	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	4347	3784	0	0
T8	4187	3246	0	0
T9	1000249	894408	0	0
T10	887915	772057	0	0
T11	539332	262981	0	0
T12	33732	16866	0	0
T13	38128	38128	0	0
T14	18702	18288	0	0
T15	9769	9769	0	0
T16	0	107264	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659527669	3189301	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	776234	7127	0	0
T11	539332	13777	0	0
T12	33732	832	0	0
T13	76256	832	0	0
T14	37404	832	0	0
T15	19538	1344	0	0
T16	214528	5682	0	0
T17	4162	50	0	0
T18	458070	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T25	0	534	0	0
T26	0	155	0	0
T27	0	2859	0	0
T29	0	7634	0	0
T30	189225	0	0	0
T36	0	2721	0	0
T43	0	2959	0	0
T52	28780	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T17
1	0	Covered	T10,T11,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Covered	T10,T11,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T11,T17
0	0	1	Unreachable
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127405763	29072588	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	127405763	653850	0	0
GntImpliesValid_A	127405763	653850	0	0
GrantKnown_A	127405763	29072588	0	0
IdxKnown_A	127405763	29072588	0	0
IndexIsCorrect_A	127405763	653850	0	0
LockArbDecision_A	127405763	0	0	0
NoReadyValidNoGrant_A	127405763	0	0	0
ReadyAndValidImplyGrant_A	127405763	653850	0	0
ReqAndReadyImplyGrant_A	127405763	653850	0	0
ReqImpliesValid_A	127405763	653850	0	0
ReqStaysHighUntilGranted0_M	127405763	0	0	0
RoundRobin_A	127405763	0	0	0
ValidKnown_A	127405763	29072588	0	0
gen_data_port_assertion.DataFlow_A	127405763	653850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	29072588	0	0
T7	504	504	0	0
T8	541	216	0	0
T9	100739	95696	0	0
T10	111681	107576	0	0
T11	269666	121512	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	29072588	0	0
T7	504	504	0	0
T8	541	216	0	0
T9	100739	95696	0	0
T10	111681	107576	0	0
T11	269666	121512	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	29072588	0	0
T7	504	504	0	0
T8	541	216	0	0
T9	100739	95696	0	0
T10	111681	107576	0	0
T11	269666	121512	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	29072588	0	0
T7	504	504	0	0
T8	541	216	0	0
T9	100739	95696	0	0
T10	111681	107576	0	0
T11	269666	121512	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T17	2081	1664	0	0
T18	0	225816	0	0
T20	0	2624	0	0
T21	0	2200	0	0
T26	0	3056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	653850	0	0
T10	111681	4933	0	0
T11	269666	5657	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	0	0	0
T17	2081	50	0	0
T18	229035	2219	0	0
T20	0	169	0	0
T21	0	167	0	0
T26	0	155	0	0
T27	0	2584	0	0
T29	0	4134	0	0
T43	0	2701	0	0
T52	14390	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T16,T25

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T25
1	0	Covered	T11,T16,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T11,T16,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T16,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T16,T25
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T16,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T16,T25
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127405763	97022432	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	127405763	517248	0	0
GntImpliesValid_A	127405763	517248	0	0
GrantKnown_A	127405763	97022432	0	0
IdxKnown_A	127405763	97022432	0	0
IndexIsCorrect_A	127405763	517248	0	0
LockArbDecision_A	127405763	0	0	0
NoReadyValidNoGrant_A	127405763	0	0	0
ReadyAndValidImplyGrant_A	127405763	517248	0	0
ReqAndReadyImplyGrant_A	127405763	517248	0	0
ReqImpliesValid_A	127405763	517248	0	0
ReqStaysHighUntilGranted0_M	127405763	0	0	0
RoundRobin_A	127405763	0	0	0
ValidKnown_A	127405763	97022432	0	0
gen_data_port_assertion.DataFlow_A	127405763	517248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	97022432	0	0
T1	35505	34816	0	0
T2	4848	4848	0	0
T3	47340	47340	0	0
T4	208202	207400	0	0
T7	504	0	0	0
T8	541	0	0	0
T9	100739	0	0	0
T10	111681	0	0	0
T11	269666	141469	0	0
T12	16866	16866	0	0
T13	0	38128	0	0
T14	0	18288	0	0
T15	0	9769	0	0
T16	0	107264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	97022432	0	0
T1	35505	34816	0	0
T2	4848	4848	0	0
T3	47340	47340	0	0
T4	208202	207400	0	0
T7	504	0	0	0
T8	541	0	0	0
T9	100739	0	0	0
T10	111681	0	0	0
T11	269666	141469	0	0
T12	16866	16866	0	0
T13	0	38128	0	0
T14	0	18288	0	0
T15	0	9769	0	0
T16	0	107264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	97022432	0	0
T1	35505	34816	0	0
T2	4848	4848	0	0
T3	47340	47340	0	0
T4	208202	207400	0	0
T7	504	0	0	0
T8	541	0	0	0
T9	100739	0	0	0
T10	111681	0	0	0
T11	269666	141469	0	0
T12	16866	16866	0	0
T13	0	38128	0	0
T14	0	18288	0	0
T15	0	9769	0	0
T16	0	107264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	97022432	0	0
T1	35505	34816	0	0
T2	4848	4848	0	0
T3	47340	47340	0	0
T4	208202	207400	0	0
T7	504	0	0	0
T8	541	0	0	0
T9	100739	0	0	0
T10	111681	0	0	0
T11	269666	141469	0	0
T12	16866	16866	0	0
T13	0	38128	0	0
T14	0	18288	0	0
T15	0	9769	0	0
T16	0	107264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127405763	517248	0	0
T11	269666	1061	0	0
T12	16866	0	0	0
T13	38128	0	0	0
T14	18702	0	0	0
T15	9769	0	0	0
T16	107264	5682	0	0
T17	2081	0	0	0
T18	229035	0	0	0
T25	0	534	0	0
T27	0	275	0	0
T29	0	3500	0	0
T30	189225	0	0	0
T31	0	2714	0	0
T32	0	15	0	0
T36	0	2721	0	0
T43	0	258	0	0
T52	14390	0	0	0
T65	0	7855	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T17
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404716143	404630686	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	404716143	2018203	0	0
GntImpliesValid_A	404716143	2018203	0	0
GrantKnown_A	404716143	404630686	0	0
IdxKnown_A	404716143	404630686	0	0
IndexIsCorrect_A	404716143	2018203	0	0
LockArbDecision_A	404716143	0	0	0
NoReadyValidNoGrant_A	404716143	0	0	0
ReadyAndValidImplyGrant_A	404716143	2018203	0	0
ReqAndReadyImplyGrant_A	404716143	2018203	0	0
ReqImpliesValid_A	404716143	2018203	0	0
ReqStaysHighUntilGranted0_M	404716143	0	0	0
RoundRobin_A	404716143	3	0	906
ValidKnown_A	404716143	404630686	0	0
gen_data_port_assertion.DataFlow_A	404716143	2018203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	404630686	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	404630686	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	404630686	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	3	0	906
T53	896833	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	454938	0	0	1
T57	571017	0	0	1
T58	94457	0	0	1
T59	1200	0	0	1
T60	10116	0	0	1
T61	305724	0	0	1
T62	1257	0	0	1
T63	984796	0	0	1
T64	87985	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	404630686	0	0
T1	214513	214427	0	0
T2	36958	36884	0	0
T3	195998	195918	0	0
T4	104812	104805	0	0
T5	1202	1118	0	0
T6	1346	1263	0	0
T7	3339	3280	0	0
T8	3105	3030	0	0
T9	798771	798712	0	0
T10	664553	664481	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404716143	2018203	0	0
T1	214513	1088	0	0
T2	36958	832	0	0
T3	195998	832	0	0
T4	104812	832	0	0
T5	1202	0	0	0
T6	1346	0	0	0
T7	3339	0	0	0
T8	3105	0	0	0
T9	798771	0	0	0
T10	664553	2194	0	0
T11	0	7059	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1344	0	0