Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.93	98.30	94.11	98.61	89.36	97.06	95.83	98.22

Total test records in report: 1081

T1009	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3231565465	May 23 02:03:08 PM PDT 24	May 23 02:03:11 PM PDT 24	104427011 ps
T1010	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2330242499	May 23 02:04:10 PM PDT 24	May 23 02:04:11 PM PDT 24	26202398 ps
T163	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.152785569	May 23 02:03:33 PM PDT 24	May 23 02:03:37 PM PDT 24	419157365 ps
T1011	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3116208411	May 23 02:02:30 PM PDT 24	May 23 02:02:32 PM PDT 24	449887938 ps
T105	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2625777619	May 23 02:03:24 PM PDT 24	May 23 02:03:28 PM PDT 24	485488611 ps
T1012	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.3939734407	May 23 02:04:23 PM PDT 24	May 23 02:04:25 PM PDT 24	24248414 ps
T1013	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.564657032	May 23 02:02:31 PM PDT 24	May 23 02:02:46 PM PDT 24	402093715 ps
T1014	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3903361869	May 23 02:02:46 PM PDT 24	May 23 02:02:47 PM PDT 24	51340643 ps
T1015	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.1880326611	May 23 02:04:21 PM PDT 24	May 23 02:04:23 PM PDT 24	49943840 ps
T108	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2269384723	May 23 02:03:35 PM PDT 24	May 23 02:03:40 PM PDT 24	578939758 ps
T1016	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2558124770	May 23 02:03:48 PM PDT 24	May 23 02:03:54 PM PDT 24	298812706 ps
T1017	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2223722543	May 23 02:03:49 PM PDT 24	May 23 02:03:51 PM PDT 24	377218830 ps
T1018	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3142088431	May 23 02:04:07 PM PDT 24	May 23 02:04:10 PM PDT 24	94395040 ps
T85	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1309114720	May 23 02:02:20 PM PDT 24	May 23 02:02:22 PM PDT 24	42082965 ps
T1019	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.967779784	May 23 02:03:34 PM PDT 24	May 23 02:03:38 PM PDT 24	1129508419 ps
T1020	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2817609453	May 23 02:03:08 PM PDT 24	May 23 02:03:12 PM PDT 24	930752243 ps
T1021	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1616262116	May 23 02:02:46 PM PDT 24	May 23 02:03:09 PM PDT 24	1051025635 ps
T1022	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3302439739	May 23 02:02:30 PM PDT 24	May 23 02:02:33 PM PDT 24	92816610 ps
T1023	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3396280504	May 23 02:03:48 PM PDT 24	May 23 02:03:50 PM PDT 24	16055430 ps
T1024	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.773630661	May 23 02:03:35 PM PDT 24	May 23 02:03:39 PM PDT 24	663856835 ps
T1025	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2940477968	May 23 02:02:44 PM PDT 24	May 23 02:02:46 PM PDT 24	26893751 ps
T1026	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3075934740	May 23 02:04:09 PM PDT 24	May 23 02:04:14 PM PDT 24	192541352 ps
T1027	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.190008898	May 23 02:04:07 PM PDT 24	May 23 02:04:09 PM PDT 24	41617234 ps
T1028	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3074217153	May 23 02:02:44 PM PDT 24	May 23 02:02:48 PM PDT 24	60825779 ps
T1029	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2998513536	May 23 02:03:35 PM PDT 24	May 23 02:03:50 PM PDT 24	881863627 ps
T1030	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.597343068	May 23 02:02:19 PM PDT 24	May 23 02:02:22 PM PDT 24	109768211 ps
T1031	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2885927413	May 23 02:03:11 PM PDT 24	May 23 02:03:13 PM PDT 24	123039730 ps
T1032	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2279351436	May 23 02:03:35 PM PDT 24	May 23 02:03:45 PM PDT 24	350647163 ps
T1033	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3783350492	May 23 02:04:07 PM PDT 24	May 23 02:04:10 PM PDT 24	38330223 ps
T1034	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3520295305	May 23 02:03:20 PM PDT 24	May 23 02:03:24 PM PDT 24	43448661 ps
T111	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.126281790	May 23 02:03:09 PM PDT 24	May 23 02:03:13 PM PDT 24	161158219 ps
T86	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3486125382	May 23 02:02:57 PM PDT 24	May 23 02:02:59 PM PDT 24	36722920 ps
T1035	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1432104601	May 23 02:02:20 PM PDT 24	May 23 02:02:29 PM PDT 24	1249241784 ps
T1036	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1175325545	May 23 02:03:34 PM PDT 24	May 23 02:03:38 PM PDT 24	102689108 ps
T1037	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.97722525	May 23 02:02:36 PM PDT 24	May 23 02:02:37 PM PDT 24	12761950 ps
T1038	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2852691700	May 23 02:03:34 PM PDT 24	May 23 02:03:36 PM PDT 24	14812126 ps
T1039	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.490970333	May 23 02:04:08 PM PDT 24	May 23 02:04:23 PM PDT 24	488136987 ps
T1040	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2860929510	May 23 02:03:51 PM PDT 24	May 23 02:03:54 PM PDT 24	108344425 ps
T1041	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.219648056	May 23 02:04:07 PM PDT 24	May 23 02:04:09 PM PDT 24	92878815 ps
T1042	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.851954991	May 23 02:03:24 PM PDT 24	May 23 02:03:27 PM PDT 24	782212984 ps
T1043	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1144025901	May 23 02:03:20 PM PDT 24	May 23 02:03:23 PM PDT 24	229447490 ps
T106	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1398761925	May 23 02:03:34 PM PDT 24	May 23 02:03:37 PM PDT 24	64707602 ps
T1044	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2031075174	May 23 02:03:11 PM PDT 24	May 23 02:03:14 PM PDT 24	62522994 ps
T1045	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3818203154	May 23 02:03:48 PM PDT 24	May 23 02:03:51 PM PDT 24	45800424 ps
T1046	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.567381256	May 23 02:02:56 PM PDT 24	May 23 02:02:57 PM PDT 24	12463890 ps
T1047	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.311233943	May 23 02:04:09 PM PDT 24	May 23 02:04:11 PM PDT 24	40741945 ps
T1048	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1126023438	May 23 02:03:35 PM PDT 24	May 23 02:03:43 PM PDT 24	2011145152 ps
T1049	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1432191341	May 23 02:03:10 PM PDT 24	May 23 02:03:12 PM PDT 24	110229077 ps
T1050	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.3306620796	May 23 02:03:49 PM PDT 24	May 23 02:03:51 PM PDT 24	28213910 ps
T1051	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1959092293	May 23 02:03:34 PM PDT 24	May 23 02:03:37 PM PDT 24	80529347 ps
T1052	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3140917924	May 23 02:03:49 PM PDT 24	May 23 02:03:52 PM PDT 24	207041179 ps
T1053	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3063862658	May 23 02:02:58 PM PDT 24	May 23 02:03:01 PM PDT 24	27599151 ps
T1054	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1047684171	May 23 02:03:50 PM PDT 24	May 23 02:03:55 PM PDT 24	611785051 ps
T1055	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3400227762	May 23 02:04:07 PM PDT 24	May 23 02:04:09 PM PDT 24	61304244 ps
T1056	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3291548999	May 23 02:04:21 PM PDT 24	May 23 02:04:23 PM PDT 24	56193716 ps
T1057	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1242461300	May 23 02:03:49 PM PDT 24	May 23 02:03:52 PM PDT 24	55778234 ps
T1058	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.827716114	May 23 02:04:26 PM PDT 24	May 23 02:04:28 PM PDT 24	15917569 ps
T1059	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3942936359	May 23 02:02:43 PM PDT 24	May 23 02:02:46 PM PDT 24	188781257 ps
T171	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.255186283	May 23 02:03:21 PM PDT 24	May 23 02:03:42 PM PDT 24	1364673097 ps
T1060	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1386102729	May 23 02:03:35 PM PDT 24	May 23 02:03:39 PM PDT 24	48774315 ps
T1061	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3623965677	May 23 02:04:09 PM PDT 24	May 23 02:04:10 PM PDT 24	22746588 ps
T1062	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4152024018	May 23 02:03:21 PM PDT 24	May 23 02:03:34 PM PDT 24	529622646 ps
T1063	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.521627915	May 23 02:04:06 PM PDT 24	May 23 02:04:08 PM PDT 24	16375049 ps
T1064	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1693163678	May 23 02:02:21 PM PDT 24	May 23 02:02:24 PM PDT 24	163215237 ps
T1065	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3090786502	May 23 02:04:23 PM PDT 24	May 23 02:04:25 PM PDT 24	135099320 ps
T1066	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3491048003	May 23 02:02:58 PM PDT 24	May 23 02:03:02 PM PDT 24	478367168 ps
T1067	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.492425854	May 23 02:02:58 PM PDT 24	May 23 02:03:20 PM PDT 24	1395972952 ps
T1068	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.281444936	May 23 02:02:46 PM PDT 24	May 23 02:02:51 PM PDT 24	683688835 ps
T1069	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1728351800	May 23 02:03:48 PM PDT 24	May 23 02:03:52 PM PDT 24	176065872 ps
T1070	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3571794372	May 23 02:04:06 PM PDT 24	May 23 02:04:08 PM PDT 24	13818063 ps
T1071	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1915559880	May 23 02:04:21 PM PDT 24	May 23 02:04:22 PM PDT 24	84444924 ps
T1072	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2436502611	May 23 02:03:11 PM PDT 24	May 23 02:03:35 PM PDT 24	1223669266 ps
T1073	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1714972848	May 23 02:03:10 PM PDT 24	May 23 02:03:12 PM PDT 24	14716914 ps
T1074	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.840175484	May 23 02:03:09 PM PDT 24	May 23 02:03:11 PM PDT 24	23937917 ps
T1075	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4197998892	May 23 02:03:49 PM PDT 24	May 23 02:03:53 PM PDT 24	40240697 ps
T1076	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.60513238	May 23 02:03:49 PM PDT 24	May 23 02:03:52 PM PDT 24	33168920 ps
T1077	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1140152586	May 23 02:03:08 PM PDT 24	May 23 02:03:11 PM PDT 24	126697644 ps
T1078	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1597253502	May 23 02:03:21 PM PDT 24	May 23 02:03:24 PM PDT 24	220200641 ps
T1079	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.332038683	May 23 02:03:22 PM PDT 24	May 23 02:03:23 PM PDT 24	33303136 ps
T1080	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.673062567	May 23 02:03:23 PM PDT 24	May 23 02:03:27 PM PDT 24	44296997 ps
T1081	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1929860699	May 23 02:03:35 PM PDT 24	May 23 02:03:37 PM PDT 24	12115655 ps

Test location	/workspace/coverage/default/42.spi_device_flash_mode.2645494309
Short name	T1
Test name
Test status
Simulation time	7150377533 ps
CPU time	33.06 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:49:16 PM PDT 24
Peak memory	240848 kb
Host	smart-d11743b8-8e75-4f29-b282-275e12326317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645494309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2645494309
Directory	/workspace/42.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm.3521006278
Short name	T27
Test name
Test status
Simulation time	24954675402 ps
CPU time	107.24 seconds
Started	May 23 02:47:51 PM PDT 24
Finished	May 23 02:49:40 PM PDT 24
Peak memory	249124 kb
Host	smart-c4e2956e-467d-498c-82fc-e73f516f4811
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521006278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3521006278
Directory	/workspace/40.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3947141820
Short name	T11
Test name
Test status
Simulation time	19174102208 ps
CPU time	175.12 seconds
Started	May 23 02:47:46 PM PDT 24
Finished	May 23 02:50:43 PM PDT 24
Peak memory	249120 kb
Host	smart-fbc3fdb8-76e6-49ea-8088-6267e1672695
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947141820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl e.3947141820
Directory	/workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/1.spi_device_stress_all.2199355936
Short name	T36
Test name
Test status
Simulation time	9599731498 ps
CPU time	170.12 seconds
Started	May 23 02:40:34 PM PDT 24
Finished	May 23 02:43:25 PM PDT 24
Peak memory	253768 kb
Host	smart-e44ff538-4a49-4650-8043-4bda05ee8443
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199355936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres s_all.2199355936
Directory	/workspace/1.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1526261602
Short name	T120
Test name
Test status
Simulation time	76957244 ps
CPU time	1.97 seconds
Started	May 23 02:03:33 PM PDT 24
Finished	May 23 02:03:35 PM PDT 24
Peak memory	215160 kb
Host	smart-f2e3e3bd-2d97-40c6-8325-4eeb0983aef3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526261602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 1526261602
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/default/14.spi_device_stress_all.4183052346
Short name	T39
Test name
Test status
Simulation time	401623457914 ps
CPU time	405.23 seconds
Started	May 23 02:43:36 PM PDT 24
Finished	May 23 02:50:22 PM PDT 24
Peak memory	255056 kb
Host	smart-515ed2ae-4557-48df-89fa-8a3588d717cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183052346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre ss_all.4183052346
Directory	/workspace/14.spi_device_stress_all/latest

Test location	/workspace/coverage/default/29.spi_device_stress_all.3821655442
Short name	T50
Test name
Test status
Simulation time	30158879364 ps
CPU time	415.12 seconds
Started	May 23 02:46:02 PM PDT 24
Finished	May 23 02:52:59 PM PDT 24
Peak memory	281868 kb
Host	smart-dc18740f-93f7-4f03-ab05-3e8afef5036d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821655442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre ss_all.3821655442
Directory	/workspace/29.spi_device_stress_all/latest

Test location	/workspace/coverage/default/10.spi_device_stress_all.1178090251
Short name	T192
Test name
Test status
Simulation time	22544699874 ps
CPU time	316.5 seconds
Started	May 23 02:42:44 PM PDT 24
Finished	May 23 02:48:01 PM PDT 24
Peak memory	281660 kb
Host	smart-c3ded6d7-3fb4-4484-8fd5-ccd617db5eae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178090251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre ss_all.1178090251
Directory	/workspace/10.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1655843217
Short name	T96
Test name
Test status
Simulation time	1129237063 ps
CPU time	19.06 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:04:08 PM PDT 24
Peak memory	215448 kb
Host	smart-77d5a7b6-fa5a-4f98-af9e-ab3a51a10ec5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655843217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.1655843217
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/18.spi_device_flash_all.3530814796
Short name	T30
Test name
Test status
Simulation time	11747486941 ps
CPU time	54.36 seconds
Started	May 23 02:44:21 PM PDT 24
Finished	May 23 02:45:17 PM PDT 24
Peak memory	224432 kb
Host	smart-e3eb51af-1de8-43be-b01f-98bd8e464c2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530814796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3530814796
Directory	/workspace/18.spi_device_flash_all/latest

Test location	/workspace/coverage/default/0.spi_device_ram_cfg.3691427254
Short name	T74
Test name
Test status
Simulation time	29003559 ps
CPU time	0.75 seconds
Started	May 23 02:39:48 PM PDT 24
Finished	May 23 02:39:50 PM PDT 24
Peak memory	216104 kb
Host	smart-7eb74b65-7208-4aef-8150-a97eb0b9ae01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691427254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3691427254
Directory	/workspace/0.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm.3491670147
Short name	T160
Test name
Test status
Simulation time	88157696144 ps
CPU time	711.78 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:58:29 PM PDT 24
Peak memory	272860 kb
Host	smart-2e47cccd-533a-46f5-87a3-df5c39c67ad3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491670147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3491670147
Directory	/workspace/31.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/37.spi_device_stress_all.3266062800
Short name	T151
Test name
Test status
Simulation time	61658620523 ps
CPU time	632.26 seconds
Started	May 23 02:47:32 PM PDT 24
Finished	May 23 02:58:05 PM PDT 24
Peak memory	264468 kb
Host	smart-eafd92bb-b2d0-4831-95a9-86ba1716cd14
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266062800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre ss_all.3266062800
Directory	/workspace/37.spi_device_stress_all/latest

Test location	/workspace/coverage/default/4.spi_device_sec_cm.2476302730
Short name	T28
Test name
Test status
Simulation time	115040557 ps
CPU time	1.19 seconds
Started	May 23 02:41:36 PM PDT 24
Finished	May 23 02:41:38 PM PDT 24
Peak memory	236236 kb
Host	smart-8afb827c-e042-437a-855b-4694af463d26
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476302730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2476302730
Directory	/workspace/4.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/35.spi_device_flash_all.3652241249
Short name	T83
Test name
Test status
Simulation time	14122380129 ps
CPU time	83.28 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:48:13 PM PDT 24
Peak memory	265452 kb
Host	smart-3fc384b4-6a73-4f00-98b3-6589e6b976fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652241249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3652241249
Directory	/workspace/35.spi_device_flash_all/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.132905497
Short name	T98
Test name
Test status
Simulation time	232197319 ps
CPU time	3.36 seconds
Started	May 23 02:02:41 PM PDT 24
Finished	May 23 02:02:45 PM PDT 24
Peak memory	215400 kb
Host	smart-f091e603-f2a8-4ab3-a20f-88ebe3f1fcb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132905497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.132905497
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2894102226
Short name	T29
Test name
Test status
Simulation time	101790538347 ps
CPU time	282.42 seconds
Started	May 23 02:47:16 PM PDT 24
Finished	May 23 02:52:00 PM PDT 24
Peak memory	255328 kb
Host	smart-8f693ba4-7f05-4c21-be1c-af0ef8cf9509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894102226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl e.2894102226
Directory	/workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/21.spi_device_flash_all.77949066
Short name	T159
Test name
Test status
Simulation time	67787365427 ps
CPU time	184.65 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:47:56 PM PDT 24
Peak memory	253200 kb
Host	smart-3be2a564-8fee-41d9-a19e-433222ecaf97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77949066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.77949066
Directory	/workspace/21.spi_device_flash_all/latest

Test location	/workspace/coverage/default/5.spi_device_stress_all.110056776
Short name	T133
Test name
Test status
Simulation time	83004298978 ps
CPU time	275.45 seconds
Started	May 23 02:41:51 PM PDT 24
Finished	May 23 02:46:27 PM PDT 24
Peak memory	265496 kb
Host	smart-fba695c9-8904-467d-bcdd-3c513c34c7cb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110056776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress _all.110056776
Directory	/workspace/5.spi_device_stress_all/latest

Test location	/workspace/coverage/default/22.spi_device_stress_all.339248794
Short name	T139
Test name
Test status
Simulation time	69132640225 ps
CPU time	715.19 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:57:03 PM PDT 24
Peak memory	286372 kb
Host	smart-bd16cc29-9acb-4125-ae99-4cf1acf11f31
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339248794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres s_all.339248794
Directory	/workspace/22.spi_device_stress_all/latest

Test location	/workspace/coverage/default/20.spi_device_stress_all.1843682534
Short name	T152
Test name
Test status
Simulation time	180509653484 ps
CPU time	409.63 seconds
Started	May 23 02:45:01 PM PDT 24
Finished	May 23 02:51:51 PM PDT 24
Peak memory	273568 kb
Host	smart-eb1e6960-6b51-4353-a988-85fb1a249892
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843682534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre ss_all.1843682534
Directory	/workspace/20.spi_device_stress_all/latest

Test location	/workspace/coverage/default/42.spi_device_flash_all.1858406377
Short name	T34
Test name
Test status
Simulation time	57945690409 ps
CPU time	443.63 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:56:07 PM PDT 24
Peak memory	249068 kb
Host	smart-89de9f73-7cf9-4314-8ff7-257bb2418a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858406377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1858406377
Directory	/workspace/42.spi_device_flash_all/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm.364331282
Short name	T209
Test name
Test status
Simulation time	472540311864 ps
CPU time	353.64 seconds
Started	May 23 02:46:04 PM PDT 24
Finished	May 23 02:51:59 PM PDT 24
Peak memory	257220 kb
Host	smart-8c8df234-bc9d-487f-98c3-52a5afff5e14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364331282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.364331282
Directory	/workspace/29.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/2.spi_device_stress_all.1913478095
Short name	T162
Test name
Test status
Simulation time	125326736516 ps
CPU time	398.8 seconds
Started	May 23 02:40:59 PM PDT 24
Finished	May 23 02:47:39 PM PDT 24
Peak memory	273740 kb
Host	smart-44afe563-344b-4d32-9a3f-7fe4abe585a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913478095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres s_all.1913478095
Directory	/workspace/2.spi_device_stress_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.956296400
Short name	T9
Test name
Test status
Simulation time	16301331268 ps
CPU time	23.46 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:45:13 PM PDT 24
Peak memory	216120 kb
Host	smart-48ae9984-d801-4e0c-a5eb-ecee9d5f9b76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956296400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.956296400
Directory	/workspace/22.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/1.spi_device_alert_test.2871164651
Short name	T337
Test name
Test status
Simulation time	34804154 ps
CPU time	0.71 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:34 PM PDT 24
Peak memory	204744 kb
Host	smart-cde5b382-f97c-4368-8398-a3799cf19929
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871164651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2 871164651
Directory	/workspace/1.spi_device_alert_test/latest

Test location	/workspace/coverage/default/33.spi_device_flash_all.2686052324
Short name	T199
Test name
Test status
Simulation time	15148240738 ps
CPU time	76.12 seconds
Started	May 23 02:46:52 PM PDT 24
Finished	May 23 02:48:10 PM PDT 24
Peak memory	257164 kb
Host	smart-a2944136-3a92-4c7e-893a-52b108c699e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686052324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2686052324
Directory	/workspace/33.spi_device_flash_all/latest

Test location	/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2834144354
Short name	T201
Test name
Test status
Simulation time	47850052074 ps
CPU time	293.12 seconds
Started	May 23 02:41:51 PM PDT 24
Finished	May 23 02:46:45 PM PDT 24
Peak memory	271632 kb
Host	smart-11dde215-bc60-44b2-888b-c7f41600b5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834144354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle .2834144354
Directory	/workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1660033937
Short name	T205
Test name
Test status
Simulation time	41766670971 ps
CPU time	425.49 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:49:26 PM PDT 24
Peak memory	262744 kb
Host	smart-8a272763-8fb9-4d11-8fa1-cc3330d41b87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660033937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle .1660033937
Directory	/workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1157519726
Short name	T170
Test name
Test status
Simulation time	1211047354 ps
CPU time	20.44 seconds
Started	May 23 02:04:08 PM PDT 24
Finished	May 23 02:04:30 PM PDT 24
Peak memory	215560 kb
Host	smart-2577031c-902f-4888-adf1-dbcbef66db02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157519726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.1157519726
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/12.spi_device_flash_mode.11323421
Short name	T280
Test name
Test status
Simulation time	1836217884 ps
CPU time	15.59 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:25 PM PDT 24
Peak memory	232596 kb
Host	smart-0af9b2be-4a2c-4025-a0fc-49a15f429b27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11323421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.11323421
Directory	/workspace/12.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm.1264473771
Short name	T54
Test name
Test status
Simulation time	24286101832 ps
CPU time	267.52 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:50:03 PM PDT 24
Peak memory	249108 kb
Host	smart-13f2aba8-8d3a-486f-8967-6a972a6dc841
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264473771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1264473771
Directory	/workspace/25.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/25.spi_device_stress_all.1156569804
Short name	T24
Test name
Test status
Simulation time	42969432961 ps
CPU time	270.27 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:50:08 PM PDT 24
Peak memory	255288 kb
Host	smart-431a99ad-78a4-4584-bb96-17376bc23b61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156569804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre ss_all.1156569804
Directory	/workspace/25.spi_device_stress_all/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1040362496
Short name	T227
Test name
Test status
Simulation time	295689187791 ps
CPU time	417.17 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:54:35 PM PDT 24
Peak memory	265184 kb
Host	smart-870c17ac-d7bc-40a4-9428-88f99412efe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040362496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl e.1040362496
Directory	/workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3535446734
Short name	T95
Test name
Test status
Simulation time	70112974 ps
CPU time	5.16 seconds
Started	May 23 02:03:10 PM PDT 24
Finished	May 23 02:03:16 PM PDT 24
Peak memory	215396 kb
Host	smart-b39e1658-e517-47a9-a1dd-78fcb4dfb605
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535446734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3 535446734
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/24.spi_device_flash_mode.1433712256
Short name	T15
Test name
Test status
Simulation time	106144336 ps
CPU time	5.24 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:28 PM PDT 24
Peak memory	232520 kb
Host	smart-32243713-57fa-4ed0-afeb-8e635b11c376
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433712256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1433712256
Directory	/workspace/24.spi_device_flash_mode/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3276280170
Short name	T166
Test name
Test status
Simulation time	2945599086 ps
CPU time	19.2 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:03:04 PM PDT 24
Peak memory	215804 kb
Host	smart-4ba28669-1bcc-49a7-b8c7-46dd4c0251f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276280170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.3276280170
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/8.spi_device_stress_all.79857528
Short name	T203
Test name
Test status
Simulation time	270863861209 ps
CPU time	572.25 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:52:07 PM PDT 24
Peak memory	255616 kb
Host	smart-9491bae3-b108-40e1-9c87-b5a0be2853ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79857528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_ all.79857528
Directory	/workspace/8.spi_device_stress_all/latest

Test location	/workspace/coverage/default/22.spi_device_cfg_cmd.1420863542
Short name	T93
Test name
Test status
Simulation time	240709466 ps
CPU time	2.9 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:44:53 PM PDT 24
Peak memory	218620 kb
Host	smart-324be07f-12d7-4fa9-bc77-3f3270e4fbf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420863542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1420863542
Directory	/workspace/22.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/0.spi_device_flash_all.1834807725
Short name	T41
Test name
Test status
Simulation time	65017819644 ps
CPU time	247.05 seconds
Started	May 23 02:40:22 PM PDT 24
Finished	May 23 02:44:30 PM PDT 24
Peak memory	252220 kb
Host	smart-6737463b-5768-4836-af66-5e6d5e0a186c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834807725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1834807725
Directory	/workspace/0.spi_device_flash_all/latest

Test location	/workspace/coverage/default/10.spi_device_flash_mode.1296401330
Short name	T286
Test name
Test status
Simulation time	436143702 ps
CPU time	4.5 seconds
Started	May 23 02:42:45 PM PDT 24
Finished	May 23 02:42:50 PM PDT 24
Peak memory	232640 kb
Host	smart-9d53bc5a-b189-41bb-8a75-2b8e8d56d8c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296401330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1296401330
Directory	/workspace/10.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm.755946732
Short name	T40
Test name
Test status
Simulation time	4461306939 ps
CPU time	54.18 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:44:30 PM PDT 24
Peak memory	253368 kb
Host	smart-5e23157e-6eb1-4107-a631-57c2f44a0c92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755946732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.755946732
Directory	/workspace/14.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/16.spi_device_stress_all.3116912938
Short name	T264
Test name
Test status
Simulation time	4994508258 ps
CPU time	122.62 seconds
Started	May 23 02:43:59 PM PDT 24
Finished	May 23 02:46:02 PM PDT 24
Peak memory	255732 kb
Host	smart-19fe674c-08d3-4d37-bb5c-e32f9b139214
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116912938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre ss_all.3116912938
Directory	/workspace/16.spi_device_stress_all/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm.707369129
Short name	T187
Test name
Test status
Simulation time	131122511458 ps
CPU time	315.02 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:49:53 PM PDT 24
Peak memory	249132 kb
Host	smart-43bda632-c4b5-4a0a-b650-120e7adaaa09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707369129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.707369129
Directory	/workspace/20.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1976015350
Short name	T270
Test name
Test status
Simulation time	6646549769 ps
CPU time	9.63 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:46 PM PDT 24
Peak memory	218544 kb
Host	smart-1917eda9-1e71-4da4-a7fb-2332ca9dcb54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976015350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.1976015350
Directory	/workspace/38.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/4.spi_device_flash_all.1717455181
Short name	T233
Test name
Test status
Simulation time	7216092225 ps
CPU time	97.75 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:43:03 PM PDT 24
Peak memory	253584 kb
Host	smart-6a4868dd-c73b-4063-a407-3056a32630e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717455181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1717455181
Directory	/workspace/4.spi_device_flash_all/latest

Test location	/workspace/coverage/default/16.spi_device_pass_cmd_filtering.2571152293
Short name	T13
Test name
Test status
Simulation time	2030856649 ps
CPU time	8.63 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:44:05 PM PDT 24
Peak memory	226744 kb
Host	smart-2d6c4186-7878-44af-840e-0af0618deadc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571152293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2571152293
Directory	/workspace/16.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1973218323
Short name	T104
Test name
Test status
Simulation time	474215104 ps
CPU time	2.94 seconds
Started	May 23 02:02:18 PM PDT 24
Finished	May 23 02:02:22 PM PDT 24
Peak memory	215344 kb
Host	smart-a5e12ea6-b92c-4e00-9f9a-1118870c00c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973218323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1 973218323
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3486125382
Short name	T86
Test name
Test status
Simulation time	36722920 ps
CPU time	1.2 seconds
Started	May 23 02:02:57 PM PDT 24
Finished	May 23 02:02:59 PM PDT 24
Peak memory	206876 kb
Host	smart-ed8af49c-8efb-4784-911b-9938ac123acc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486125382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.3486125382
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1398761925
Short name	T106
Test name
Test status
Simulation time	64707602 ps
CPU time	1.6 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:37 PM PDT 24
Peak memory	215348 kb
Host	smart-ed4e6443-72c0-49da-8614-c9959f576008
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398761925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 1398761925
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1432104601
Short name	T1035
Test name
Test status
Simulation time	1249241784 ps
CPU time	8.36 seconds
Started	May 23 02:02:20 PM PDT 24
Finished	May 23 02:02:29 PM PDT 24
Peak memory	215172 kb
Host	smart-00660999-65f4-4332-8a83-0d08afd73845
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432104601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.1432104601
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.137336102
Short name	T961
Test name
Test status
Simulation time	2544535499 ps
CPU time	14.33 seconds
Started	May 23 02:02:17 PM PDT 24
Finished	May 23 02:02:32 PM PDT 24
Peak memory	215196 kb
Host	smart-7223e53d-c5b4-49d8-91a0-a45567b39d1c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137336102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr _bit_bash.137336102
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1309114720
Short name	T85
Test name
Test status
Simulation time	42082965 ps
CPU time	1.21 seconds
Started	May 23 02:02:20 PM PDT 24
Finished	May 23 02:02:22 PM PDT 24
Peak memory	206944 kb
Host	smart-ad275435-e2dd-449a-b511-62dcc940ae67
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309114720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.1309114720
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.803794896
Short name	T70
Test name
Test status
Simulation time	56086747 ps
CPU time	1.89 seconds
Started	May 23 02:02:31 PM PDT 24
Finished	May 23 02:02:34 PM PDT 24
Peak memory	215200 kb
Host	smart-7209bee3-b77b-4067-92cb-c932301bead3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803794896 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.803794896
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.597343068
Short name	T1030
Test name
Test status
Simulation time	109768211 ps
CPU time	1.98 seconds
Started	May 23 02:02:19 PM PDT 24
Finished	May 23 02:02:22 PM PDT 24
Peak memory	215176 kb
Host	smart-eafa2dd9-3b11-4c98-be84-cd673e7fc21d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597343068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.597343068
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.1373566986
Short name	T996
Test name
Test status
Simulation time	28869386 ps
CPU time	0.69 seconds
Started	May 23 02:02:18 PM PDT 24
Finished	May 23 02:02:19 PM PDT 24
Peak memory	203884 kb
Host	smart-bf473c22-b1f3-445d-b4ff-4cabe624ac6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373566986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1 373566986
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1693163678
Short name	T1064
Test name
Test status
Simulation time	163215237 ps
CPU time	1.86 seconds
Started	May 23 02:02:21 PM PDT 24
Finished	May 23 02:02:24 PM PDT 24
Peak memory	215312 kb
Host	smart-63642baa-85aa-411d-b60e-1a0007552b1a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693163678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.1693163678
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.350956070
Short name	T980
Test name
Test status
Simulation time	26985134 ps
CPU time	0.66 seconds
Started	May 23 02:02:23 PM PDT 24
Finished	May 23 02:02:24 PM PDT 24
Peak memory	203440 kb
Host	smart-e72a4462-7d4f-40e9-a8da-0a6aaee4cee5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350956070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem _walk.350956070
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3116208411
Short name	T1011
Test name
Test status
Simulation time	449887938 ps
CPU time	1.86 seconds
Started	May 23 02:02:30 PM PDT 24
Finished	May 23 02:02:32 PM PDT 24
Peak memory	215244 kb
Host	smart-adb783df-fcdd-4c28-afb8-c40cbabcfb1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116208411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.3116208411
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2660330960
Short name	T1006
Test name
Test status
Simulation time	300102987 ps
CPU time	18.83 seconds
Started	May 23 02:02:19 PM PDT 24
Finished	May 23 02:02:39 PM PDT 24
Peak memory	215172 kb
Host	smart-ddd3bed4-b24b-48ec-b251-3dd488e57b43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660330960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.2660330960
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3003130961
Short name	T123
Test name
Test status
Simulation time	2297899363 ps
CPU time	21.76 seconds
Started	May 23 02:02:45 PM PDT 24
Finished	May 23 02:03:07 PM PDT 24
Peak memory	207004 kb
Host	smart-3f40ccff-5cb3-40d8-9ffe-89905085a73a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003130961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_aliasing.3003130961
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3782996465
Short name	T119
Test name
Test status
Simulation time	794482599 ps
CPU time	13.09 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:02:58 PM PDT 24
Peak memory	206968 kb
Host	smart-cca7cacf-62dc-4cfc-b207-0ad0bbac0918
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782996465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.3782996465
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.556020910
Short name	T122
Test name
Test status
Simulation time	82937228 ps
CPU time	1.06 seconds
Started	May 23 02:02:31 PM PDT 24
Finished	May 23 02:02:32 PM PDT 24
Peak memory	206568 kb
Host	smart-d553a71a-24cf-423c-a514-bdfba4105dcb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556020910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _hw_reset.556020910
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3945712856
Short name	T113
Test name
Test status
Simulation time	25981547 ps
CPU time	1.79 seconds
Started	May 23 02:02:43 PM PDT 24
Finished	May 23 02:02:45 PM PDT 24
Peak memory	215320 kb
Host	smart-40195adc-d1be-4c7a-8ddb-a087c6cbc67c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945712856 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3945712856
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1163636920
Short name	T970
Test name
Test status
Simulation time	35914684 ps
CPU time	2.42 seconds
Started	May 23 02:02:32 PM PDT 24
Finished	May 23 02:02:35 PM PDT 24
Peak memory	207044 kb
Host	smart-9bad6f0c-98e6-4ec2-98f1-1586d44b6c78
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163636920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1 163636920
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.145090529
Short name	T985
Test name
Test status
Simulation time	27340905 ps
CPU time	0.76 seconds
Started	May 23 02:02:35 PM PDT 24
Finished	May 23 02:02:36 PM PDT 24
Peak memory	203552 kb
Host	smart-1d27f3b8-d47c-4ced-87d2-e25969ff5518
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145090529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.145090529
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3302439739
Short name	T1022
Test name
Test status
Simulation time	92816610 ps
CPU time	2.18 seconds
Started	May 23 02:02:30 PM PDT 24
Finished	May 23 02:02:33 PM PDT 24
Peak memory	215284 kb
Host	smart-f23242d8-c6ed-4136-8bc4-e7e9d4571ab9
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302439739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.3302439739
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.97722525
Short name	T1037
Test name
Test status
Simulation time	12761950 ps
CPU time	0.69 seconds
Started	May 23 02:02:36 PM PDT 24
Finished	May 23 02:02:37 PM PDT 24
Peak memory	203476 kb
Host	smart-2e8cad99-62dd-45f0-91b5-347bc40acbbb
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97722525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_ walk.97722525
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3803453933
Short name	T969
Test name
Test status
Simulation time	430283895 ps
CPU time	3.1 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:02:47 PM PDT 24
Peak memory	215208 kb
Host	smart-aae58d62-a002-4f87-aa85-2e25a6ab2629
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803453933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.3803453933
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.564657032
Short name	T1013
Test name
Test status
Simulation time	402093715 ps
CPU time	14.01 seconds
Started	May 23 02:02:31 PM PDT 24
Finished	May 23 02:02:46 PM PDT 24
Peak memory	215216 kb
Host	smart-c353beff-4f71-48c0-972e-e1845db32423
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564657032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_ tl_intg_err.564657032
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2254033389
Short name	T997
Test name
Test status
Simulation time	78193760 ps
CPU time	3.01 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	217432 kb
Host	smart-70b199e3-ca97-4db4-a3a9-9d7a90183d4e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254033389 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2254033389
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.773630661
Short name	T1024
Test name
Test status
Simulation time	663856835 ps
CPU time	2.57 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	215120 kb
Host	smart-03cac1e2-1c1d-47e3-a2f3-a9629d547264
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773630661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.773630661
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1221437299
Short name	T960
Test name
Test status
Simulation time	13673955 ps
CPU time	0.68 seconds
Started	May 23 02:03:21 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	203612 kb
Host	smart-4bc9019f-28ba-41ac-b966-608296216c78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221437299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 1221437299
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2853972962
Short name	T990
Test name
Test status
Simulation time	27515367 ps
CPU time	1.85 seconds
Started	May 23 02:03:39 PM PDT 24
Finished	May 23 02:03:42 PM PDT 24
Peak memory	215232 kb
Host	smart-0202d7f0-c2e5-4e86-a1be-ba2d349e2608
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853972962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.2853972962
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2308138428
Short name	T991
Test name
Test status
Simulation time	40741141 ps
CPU time	2.85 seconds
Started	May 23 02:03:20 PM PDT 24
Finished	May 23 02:03:24 PM PDT 24
Peak memory	215392 kb
Host	smart-91f6c822-8700-4ca8-ab8f-f0398b05707e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308138428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 2308138428
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.255186283
Short name	T171
Test name
Test status
Simulation time	1364673097 ps
CPU time	19.33 seconds
Started	May 23 02:03:21 PM PDT 24
Finished	May 23 02:03:42 PM PDT 24
Peak memory	215392 kb
Host	smart-f495f6c4-c70a-4604-a283-3cc57d9cd985
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255186283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device _tl_intg_err.255186283
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3775672690
Short name	T110
Test name
Test status
Simulation time	310986188 ps
CPU time	4.03 seconds
Started	May 23 02:03:40 PM PDT 24
Finished	May 23 02:03:44 PM PDT 24
Peak memory	217232 kb
Host	smart-bc7493b9-0c89-4923-94fc-bc1e5bc14663
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775672690 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3775672690
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3715319702
Short name	T988
Test name
Test status
Simulation time	151682099 ps
CPU time	1.36 seconds
Started	May 23 02:03:36 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	206904 kb
Host	smart-219fbe23-4612-4fb5-8189-b9c496aae8cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715319702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw. 3715319702
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1300673643
Short name	T958
Test name
Test status
Simulation time	29192017 ps
CPU time	0.79 seconds
Started	May 23 02:03:33 PM PDT 24
Finished	May 23 02:03:34 PM PDT 24
Peak memory	203828 kb
Host	smart-4a0da6b3-bbc5-4d68-93ba-01f6aecb957b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300673643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test. 1300673643
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1175325545
Short name	T1036
Test name
Test status
Simulation time	102689108 ps
CPU time	3.48 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:38 PM PDT 24
Peak memory	215172 kb
Host	smart-c08d88fd-7fdd-44c1-ac6f-7cb15fae79d3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175325545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.1175325545
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.152785569
Short name	T163
Test name
Test status
Simulation time	419157365 ps
CPU time	3.13 seconds
Started	May 23 02:03:33 PM PDT 24
Finished	May 23 02:03:37 PM PDT 24
Peak memory	215232 kb
Host	smart-fbe9ae93-d186-40a7-be7b-1718578bd55c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152785569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.152785569
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1126023438
Short name	T1048
Test name
Test status
Simulation time	2011145152 ps
CPU time	7.14 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:43 PM PDT 24
Peak memory	215236 kb
Host	smart-e641987a-6cb8-4192-a5c4-5521f7f3085b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126023438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.1126023438
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.967779784
Short name	T1019
Test name
Test status
Simulation time	1129508419 ps
CPU time	2.85 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:38 PM PDT 24
Peak memory	217460 kb
Host	smart-08836084-b724-4363-bde6-806acbc0c679
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967779784 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.967779784
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2852691700
Short name	T1038
Test name
Test status
Simulation time	14812126 ps
CPU time	0.75 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:36 PM PDT 24
Peak memory	203380 kb
Host	smart-dcf28f29-360f-47a0-9278-da8c889623da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852691700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 2852691700
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1386102729
Short name	T1060
Test name
Test status
Simulation time	48774315 ps
CPU time	2.75 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	215236 kb
Host	smart-70aac100-6b35-4a16-96ff-a87d52162851
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386102729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.1386102729
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.469395664
Short name	T147
Test name
Test status
Simulation time	2706720663 ps
CPU time	16.22 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:51 PM PDT 24
Peak memory	215396 kb
Host	smart-600c0ba6-2b5b-42f0-9a53-d0c3aed81bd7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469395664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device _tl_intg_err.469395664
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.110369799
Short name	T109
Test name
Test status
Simulation time	54402708 ps
CPU time	1.92 seconds
Started	May 23 02:03:36 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	215336 kb
Host	smart-f6095567-9592-44b4-bfc2-e6358db24775
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110369799 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.110369799
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1959092293
Short name	T1051
Test name
Test status
Simulation time	80529347 ps
CPU time	1.99 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:37 PM PDT 24
Peak memory	206908 kb
Host	smart-ed9722b4-c6b2-45e1-9bd0-ca1ed94f7e84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959092293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 1959092293
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1929860699
Short name	T1081
Test name
Test status
Simulation time	12115655 ps
CPU time	0.71 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:37 PM PDT 24
Peak memory	203572 kb
Host	smart-8daf0b79-a7a3-451a-9b84-b38b3e5593cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929860699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 1929860699
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.878616773
Short name	T982
Test name
Test status
Simulation time	82974035 ps
CPU time	2.93 seconds
Started	May 23 02:03:33 PM PDT 24
Finished	May 23 02:03:37 PM PDT 24
Peak memory	215264 kb
Host	smart-4846114e-e9a9-4c63-bf37-06d1c30d63a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878616773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s pi_device_same_csr_outstanding.878616773
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2269384723
Short name	T108
Test name
Test status
Simulation time	578939758 ps
CPU time	3.19 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:40 PM PDT 24
Peak memory	215388 kb
Host	smart-e9da2e3a-aec5-45dc-87f7-2e1ec77c22e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269384723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 2269384723
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2998513536
Short name	T1029
Test name
Test status
Simulation time	881863627 ps
CPU time	13.5 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:50 PM PDT 24
Peak memory	215080 kb
Host	smart-495927c9-c19a-4a6d-9122-be55ad5d4e76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998513536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.2998513536
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1728351800
Short name	T1069
Test name
Test status
Simulation time	176065872 ps
CPU time	3.09 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	216824 kb
Host	smart-6135d0f9-e69a-4df0-862d-88d0efa2bf33
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728351800 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1728351800
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.420751960
Short name	T121
Test name
Test status
Simulation time	326209456 ps
CPU time	1.44 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:36 PM PDT 24
Peak memory	206948 kb
Host	smart-02628f6e-5b0a-4f72-9476-03a1ec302af8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420751960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.420751960
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2083831256
Short name	T979
Test name
Test status
Simulation time	12759807 ps
CPU time	0.73 seconds
Started	May 23 02:03:34 PM PDT 24
Finished	May 23 02:03:35 PM PDT 24
Peak memory	203648 kb
Host	smart-5ade14d9-df31-4487-9f6f-461f8ba85b0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083831256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 2083831256
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1177211504
Short name	T145
Test name
Test status
Simulation time	78782177 ps
CPU time	2.03 seconds
Started	May 23 02:03:51 PM PDT 24
Finished	May 23 02:03:55 PM PDT 24
Peak memory	215228 kb
Host	smart-cd7f0699-703a-48bc-876b-c6143a7e2bdc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177211504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.1177211504
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1987537194
Short name	T97
Test name
Test status
Simulation time	1212344686 ps
CPU time	1.81 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:39 PM PDT 24
Peak memory	216520 kb
Host	smart-e31dd368-f8d7-4be6-96ed-3a3f2341142b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987537194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors. 1987537194
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2279351436
Short name	T1032
Test name
Test status
Simulation time	350647163 ps
CPU time	8.43 seconds
Started	May 23 02:03:35 PM PDT 24
Finished	May 23 02:03:45 PM PDT 24
Peak memory	215340 kb
Host	smart-3df61ad2-6f1a-44ad-b5b4-e02520238116
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279351436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.2279351436
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4197998892
Short name	T1075
Test name
Test status
Simulation time	40240697 ps
CPU time	3.04 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:53 PM PDT 24
Peak memory	216360 kb
Host	smart-32840856-65d1-4d67-8a3e-ff28a3bee68b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197998892 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4197998892
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3140917924
Short name	T1052
Test name
Test status
Simulation time	207041179 ps
CPU time	2.7 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	215176 kb
Host	smart-7a0782ca-519d-4670-92f2-1fe66a98e45a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140917924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 3140917924
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3267630289
Short name	T1008
Test name
Test status
Simulation time	15910271 ps
CPU time	0.74 seconds
Started	May 23 02:03:51 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	203904 kb
Host	smart-7fd63ec3-fe60-4424-89e4-e2a25fd0ff6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267630289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 3267630289
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2223722543
Short name	T1017
Test name
Test status
Simulation time	377218830 ps
CPU time	1.67 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:51 PM PDT 24
Peak memory	207024 kb
Host	smart-ca762fec-f313-49f4-93ab-8e79b917d60a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223722543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.2223722543
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2558124770
Short name	T1016
Test name
Test status
Simulation time	298812706 ps
CPU time	4.5 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:03:54 PM PDT 24
Peak memory	215516 kb
Host	smart-04d36f00-7e32-4bca-8b5d-d40240172e8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558124770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 2558124770
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2845924665
Short name	T164
Test name
Test status
Simulation time	922951343 ps
CPU time	7.55 seconds
Started	May 23 02:03:51 PM PDT 24
Finished	May 23 02:04:00 PM PDT 24
Peak memory	215512 kb
Host	smart-0a0dc8b4-9162-4731-9672-2d3f65980b5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845924665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.2845924665
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1047684171
Short name	T1054
Test name
Test status
Simulation time	611785051 ps
CPU time	3.83 seconds
Started	May 23 02:03:50 PM PDT 24
Finished	May 23 02:03:55 PM PDT 24
Peak memory	218280 kb
Host	smart-c415d7f7-98fe-4e27-abf4-a9f3885ca3e0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047684171 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1047684171
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3270805868
Short name	T117
Test name
Test status
Simulation time	292331098 ps
CPU time	1.93 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	215152 kb
Host	smart-ab2f2ab0-f060-4371-b77e-94199a2da0a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270805868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 3270805868
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.3306620796
Short name	T1050
Test name
Test status
Simulation time	28213910 ps
CPU time	0.73 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:51 PM PDT 24
Peak memory	203940 kb
Host	smart-1d9a2457-985f-4137-83e5-6561052cbab1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306620796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 3306620796
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2043003670
Short name	T146
Test name
Test status
Simulation time	79760700 ps
CPU time	2.22 seconds
Started	May 23 02:03:50 PM PDT 24
Finished	May 23 02:03:54 PM PDT 24
Peak memory	206948 kb
Host	smart-cd86d70a-b63b-4db1-afee-2763054812c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043003670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.2043003670
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2813404374
Short name	T112
Test name
Test status
Simulation time	46775878 ps
CPU time	1.92 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	216380 kb
Host	smart-cbcf5fcf-3f0e-4bae-92b6-998165f15b0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813404374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 2813404374
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3521374131
Short name	T983
Test name
Test status
Simulation time	93976843 ps
CPU time	1.76 seconds
Started	May 23 02:03:50 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	216272 kb
Host	smart-de658829-c75f-46ac-a51d-de3c6e60061a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521374131 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3521374131
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1242461300
Short name	T1057
Test name
Test status
Simulation time	55778234 ps
CPU time	1.23 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	206924 kb
Host	smart-50fc2065-057a-466f-a03d-4dae40eacc2f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242461300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw. 1242461300
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3396280504
Short name	T1023
Test name
Test status
Simulation time	16055430 ps
CPU time	0.74 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:03:50 PM PDT 24
Peak memory	203908 kb
Host	smart-b86a0377-0305-4da8-ad2e-9915e588934f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396280504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 3396280504
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3818203154
Short name	T1045
Test name
Test status
Simulation time	45800424 ps
CPU time	2.63 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:03:51 PM PDT 24
Peak memory	215216 kb
Host	smart-822f9185-6e93-4328-9efb-61764ac73c28
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818203154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.3818203154
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.60513238
Short name	T1076
Test name
Test status
Simulation time	33168920 ps
CPU time	2.34 seconds
Started	May 23 02:03:49 PM PDT 24
Finished	May 23 02:03:52 PM PDT 24
Peak memory	216408 kb
Host	smart-4a9623a6-025c-46f4-aded-9b1396e3ca05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60513238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.60513238
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1993447885
Short name	T165
Test name
Test status
Simulation time	3440117318 ps
CPU time	24.1 seconds
Started	May 23 02:03:48 PM PDT 24
Finished	May 23 02:04:13 PM PDT 24
Peak memory	215768 kb
Host	smart-33246cde-0c3d-4b8f-8d5e-f39a3d496e34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993447885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.1993447885
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3075934740
Short name	T1026
Test name
Test status
Simulation time	192541352 ps
CPU time	3.71 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:14 PM PDT 24
Peak memory	216584 kb
Host	smart-a283fd76-0769-4392-9e58-deb1139d748e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075934740 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3075934740
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.669547265
Short name	T1007
Test name
Test status
Simulation time	34805824 ps
CPU time	1.8 seconds
Started	May 23 02:04:08 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	207008 kb
Host	smart-a935ad66-5fd7-4d32-a217-2582150dc07f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669547265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.669547265
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2193018730
Short name	T966
Test name
Test status
Simulation time	16747677 ps
CPU time	0.73 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203888 kb
Host	smart-1932ec40-f382-4cac-91a3-9508c02a8560
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193018730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 2193018730
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2165981762
Short name	T959
Test name
Test status
Simulation time	190791895 ps
CPU time	3.06 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	215236 kb
Host	smart-ac427d1b-cd13-4073-8b1f-97301d746de6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165981762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.2165981762
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2860929510
Short name	T1040
Test name
Test status
Simulation time	108344425 ps
CPU time	2.01 seconds
Started	May 23 02:03:51 PM PDT 24
Finished	May 23 02:03:54 PM PDT 24
Peak memory	215432 kb
Host	smart-95f11d40-c4b6-481c-a37d-52c85b9084e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860929510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 2860929510
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4201236167
Short name	T1005
Test name
Test status
Simulation time	112384625 ps
CPU time	2.9 seconds
Started	May 23 02:04:10 PM PDT 24
Finished	May 23 02:04:13 PM PDT 24
Peak memory	217348 kb
Host	smart-c84b117f-28dd-4d70-822f-f1ca106c1760
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201236167 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4201236167
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3142088431
Short name	T1018
Test name
Test status
Simulation time	94395040 ps
CPU time	1.35 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:10 PM PDT 24
Peak memory	206972 kb
Host	smart-68e0ff67-5838-4d87-af91-c1033b280a9e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142088431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 3142088431
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3571794372
Short name	T1070
Test name
Test status
Simulation time	13818063 ps
CPU time	0.73 seconds
Started	May 23 02:04:06 PM PDT 24
Finished	May 23 02:04:08 PM PDT 24
Peak memory	203592 kb
Host	smart-8cfbc55a-1c8c-4709-9b58-23d9fcf6916f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571794372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 3571794372
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2470342747
Short name	T998
Test name
Test status
Simulation time	95582425 ps
CPU time	1.85 seconds
Started	May 23 02:04:08 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	215240 kb
Host	smart-37c4a684-5dc0-4a7e-b266-71c891750e5c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470342747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.2470342747
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2220354085
Short name	T72
Test name
Test status
Simulation time	42654398 ps
CPU time	3 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	216200 kb
Host	smart-de7e4bb7-bfd4-4afc-8f41-a1484b0b0e35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220354085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 2220354085
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.490970333
Short name	T1039
Test name
Test status
Simulation time	488136987 ps
CPU time	13.51 seconds
Started	May 23 02:04:08 PM PDT 24
Finished	May 23 02:04:23 PM PDT 24
Peak memory	215304 kb
Host	smart-b377f79f-6079-4670-b3f9-d1b28291d22a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490970333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device _tl_intg_err.490970333
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1616262116
Short name	T1021
Test name
Test status
Simulation time	1051025635 ps
CPU time	22.46 seconds
Started	May 23 02:02:46 PM PDT 24
Finished	May 23 02:03:09 PM PDT 24
Peak memory	206960 kb
Host	smart-adb08783-865a-489a-9dbc-7e66d3cdf5ad
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616262116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.1616262116
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4269707942
Short name	T124
Test name
Test status
Simulation time	20154266866 ps
CPU time	39.03 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	215168 kb
Host	smart-d9779e4a-7685-4f31-9a7f-d532881f055b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269707942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.4269707942
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3903361869
Short name	T1014
Test name
Test status
Simulation time	51340643 ps
CPU time	0.93 seconds
Started	May 23 02:02:46 PM PDT 24
Finished	May 23 02:02:47 PM PDT 24
Peak memory	206660 kb
Host	smart-4c476074-4ae5-4f9b-b755-5aeb95312ba3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903361869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.3903361869
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2405133215
Short name	T976
Test name
Test status
Simulation time	354766343 ps
CPU time	2.6 seconds
Started	May 23 02:02:45 PM PDT 24
Finished	May 23 02:02:49 PM PDT 24
Peak memory	217024 kb
Host	smart-dbde626a-8e17-49d1-9b5c-522eb160bc71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405133215 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2405133215
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2379509193
Short name	T1001
Test name
Test status
Simulation time	71213820 ps
CPU time	1.99 seconds
Started	May 23 02:02:45 PM PDT 24
Finished	May 23 02:02:48 PM PDT 24
Peak memory	214928 kb
Host	smart-1d3096e5-fc86-4a64-a571-6d187b97eaba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379509193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2 379509193
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3898613541
Short name	T957
Test name
Test status
Simulation time	36297809 ps
CPU time	0.72 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:02:45 PM PDT 24
Peak memory	203520 kb
Host	smart-ef850dd7-097b-4a55-929d-d3f4f87a97eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898613541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3 898613541
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3074217153
Short name	T1028
Test name
Test status
Simulation time	60825779 ps
CPU time	2.45 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:02:48 PM PDT 24
Peak memory	215124 kb
Host	smart-b2fcc012-9f12-49a5-ac9e-d21f70d6ca7a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074217153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.3074217153
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2940477968
Short name	T1025
Test name
Test status
Simulation time	26893751 ps
CPU time	0.69 seconds
Started	May 23 02:02:44 PM PDT 24
Finished	May 23 02:02:46 PM PDT 24
Peak memory	203576 kb
Host	smart-1100a5cc-6e9d-4a7a-a387-abec7e2fba60
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940477968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.2940477968
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.8493284
Short name	T144
Test name
Test status
Simulation time	705220479 ps
CPU time	4.19 seconds
Started	May 23 02:02:46 PM PDT 24
Finished	May 23 02:02:50 PM PDT 24
Peak memory	215268 kb
Host	smart-bf6da65d-1f66-4138-a046-5848abc9200b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8493284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_ device_same_csr_outstanding.8493284
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3942936359
Short name	T1059
Test name
Test status
Simulation time	188781257 ps
CPU time	1.85 seconds
Started	May 23 02:02:43 PM PDT 24
Finished	May 23 02:02:46 PM PDT 24
Peak memory	215436 kb
Host	smart-10f00d88-5148-49b4-a710-44d74d61e6c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942936359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3 942936359
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2006311932
Short name	T167
Test name
Test status
Simulation time	825091352 ps
CPU time	13.45 seconds
Started	May 23 02:02:43 PM PDT 24
Finished	May 23 02:02:57 PM PDT 24
Peak memory	215288 kb
Host	smart-d6e09523-ccc2-4e23-b90d-050e73db4520
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006311932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device _tl_intg_err.2006311932
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3400227762
Short name	T1055
Test name
Test status
Simulation time	61304244 ps
CPU time	0.72 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203820 kb
Host	smart-976b5a90-b98a-440b-82f5-d169d747510b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400227762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test. 3400227762
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1579094432
Short name	T968
Test name
Test status
Simulation time	70966594 ps
CPU time	0.73 seconds
Started	May 23 02:04:06 PM PDT 24
Finished	May 23 02:04:08 PM PDT 24
Peak memory	203868 kb
Host	smart-d756dd47-7a1e-41d3-bed2-ed3c164c3213
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579094432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 1579094432
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2654446700
Short name	T993
Test name
Test status
Simulation time	124356680 ps
CPU time	0.7 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	203616 kb
Host	smart-cc77b111-a046-41bb-bf19-9fff3e22bb43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654446700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 2654446700
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.957624988
Short name	T971
Test name
Test status
Simulation time	11167512 ps
CPU time	0.77 seconds
Started	May 23 02:04:11 PM PDT 24
Finished	May 23 02:04:12 PM PDT 24
Peak memory	203592 kb
Host	smart-76b66670-aca6-48af-aaba-45003aeb92ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957624988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.957624988
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.4117965184
Short name	T962
Test name
Test status
Simulation time	12545746 ps
CPU time	0.73 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203616 kb
Host	smart-5fa5edb1-67c0-40fb-b8ac-3416ac06d5de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117965184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 4117965184
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3623965677
Short name	T1061
Test name
Test status
Simulation time	22746588 ps
CPU time	0.73 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:10 PM PDT 24
Peak memory	203880 kb
Host	smart-716dc847-f9ff-438d-a7a2-0384e920b43f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623965677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test. 3623965677
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.219648056
Short name	T1041
Test name
Test status
Simulation time	92878815 ps
CPU time	0.76 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203876 kb
Host	smart-89748e1c-96d1-49ab-b36d-059cd03ec289
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219648056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.219648056
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.170086171
Short name	T981
Test name
Test status
Simulation time	13508325 ps
CPU time	0.71 seconds
Started	May 23 02:04:08 PM PDT 24
Finished	May 23 02:04:10 PM PDT 24
Peak memory	203576 kb
Host	smart-19a65b2f-5b8a-4674-9233-6f4a5a3b1e0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170086171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.170086171
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.3298396530
Short name	T984
Test name
Test status
Simulation time	37810012 ps
CPU time	0.75 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	203600 kb
Host	smart-ff5bee5e-3606-40a6-a889-4ee7f309764d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298396530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 3298396530
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.352347214
Short name	T986
Test name
Test status
Simulation time	41656010 ps
CPU time	0.75 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203916 kb
Host	smart-2a1b30d2-03ef-41c4-be69-7e409bf75858
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352347214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.352347214
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3579155628
Short name	T126
Test name
Test status
Simulation time	3768726970 ps
CPU time	17.73 seconds
Started	May 23 02:02:57 PM PDT 24
Finished	May 23 02:03:15 PM PDT 24
Peak memory	215212 kb
Host	smart-1ba34afb-cddc-4143-b731-02f563253147
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579155628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.3579155628
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.121444810
Short name	T125
Test name
Test status
Simulation time	6035447416 ps
CPU time	25.67 seconds
Started	May 23 02:02:59 PM PDT 24
Finished	May 23 02:03:25 PM PDT 24
Peak memory	207116 kb
Host	smart-46e1ee93-c597-4b22-99b9-a2db15adc242
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121444810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr _bit_bash.121444810
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3277909746
Short name	T114
Test name
Test status
Simulation time	80192370 ps
CPU time	2.46 seconds
Started	May 23 02:02:59 PM PDT 24
Finished	May 23 02:03:02 PM PDT 24
Peak memory	215388 kb
Host	smart-cc4a574b-45db-48ec-a626-91b992d50913
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277909746 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3277909746
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2139518412
Short name	T115
Test name
Test status
Simulation time	254140164 ps
CPU time	2.31 seconds
Started	May 23 02:02:57 PM PDT 24
Finished	May 23 02:03:00 PM PDT 24
Peak memory	215228 kb
Host	smart-309896de-f811-43ca-a815-c4039e215d28
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139518412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2 139518412
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4139022896
Short name	T975
Test name
Test status
Simulation time	19458289 ps
CPU time	0.76 seconds
Started	May 23 02:02:47 PM PDT 24
Finished	May 23 02:02:48 PM PDT 24
Peak memory	203588 kb
Host	smart-cd56ae1d-ceb1-4a02-8a3a-66c19bf2b31c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139022896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4 139022896
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.903213183
Short name	T118
Test name
Test status
Simulation time	133815480 ps
CPU time	2.59 seconds
Started	May 23 02:02:56 PM PDT 24
Finished	May 23 02:02:59 PM PDT 24
Peak memory	215304 kb
Host	smart-75913c36-a5e2-4d1f-a262-b7f98392929f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903213183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_ device_mem_partial_access.903213183
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.567381256
Short name	T1046
Test name
Test status
Simulation time	12463890 ps
CPU time	0.69 seconds
Started	May 23 02:02:56 PM PDT 24
Finished	May 23 02:02:57 PM PDT 24
Peak memory	203516 kb
Host	smart-985c0696-b451-449b-983c-32db7594d171
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567381256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem _walk.567381256
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3063862658
Short name	T1053
Test name
Test status
Simulation time	27599151 ps
CPU time	1.98 seconds
Started	May 23 02:02:58 PM PDT 24
Finished	May 23 02:03:01 PM PDT 24
Peak memory	215212 kb
Host	smart-56067814-0bdd-4209-a773-265861635896
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063862658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s pi_device_same_csr_outstanding.3063862658
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.281444936
Short name	T1068
Test name
Test status
Simulation time	683688835 ps
CPU time	4.11 seconds
Started	May 23 02:02:46 PM PDT 24
Finished	May 23 02:02:51 PM PDT 24
Peak memory	215344 kb
Host	smart-8a57fee0-c7e6-40c2-b710-1165a72e3300
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281444936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.281444936
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.521627915
Short name	T1063
Test name
Test status
Simulation time	16375049 ps
CPU time	0.76 seconds
Started	May 23 02:04:06 PM PDT 24
Finished	May 23 02:04:08 PM PDT 24
Peak memory	203604 kb
Host	smart-be0e6995-8a3c-4cce-adc2-4dce12d2d089
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521627915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.521627915
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2330242499
Short name	T1010
Test name
Test status
Simulation time	26202398 ps
CPU time	0.73 seconds
Started	May 23 02:04:10 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	203580 kb
Host	smart-0ce8eaa9-7b75-4037-97ed-4d97fdc4f70d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330242499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 2330242499
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.311233943
Short name	T1047
Test name
Test status
Simulation time	40741945 ps
CPU time	0.77 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	203568 kb
Host	smart-617a3024-bf11-40c5-9873-7cc676418e0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311233943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.311233943
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.190008898
Short name	T1027
Test name
Test status
Simulation time	41617234 ps
CPU time	0.72 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:09 PM PDT 24
Peak memory	203492 kb
Host	smart-ba3ac0e5-c226-49c6-96f2-e986483381da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190008898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.190008898
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3198704868
Short name	T978
Test name
Test status
Simulation time	45806547 ps
CPU time	0.7 seconds
Started	May 23 02:04:06 PM PDT 24
Finished	May 23 02:04:08 PM PDT 24
Peak memory	203880 kb
Host	smart-b7f2f01c-265f-4093-84c0-b89542a2967a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198704868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 3198704868
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.2246145708
Short name	T973
Test name
Test status
Simulation time	52593119 ps
CPU time	0.79 seconds
Started	May 23 02:04:09 PM PDT 24
Finished	May 23 02:04:11 PM PDT 24
Peak memory	203592 kb
Host	smart-dab92737-1139-43bc-b5c8-549f4e2cec61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246145708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 2246145708
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3783350492
Short name	T1033
Test name
Test status
Simulation time	38330223 ps
CPU time	0.8 seconds
Started	May 23 02:04:07 PM PDT 24
Finished	May 23 02:04:10 PM PDT 24
Peak memory	203640 kb
Host	smart-44d910c3-6749-438c-9bc2-2df0c163fd2c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783350492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 3783350492
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.3939734407
Short name	T1012
Test name
Test status
Simulation time	24248414 ps
CPU time	0.76 seconds
Started	May 23 02:04:23 PM PDT 24
Finished	May 23 02:04:25 PM PDT 24
Peak memory	203564 kb
Host	smart-f419b16e-01dd-4949-affb-94197486b4a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939734407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 3939734407
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.4251811876
Short name	T977
Test name
Test status
Simulation time	41454565 ps
CPU time	0.74 seconds
Started	May 23 02:04:27 PM PDT 24
Finished	May 23 02:04:29 PM PDT 24
Peak memory	203612 kb
Host	smart-56bd1251-a23a-4e2e-a8d4-5fe29db08ea8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251811876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 4251811876
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.827716114
Short name	T1058
Test name
Test status
Simulation time	15917569 ps
CPU time	0.76 seconds
Started	May 23 02:04:26 PM PDT 24
Finished	May 23 02:04:28 PM PDT 24
Peak memory	203620 kb
Host	smart-e36430b5-b3ef-478f-a38d-dbc99d42632f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827716114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.827716114
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1022511326
Short name	T116
Test name
Test status
Simulation time	112835725 ps
CPU time	8.52 seconds
Started	May 23 02:03:08 PM PDT 24
Finished	May 23 02:03:17 PM PDT 24
Peak memory	206992 kb
Host	smart-5f3fc2ce-8d0f-4678-a817-6ba3010f76b4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022511326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.1022511326
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2436502611
Short name	T1072
Test name
Test status
Simulation time	1223669266 ps
CPU time	23.4 seconds
Started	May 23 02:03:11 PM PDT 24
Finished	May 23 02:03:35 PM PDT 24
Peak memory	206924 kb
Host	smart-486cb7f1-59f0-47aa-ab36-5adc41032291
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436502611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_bit_bash.2436502611
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.700378710
Short name	T84
Test name
Test status
Simulation time	109012271 ps
CPU time	1.01 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:11 PM PDT 24
Peak memory	206768 kb
Host	smart-d57ce567-e7d7-4110-aeb3-af9b1c68edcd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700378710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _hw_reset.700378710
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.840175484
Short name	T1074
Test name
Test status
Simulation time	23937917 ps
CPU time	1.78 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:11 PM PDT 24
Peak memory	216316 kb
Host	smart-03c9464a-e1d3-4897-a073-b3ff90ce3bf2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840175484 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.840175484
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3231565465
Short name	T1009
Test name
Test status
Simulation time	104427011 ps
CPU time	1.97 seconds
Started	May 23 02:03:08 PM PDT 24
Finished	May 23 02:03:11 PM PDT 24
Peak memory	206932 kb
Host	smart-69c7938c-ce8f-44a5-adbd-138523619ca5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231565465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3 231565465
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.872074205
Short name	T999
Test name
Test status
Simulation time	11760107 ps
CPU time	0.72 seconds
Started	May 23 02:02:59 PM PDT 24
Finished	May 23 02:03:01 PM PDT 24
Peak memory	203852 kb
Host	smart-9626dfd8-3b54-480b-9abc-39425a9b8c1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872074205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.872074205
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2031075174
Short name	T1044
Test name
Test status
Simulation time	62522994 ps
CPU time	2.11 seconds
Started	May 23 02:03:11 PM PDT 24
Finished	May 23 02:03:14 PM PDT 24
Peak memory	215244 kb
Host	smart-42b25161-c660-4e14-a77d-feb74b79caad
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031075174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.2031075174
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3022359989
Short name	T989
Test name
Test status
Simulation time	18749564 ps
CPU time	0.67 seconds
Started	May 23 02:03:10 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	203440 kb
Host	smart-c125f8a5-d1fd-4bee-9e1a-f8d415041c45
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022359989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.3022359989
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2885927413
Short name	T1031
Test name
Test status
Simulation time	123039730 ps
CPU time	1.63 seconds
Started	May 23 02:03:11 PM PDT 24
Finished	May 23 02:03:13 PM PDT 24
Peak memory	215152 kb
Host	smart-ba34b698-1f7f-47f3-9f38-5c8b80239a9d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885927413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.2885927413
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3491048003
Short name	T1066
Test name
Test status
Simulation time	478367168 ps
CPU time	3.17 seconds
Started	May 23 02:02:58 PM PDT 24
Finished	May 23 02:03:02 PM PDT 24
Peak memory	216148 kb
Host	smart-ef82c9af-e4d2-43d5-83c5-58395c01382e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491048003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3 491048003
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.492425854
Short name	T1067
Test name
Test status
Simulation time	1395972952 ps
CPU time	21.88 seconds
Started	May 23 02:02:58 PM PDT 24
Finished	May 23 02:03:20 PM PDT 24
Peak memory	215268 kb
Host	smart-8cf6d193-8c1b-4c48-9011-37a1f7205ae1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492425854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_ tl_intg_err.492425854
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1985215880
Short name	T1002
Test name
Test status
Simulation time	18582942 ps
CPU time	0.71 seconds
Started	May 23 02:04:22 PM PDT 24
Finished	May 23 02:04:24 PM PDT 24
Peak memory	203424 kb
Host	smart-3ce221a9-d5f3-44f1-9384-e890ab274c5e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985215880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 1985215880
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1446564937
Short name	T995
Test name
Test status
Simulation time	52963775 ps
CPU time	0.74 seconds
Started	May 23 02:04:24 PM PDT 24
Finished	May 23 02:04:26 PM PDT 24
Peak memory	203596 kb
Host	smart-a3fced62-cc06-4c23-8bb8-30908dfafeca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446564937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 1446564937
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.1880326611
Short name	T1015
Test name
Test status
Simulation time	49943840 ps
CPU time	0.75 seconds
Started	May 23 02:04:21 PM PDT 24
Finished	May 23 02:04:23 PM PDT 24
Peak memory	203616 kb
Host	smart-5c2d9a0d-38a1-40ca-ad80-598c239fbaff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880326611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 1880326611
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.1931914288
Short name	T965
Test name
Test status
Simulation time	14962286 ps
CPU time	0.79 seconds
Started	May 23 02:04:22 PM PDT 24
Finished	May 23 02:04:25 PM PDT 24
Peak memory	203600 kb
Host	smart-793dbfb6-a6da-4179-ac4a-67c17646f072
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931914288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 1931914288
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3995881860
Short name	T987
Test name
Test status
Simulation time	12136604 ps
CPU time	0.78 seconds
Started	May 23 02:04:21 PM PDT 24
Finished	May 23 02:04:23 PM PDT 24
Peak memory	203624 kb
Host	smart-c9ff89d6-36c0-496d-b1e7-2b6bbd05d136
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995881860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 3995881860
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2372152075
Short name	T992
Test name
Test status
Simulation time	25778468 ps
CPU time	0.71 seconds
Started	May 23 02:04:25 PM PDT 24
Finished	May 23 02:04:26 PM PDT 24
Peak memory	203604 kb
Host	smart-df671b5b-584d-45fc-aea1-af7d27108910
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372152075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 2372152075
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3090786502
Short name	T1065
Test name
Test status
Simulation time	135099320 ps
CPU time	0.74 seconds
Started	May 23 02:04:23 PM PDT 24
Finished	May 23 02:04:25 PM PDT 24
Peak memory	203584 kb
Host	smart-44641f3b-fcbb-451c-8f20-e4a80045a2a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090786502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 3090786502
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.964118279
Short name	T967
Test name
Test status
Simulation time	19068565 ps
CPU time	0.7 seconds
Started	May 23 02:04:22 PM PDT 24
Finished	May 23 02:04:24 PM PDT 24
Peak memory	203608 kb
Host	smart-32c6b3e5-461a-4750-b8b4-53d48f3ff45e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964118279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.964118279
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1915559880
Short name	T1071
Test name
Test status
Simulation time	84444924 ps
CPU time	0.71 seconds
Started	May 23 02:04:21 PM PDT 24
Finished	May 23 02:04:22 PM PDT 24
Peak memory	203528 kb
Host	smart-738d9aa8-e738-47c6-850c-9dacf52b3127
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915559880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 1915559880
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3291548999
Short name	T1056
Test name
Test status
Simulation time	56193716 ps
CPU time	0.75 seconds
Started	May 23 02:04:21 PM PDT 24
Finished	May 23 02:04:23 PM PDT 24
Peak memory	203600 kb
Host	smart-1c5c82b2-6061-4afc-99df-013c742a983a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291548999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test. 3291548999
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2678847296
Short name	T149
Test name
Test status
Simulation time	61576041 ps
CPU time	1.76 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	215456 kb
Host	smart-c953d901-6496-4925-a3b5-60fa0213eb41
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678847296 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2678847296
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1432191341
Short name	T1049
Test name
Test status
Simulation time	110229077 ps
CPU time	1.75 seconds
Started	May 23 02:03:10 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	207024 kb
Host	smart-aa3705c7-d987-4f93-ab56-207d1c2335c6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432191341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1 432191341
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1714972848
Short name	T1073
Test name
Test status
Simulation time	14716914 ps
CPU time	0.73 seconds
Started	May 23 02:03:10 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	203800 kb
Host	smart-6d038c77-2fbd-455b-ba80-f5fafe892e82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714972848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1 714972848
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2817609453
Short name	T1020
Test name
Test status
Simulation time	930752243 ps
CPU time	3.31 seconds
Started	May 23 02:03:08 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	215220 kb
Host	smart-b9bc5d60-9e97-4e9f-8308-c8024be271a8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817609453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s pi_device_same_csr_outstanding.2817609453
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2555153531
Short name	T169
Test name
Test status
Simulation time	3319756497 ps
CPU time	21.9 seconds
Started	May 23 02:03:08 PM PDT 24
Finished	May 23 02:03:31 PM PDT 24
Peak memory	215540 kb
Host	smart-cf794dad-9d22-4bb1-aad0-23eab2cf759d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555153531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2555153531
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1650128226
Short name	T974
Test name
Test status
Simulation time	38315674 ps
CPU time	2.62 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:12 PM PDT 24
Peak memory	216104 kb
Host	smart-f9046c04-bc51-4def-a1e0-983bc37bbf87
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650128226 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1650128226
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1140152586
Short name	T1077
Test name
Test status
Simulation time	126697644 ps
CPU time	2.08 seconds
Started	May 23 02:03:08 PM PDT 24
Finished	May 23 02:03:11 PM PDT 24
Peak memory	215200 kb
Host	smart-f32cedec-3dd9-4be0-8e78-ec1f736e38c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140152586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1 140152586
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3832786289
Short name	T963
Test name
Test status
Simulation time	51869937 ps
CPU time	0.76 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:11 PM PDT 24
Peak memory	203572 kb
Host	smart-2212a1fb-a9ac-47f6-9d19-6dfe9378e36d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832786289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3 832786289
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1215509445
Short name	T964
Test name
Test status
Simulation time	386706442 ps
CPU time	3.03 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:13 PM PDT 24
Peak memory	215224 kb
Host	smart-68ef40ab-8784-46b9-a310-0a8251adfc50
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215509445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s pi_device_same_csr_outstanding.1215509445
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.126281790
Short name	T111
Test name
Test status
Simulation time	161158219 ps
CPU time	2.95 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:13 PM PDT 24
Peak memory	215352 kb
Host	smart-5a149734-2fd5-4acd-91aa-5516de2ba593
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126281790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.126281790
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1301745000
Short name	T94
Test name
Test status
Simulation time	566714505 ps
CPU time	12.52 seconds
Started	May 23 02:03:10 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	215232 kb
Host	smart-457cda9d-8794-4ab4-a6ca-84a73606d739
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301745000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.1301745000
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.889893238
Short name	T1000
Test name
Test status
Simulation time	167682495 ps
CPU time	1.92 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:25 PM PDT 24
Peak memory	215424 kb
Host	smart-300e62b9-8666-47ca-b5dd-5d41544a8360
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889893238 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.889893238
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1814136812
Short name	T1003
Test name
Test status
Simulation time	169579294 ps
CPU time	1.5 seconds
Started	May 23 02:03:23 PM PDT 24
Finished	May 23 02:03:25 PM PDT 24
Peak memory	219212 kb
Host	smart-1da3a395-0ee9-4836-9978-4a8aa2dc0b25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814136812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1 814136812
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.431159457
Short name	T972
Test name
Test status
Simulation time	27755837 ps
CPU time	0.74 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	203584 kb
Host	smart-67bd1b6a-2a3c-4315-bcce-ce0ef68e0ac7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431159457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.431159457
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3156168498
Short name	T1004
Test name
Test status
Simulation time	97976167 ps
CPU time	1.95 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:24 PM PDT 24
Peak memory	215200 kb
Host	smart-3c5a1925-bab1-475d-8252-d1cbeea5d1ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156168498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.3156168498
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3976581667
Short name	T103
Test name
Test status
Simulation time	136119755 ps
CPU time	2.56 seconds
Started	May 23 02:03:11 PM PDT 24
Finished	May 23 02:03:14 PM PDT 24
Peak memory	215468 kb
Host	smart-d2705a0b-e16c-46c8-9200-51ff0e2dc5f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976581667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3 976581667
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1466211977
Short name	T168
Test name
Test status
Simulation time	540697874 ps
CPU time	15.35 seconds
Started	May 23 02:03:09 PM PDT 24
Finished	May 23 02:03:25 PM PDT 24
Peak memory	215148 kb
Host	smart-8025e96b-1339-4232-ba78-7eb0aac157fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466211977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.1466211977
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3520295305
Short name	T1034
Test name
Test status
Simulation time	43448661 ps
CPU time	3.23 seconds
Started	May 23 02:03:20 PM PDT 24
Finished	May 23 02:03:24 PM PDT 24
Peak memory	217876 kb
Host	smart-9d6a79ca-fc7f-427a-9ac1-c46193cfbc7b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520295305 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3520295305
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3656262544
Short name	T148
Test name
Test status
Simulation time	84084409 ps
CPU time	1.44 seconds
Started	May 23 02:03:21 PM PDT 24
Finished	May 23 02:03:24 PM PDT 24
Peak memory	214956 kb
Host	smart-1383a670-788a-43d4-97b3-6906f11b0322
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656262544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3 656262544
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.332038683
Short name	T1079
Test name
Test status
Simulation time	33303136 ps
CPU time	0.71 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	203604 kb
Host	smart-9bfdac9b-3bd6-42ce-9740-eb9bccf2c69d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332038683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.332038683
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.673062567
Short name	T1080
Test name
Test status
Simulation time	44296997 ps
CPU time	2.99 seconds
Started	May 23 02:03:23 PM PDT 24
Finished	May 23 02:03:27 PM PDT 24
Peak memory	215176 kb
Host	smart-9de327e6-00c0-410d-9d50-97375e204ad8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673062567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp i_device_same_csr_outstanding.673062567
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3095860634
Short name	T107
Test name
Test status
Simulation time	175687079 ps
CPU time	5.49 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:28 PM PDT 24
Peak memory	215456 kb
Host	smart-66b41b00-72af-4fbe-9341-0201d1679ad2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095860634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3 095860634
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4152024018
Short name	T1062
Test name
Test status
Simulation time	529622646 ps
CPU time	13.18 seconds
Started	May 23 02:03:21 PM PDT 24
Finished	May 23 02:03:34 PM PDT 24
Peak memory	215208 kb
Host	smart-809bfaf4-b76c-41c8-9ecd-0084f884a860
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152024018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.4152024018
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1144025901
Short name	T1043
Test name
Test status
Simulation time	229447490 ps
CPU time	1.97 seconds
Started	May 23 02:03:20 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	215252 kb
Host	smart-6b1761db-f456-4ff8-8e23-441ba93ac902
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144025901 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1144025901
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.851954991
Short name	T1042
Test name
Test status
Simulation time	782212984 ps
CPU time	3.01 seconds
Started	May 23 02:03:24 PM PDT 24
Finished	May 23 02:03:27 PM PDT 24
Peak memory	215200 kb
Host	smart-89349a1d-742f-43dd-9216-5d5da15bb1ca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851954991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.851954991
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.2033405795
Short name	T994
Test name
Test status
Simulation time	17051745 ps
CPU time	0.78 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:23 PM PDT 24
Peak memory	203512 kb
Host	smart-65c55206-b882-4027-af41-8de4b1d36e78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033405795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2 033405795
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1597253502
Short name	T1078
Test name
Test status
Simulation time	220200641 ps
CPU time	2.04 seconds
Started	May 23 02:03:21 PM PDT 24
Finished	May 23 02:03:24 PM PDT 24
Peak memory	215488 kb
Host	smart-c0d905a0-49a0-49ab-8d4e-aae5f7220cbb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597253502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.1597253502
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2625777619
Short name	T105
Test name
Test status
Simulation time	485488611 ps
CPU time	3.38 seconds
Started	May 23 02:03:24 PM PDT 24
Finished	May 23 02:03:28 PM PDT 24
Peak memory	215424 kb
Host	smart-b793d91a-7587-4623-809f-f00e1cd94086
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625777619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2 625777619
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2802981280
Short name	T71
Test name
Test status
Simulation time	1213935207 ps
CPU time	21.46 seconds
Started	May 23 02:03:22 PM PDT 24
Finished	May 23 02:03:44 PM PDT 24
Peak memory	215080 kb
Host	smart-7b690c72-c977-4a55-b7e3-6b9a6e87a57a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802981280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.2802981280
Directory	/workspace/9.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/0.spi_device_alert_test.783462462
Short name	T445
Test name
Test status
Simulation time	41943727 ps
CPU time	0.74 seconds
Started	May 23 02:40:19 PM PDT 24
Finished	May 23 02:40:20 PM PDT 24
Peak memory	204772 kb
Host	smart-6eea9568-0975-405c-ad94-08d9b67f4ab9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783462462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.783462462
Directory	/workspace/0.spi_device_alert_test/latest

Test location	/workspace/coverage/default/0.spi_device_cfg_cmd.919445224
Short name	T522
Test name
Test status
Simulation time	4330568492 ps
CPU time	11.44 seconds
Started	May 23 02:40:04 PM PDT 24
Finished	May 23 02:40:17 PM PDT 24
Peak memory	232660 kb
Host	smart-5106542c-0d94-4949-8ba3-ac303e85b46a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919445224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.919445224
Directory	/workspace/0.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/0.spi_device_csb_read.3303877694
Short name	T333
Test name
Test status
Simulation time	22050634 ps
CPU time	0.73 seconds
Started	May 23 02:39:49 PM PDT 24
Finished	May 23 02:39:50 PM PDT 24
Peak memory	205456 kb
Host	smart-4ac21083-a23c-447e-bdcd-0b206289e916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303877694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3303877694
Directory	/workspace/0.spi_device_csb_read/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm.3279285043
Short name	T221
Test name
Test status
Simulation time	135649224063 ps
CPU time	553.71 seconds
Started	May 23 02:40:20 PM PDT 24
Finished	May 23 02:49:34 PM PDT 24
Peak memory	260756 kb
Host	smart-aec9118c-2ab2-458b-bbac-e5323b45f890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279285043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3279285043
Directory	/workspace/0.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1180578762
Short name	T194
Test name
Test status
Simulation time	81053092580 ps
CPU time	592.7 seconds
Started	May 23 02:40:19 PM PDT 24
Finished	May 23 02:50:13 PM PDT 24
Peak memory	257288 kb
Host	smart-a70be074-8fdf-4041-b454-c234ef5dfc1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180578762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle .1180578762
Directory	/workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/0.spi_device_flash_mode.785888427
Short name	T845
Test name
Test status
Simulation time	12438752267 ps
CPU time	17.85 seconds
Started	May 23 02:40:21 PM PDT 24
Finished	May 23 02:40:40 PM PDT 24
Peak memory	224388 kb
Host	smart-9787c5c0-0911-47fc-bfb7-0d21c4f597c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785888427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.785888427
Directory	/workspace/0.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/0.spi_device_intercept.2968952724
Short name	T554
Test name
Test status
Simulation time	10651939601 ps
CPU time	10.45 seconds
Started	May 23 02:40:03 PM PDT 24
Finished	May 23 02:40:14 PM PDT 24
Peak memory	233668 kb
Host	smart-8c7ad4d8-307b-4463-813a-cc3f52711ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968952724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2968952724
Directory	/workspace/0.spi_device_intercept/latest

Test location	/workspace/coverage/default/0.spi_device_mailbox.1707042718
Short name	T257
Test name
Test status
Simulation time	171805895111 ps
CPU time	116.54 seconds
Started	May 23 02:40:04 PM PDT 24
Finished	May 23 02:42:02 PM PDT 24
Peak memory	239988 kb
Host	smart-30c9f9e8-c349-4177-b21b-5fc4b6ee2fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707042718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1707042718
Directory	/workspace/0.spi_device_mailbox/latest

Test location	/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1146902603
Short name	T948
Test name
Test status
Simulation time	98688020 ps
CPU time	2.41 seconds
Started	May 23 02:40:03 PM PDT 24
Finished	May 23 02:40:06 PM PDT 24
Peak memory	218460 kb
Host	smart-0a679b45-ae33-4645-8995-f1d722b61a13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146902603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .1146902603
Directory	/workspace/0.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/0.spi_device_pass_cmd_filtering.2401753652
Short name	T502
Test name
Test status
Simulation time	523633438 ps
CPU time	3.74 seconds
Started	May 23 02:40:05 PM PDT 24
Finished	May 23 02:40:10 PM PDT 24
Peak memory	216824 kb
Host	smart-3d17529c-0838-408e-b7f5-b7950c9d108e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401753652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2401753652
Directory	/workspace/0.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/0.spi_device_read_buffer_direct.3034842123
Short name	T598
Test name
Test status
Simulation time	7548861835 ps
CPU time	6.94 seconds
Started	May 23 02:40:19 PM PDT 24
Finished	May 23 02:40:26 PM PDT 24
Peak memory	219680 kb
Host	smart-2cf214ae-78be-4a3d-8a22-2bb7ecc3e416
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3034842123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire ct.3034842123
Directory	/workspace/0.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/0.spi_device_sec_cm.23303725
Short name	T76
Test name
Test status
Simulation time	107884959 ps
CPU time	1.02 seconds
Started	May 23 02:40:21 PM PDT 24
Finished	May 23 02:40:23 PM PDT 24
Peak memory	234584 kb
Host	smart-834b3d0e-f6ad-47cc-b641-4fae312c8787
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.23303725
Directory	/workspace/0.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/0.spi_device_stress_all.3814139720
Short name	T81
Test name
Test status
Simulation time	53243012031 ps
CPU time	129.1 seconds
Started	May 23 02:40:21 PM PDT 24
Finished	May 23 02:42:31 PM PDT 24
Peak memory	265516 kb
Host	smart-5521e3a4-510f-46ca-96ff-c54def60fb61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814139720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres s_all.3814139720
Directory	/workspace/0.spi_device_stress_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_all.1210019287
Short name	T289
Test name
Test status
Simulation time	4258367961 ps
CPU time	22.08 seconds
Started	May 23 02:39:52 PM PDT 24
Finished	May 23 02:40:15 PM PDT 24
Peak memory	216272 kb
Host	smart-67c25ce4-30c1-442b-ac6a-0af77f58ae75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210019287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1210019287
Directory	/workspace/0.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.54667590
Short name	T297
Test name
Test status
Simulation time	19731091 ps
CPU time	0.69 seconds
Started	May 23 02:39:52 PM PDT 24
Finished	May 23 02:39:54 PM PDT 24
Peak memory	205600 kb
Host	smart-c070b05a-134c-49bd-b4c3-c41fe605bba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54667590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.54667590
Directory	/workspace/0.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_rw.2847362897
Short name	T855
Test name
Test status
Simulation time	16866135 ps
CPU time	0.85 seconds
Started	May 23 02:40:03 PM PDT 24
Finished	May 23 02:40:05 PM PDT 24
Peak memory	206420 kb
Host	smart-fd61ddcf-fef9-43f9-8358-1f7c9c33a20c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847362897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2847362897
Directory	/workspace/0.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_sts_read.1193298520
Short name	T517
Test name
Test status
Simulation time	67285464 ps
CPU time	0.94 seconds
Started	May 23 02:40:02 PM PDT 24
Finished	May 23 02:40:03 PM PDT 24
Peak memory	205696 kb
Host	smart-086c341c-d823-4e35-b158-96bc92c8062d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193298520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1193298520
Directory	/workspace/0.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/0.spi_device_upload.1345335704
Short name	T255
Test name
Test status
Simulation time	14496972573 ps
CPU time	9.3 seconds
Started	May 23 02:40:04 PM PDT 24
Finished	May 23 02:40:14 PM PDT 24
Peak memory	227796 kb
Host	smart-04fdfe46-78ca-4872-9166-896b56daf2f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345335704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1345335704
Directory	/workspace/0.spi_device_upload/latest

Test location	/workspace/coverage/default/1.spi_device_cfg_cmd.3770816304
Short name	T872
Test name
Test status
Simulation time	209930301 ps
CPU time	4.42 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:38 PM PDT 24
Peak memory	234252 kb
Host	smart-e7c35e11-f833-4483-ac9e-5a7efc9c0968
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770816304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3770816304
Directory	/workspace/1.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/1.spi_device_csb_read.2658255532
Short name	T529
Test name
Test status
Simulation time	62160837 ps
CPU time	0.78 seconds
Started	May 23 02:40:20 PM PDT 24
Finished	May 23 02:40:22 PM PDT 24
Peak memory	206768 kb
Host	smart-caeebb0e-e621-4d38-9946-ab90ae7f026d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658255532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2658255532
Directory	/workspace/1.spi_device_csb_read/latest

Test location	/workspace/coverage/default/1.spi_device_flash_all.4288796501
Short name	T383
Test name
Test status
Simulation time	148124845978 ps
CPU time	277.42 seconds
Started	May 23 02:40:33 PM PDT 24
Finished	May 23 02:45:11 PM PDT 24
Peak memory	265472 kb
Host	smart-7b2cece1-dcc1-4e75-a8fe-941f27d1b750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288796501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4288796501
Directory	/workspace/1.spi_device_flash_all/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm.3107018844
Short name	T536
Test name
Test status
Simulation time	6007211336 ps
CPU time	107.88 seconds
Started	May 23 02:40:34 PM PDT 24
Finished	May 23 02:42:23 PM PDT 24
Peak memory	249232 kb
Host	smart-380a21ca-7686-44ff-bf96-ec89df3b52cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107018844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3107018844
Directory	/workspace/1.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1822456982
Short name	T907
Test name
Test status
Simulation time	11498204896 ps
CPU time	25.13 seconds
Started	May 23 02:40:33 PM PDT 24
Finished	May 23 02:40:59 PM PDT 24
Peak memory	238192 kb
Host	smart-cc678083-e577-4425-9ab6-e3ad5e88c449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822456982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle .1822456982
Directory	/workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/1.spi_device_flash_mode.686882593
Short name	T829
Test name
Test status
Simulation time	1331092014 ps
CPU time	21.67 seconds
Started	May 23 02:40:30 PM PDT 24
Finished	May 23 02:40:53 PM PDT 24
Peak memory	233660 kb
Host	smart-c9661a6c-23ba-40f1-8d25-d1a835455bb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686882593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.686882593
Directory	/workspace/1.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/1.spi_device_intercept.726710433
Short name	T781
Test name
Test status
Simulation time	266745490 ps
CPU time	4.77 seconds
Started	May 23 02:40:31 PM PDT 24
Finished	May 23 02:40:37 PM PDT 24
Peak memory	218500 kb
Host	smart-904ab240-fdce-43c3-bf66-73fc42556981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726710433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.726710433
Directory	/workspace/1.spi_device_intercept/latest

Test location	/workspace/coverage/default/1.spi_device_mailbox.3575376272
Short name	T841
Test name
Test status
Simulation time	26613875589 ps
CPU time	131.14 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:42:44 PM PDT 24
Peak memory	236124 kb
Host	smart-d91d38be-3baa-4986-a2d9-a47bd2001251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3575376272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3575376272
Directory	/workspace/1.spi_device_mailbox/latest

Test location	/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2578435826
Short name	T556
Test name
Test status
Simulation time	2034851565 ps
CPU time	7.7 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:41 PM PDT 24
Peak memory	224420 kb
Host	smart-68ec7f0c-97e9-402c-9f7c-444accc0a239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578435826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap .2578435826
Directory	/workspace/1.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/1.spi_device_pass_cmd_filtering.563199431
Short name	T789
Test name
Test status
Simulation time	105563129 ps
CPU time	2.29 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:35 PM PDT 24
Peak memory	216040 kb
Host	smart-0edee748-6f1a-4b80-8608-aa45050e7f76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563199431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.563199431
Directory	/workspace/1.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/1.spi_device_read_buffer_direct.653604313
Short name	T593
Test name
Test status
Simulation time	3510399776 ps
CPU time	9.94 seconds
Started	May 23 02:40:31 PM PDT 24
Finished	May 23 02:40:42 PM PDT 24
Peak memory	222916 kb
Host	smart-8134725b-3c73-432e-9c70-e08bf8d91df7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=653604313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc t.653604313
Directory	/workspace/1.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/1.spi_device_sec_cm.379572218
Short name	T77
Test name
Test status
Simulation time	428030594 ps
CPU time	1.18 seconds
Started	May 23 02:40:33 PM PDT 24
Finished	May 23 02:40:35 PM PDT 24
Peak memory	236296 kb
Host	smart-7ed41684-b6a6-4f08-b154-8584f19973c1
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379572218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.379572218
Directory	/workspace/1.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_all.3579410251
Short name	T57
Test name
Test status
Simulation time	5948312942 ps
CPU time	34.3 seconds
Started	May 23 02:40:20 PM PDT 24
Finished	May 23 02:40:55 PM PDT 24
Peak memory	216236 kb
Host	smart-e7b51bee-f5d9-4829-b622-e3b80c5a23bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579410251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3579410251
Directory	/workspace/1.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2362271959
Short name	T426
Test name
Test status
Simulation time	2884814066 ps
CPU time	12.05 seconds
Started	May 23 02:40:20 PM PDT 24
Finished	May 23 02:40:33 PM PDT 24
Peak memory	216164 kb
Host	smart-ca8ce404-be1f-46e7-9ab8-0ce2cdfd2b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362271959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2362271959
Directory	/workspace/1.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_rw.1960730799
Short name	T768
Test name
Test status
Simulation time	125073275 ps
CPU time	2.48 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:35 PM PDT 24
Peak memory	216248 kb
Host	smart-79e41cb2-a41b-4a5f-8032-6d313100e99e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960730799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1960730799
Directory	/workspace/1.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_sts_read.2793153074
Short name	T465
Test name
Test status
Simulation time	215229134 ps
CPU time	0.86 seconds
Started	May 23 02:40:32 PM PDT 24
Finished	May 23 02:40:34 PM PDT 24
Peak memory	205712 kb
Host	smart-9dd1360a-b0d6-4418-a5ea-7751bae7ff54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793153074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2793153074
Directory	/workspace/1.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/1.spi_device_upload.1492030644
Short name	T581
Test name
Test status
Simulation time	277735190 ps
CPU time	3.87 seconds
Started	May 23 02:40:33 PM PDT 24
Finished	May 23 02:40:38 PM PDT 24
Peak memory	233348 kb
Host	smart-e2f16e94-a764-4951-9a0b-241bfd76ae6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492030644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1492030644
Directory	/workspace/1.spi_device_upload/latest

Test location	/workspace/coverage/default/10.spi_device_alert_test.1701787468
Short name	T842
Test name
Test status
Simulation time	60374789 ps
CPU time	0.74 seconds
Started	May 23 02:42:47 PM PDT 24
Finished	May 23 02:42:49 PM PDT 24
Peak memory	205312 kb
Host	smart-13d39808-9f4d-4410-8753-9ee08e815071
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701787468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test. 1701787468
Directory	/workspace/10.spi_device_alert_test/latest

Test location	/workspace/coverage/default/10.spi_device_cfg_cmd.1447743386
Short name	T388
Test name
Test status
Simulation time	203906162 ps
CPU time	2.52 seconds
Started	May 23 02:42:44 PM PDT 24
Finished	May 23 02:42:47 PM PDT 24
Peak memory	234160 kb
Host	smart-9addad86-028a-4be3-a3d8-6a34456108fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447743386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1447743386
Directory	/workspace/10.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/10.spi_device_csb_read.1149474053
Short name	T495
Test name
Test status
Simulation time	130560146 ps
CPU time	0.73 seconds
Started	May 23 02:42:37 PM PDT 24
Finished	May 23 02:42:38 PM PDT 24
Peak memory	206788 kb
Host	smart-dc5be191-ffbc-4359-8023-4e69e6f9e8d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149474053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1149474053
Directory	/workspace/10.spi_device_csb_read/latest

Test location	/workspace/coverage/default/10.spi_device_flash_all.1426777320
Short name	T771
Test name
Test status
Simulation time	87295155832 ps
CPU time	309.59 seconds
Started	May 23 02:42:47 PM PDT 24
Finished	May 23 02:47:57 PM PDT 24
Peak memory	248996 kb
Host	smart-d543af0b-e882-4b1c-b9b9-81fc91f16127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426777320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1426777320
Directory	/workspace/10.spi_device_flash_all/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm.3304377722
Short name	T158
Test name
Test status
Simulation time	4002942179 ps
CPU time	24.84 seconds
Started	May 23 02:42:43 PM PDT 24
Finished	May 23 02:43:09 PM PDT 24
Peak memory	235720 kb
Host	smart-8c9e9134-a5ab-49f1-958c-dac1dbab5439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304377722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3304377722
Directory	/workspace/10.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1549153791
Short name	T629
Test name
Test status
Simulation time	29743912840 ps
CPU time	79.15 seconds
Started	May 23 02:42:46 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	249248 kb
Host	smart-8ead854b-7f32-4f64-b653-168f03c8fcea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549153791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl e.1549153791
Directory	/workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/10.spi_device_intercept.404132005
Short name	T435
Test name
Test status
Simulation time	616107236 ps
CPU time	3.99 seconds
Started	May 23 02:42:47 PM PDT 24
Finished	May 23 02:42:52 PM PDT 24
Peak memory	218680 kb
Host	smart-af2e1f84-8380-477f-b5aa-c32f647262b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404132005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.404132005
Directory	/workspace/10.spi_device_intercept/latest

Test location	/workspace/coverage/default/10.spi_device_mailbox.2476351593
Short name	T242
Test name
Test status
Simulation time	1851363039 ps
CPU time	9.44 seconds
Started	May 23 02:42:44 PM PDT 24
Finished	May 23 02:42:54 PM PDT 24
Peak memory	221448 kb
Host	smart-691e4da1-201f-4cfd-8252-cc4ef21d8ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476351593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2476351593
Directory	/workspace/10.spi_device_mailbox/latest

Test location	/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.331431098
Short name	T675
Test name
Test status
Simulation time	3270132696 ps
CPU time	7.03 seconds
Started	May 23 02:42:46 PM PDT 24
Finished	May 23 02:42:53 PM PDT 24
Peak memory	233264 kb
Host	smart-cbc56fec-4ea6-4a75-a0c8-4861cb83c229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331431098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap .331431098
Directory	/workspace/10.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/10.spi_device_pass_cmd_filtering.950782288
Short name	T439
Test name
Test status
Simulation time	673244230 ps
CPU time	10.54 seconds
Started	May 23 02:42:46 PM PDT 24
Finished	May 23 02:42:57 PM PDT 24
Peak memory	233628 kb
Host	smart-c5b66c76-fd35-4ff3-9016-8c560b64ad69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950782288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.950782288
Directory	/workspace/10.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/10.spi_device_read_buffer_direct.2759174813
Short name	T501
Test name
Test status
Simulation time	283804122 ps
CPU time	4.43 seconds
Started	May 23 02:42:43 PM PDT 24
Finished	May 23 02:42:49 PM PDT 24
Peak memory	222848 kb
Host	smart-7c54ae07-5536-4aa2-9a38-bba251804623
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2759174813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir ect.2759174813
Directory	/workspace/10.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_all.2455757011
Short name	T672
Test name
Test status
Simulation time	3664012629 ps
CPU time	21.51 seconds
Started	May 23 02:42:44 PM PDT 24
Finished	May 23 02:43:07 PM PDT 24
Peak memory	216224 kb
Host	smart-99c2526b-cf85-4c30-b715-06b5094cbd86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455757011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2455757011
Directory	/workspace/10.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1277085851
Short name	T545
Test name
Test status
Simulation time	9785403996 ps
CPU time	7.48 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:42:41 PM PDT 24
Peak memory	216120 kb
Host	smart-fbfa3f90-b04d-4fdc-a5db-41febf610b95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277085851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1277085851
Directory	/workspace/10.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_rw.663582959
Short name	T309
Test name
Test status
Simulation time	173316961 ps
CPU time	0.84 seconds
Started	May 23 02:42:43 PM PDT 24
Finished	May 23 02:42:44 PM PDT 24
Peak memory	205752 kb
Host	smart-279c8d84-fab9-4174-af7f-8ca52f5efe4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663582959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.663582959
Directory	/workspace/10.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_sts_read.3143288217
Short name	T415
Test name
Test status
Simulation time	144157777 ps
CPU time	0.95 seconds
Started	May 23 02:42:45 PM PDT 24
Finished	May 23 02:42:47 PM PDT 24
Peak memory	205668 kb
Host	smart-c658ce57-83f2-4061-9263-4b3ed9e7c07a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143288217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3143288217
Directory	/workspace/10.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/10.spi_device_upload.2820768588
Short name	T524
Test name
Test status
Simulation time	524632483 ps
CPU time	4.79 seconds
Started	May 23 02:42:44 PM PDT 24
Finished	May 23 02:42:49 PM PDT 24
Peak memory	234264 kb
Host	smart-fef20d98-7bbe-482e-bee3-a6c322efd84a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820768588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2820768588
Directory	/workspace/10.spi_device_upload/latest

Test location	/workspace/coverage/default/11.spi_device_alert_test.2340179199
Short name	T895
Test name
Test status
Simulation time	46469302 ps
CPU time	0.77 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	205336 kb
Host	smart-492e98ca-92b8-471b-8472-113e7a2d177d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340179199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test. 2340179199
Directory	/workspace/11.spi_device_alert_test/latest

Test location	/workspace/coverage/default/11.spi_device_cfg_cmd.2212673550
Short name	T945
Test name
Test status
Simulation time	53537294 ps
CPU time	2.13 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	218652 kb
Host	smart-0f21f97d-3b0b-4b37-9578-e33575eaace9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212673550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2212673550
Directory	/workspace/11.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/11.spi_device_csb_read.3911099773
Short name	T564
Test name
Test status
Simulation time	17434830 ps
CPU time	0.75 seconds
Started	May 23 02:42:46 PM PDT 24
Finished	May 23 02:42:48 PM PDT 24
Peak memory	206820 kb
Host	smart-c5b60e03-dc8f-4019-9d26-b658d5415cc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911099773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3911099773
Directory	/workspace/11.spi_device_csb_read/latest

Test location	/workspace/coverage/default/11.spi_device_flash_all.3156962999
Short name	T709
Test name
Test status
Simulation time	2513089895 ps
CPU time	51.06 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:43:51 PM PDT 24
Peak memory	254868 kb
Host	smart-5e066f1e-6bff-491d-8fcb-78e432a543e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156962999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3156962999
Directory	/workspace/11.spi_device_flash_all/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm.96090578
Short name	T55
Test name
Test status
Simulation time	108267819930 ps
CPU time	467.27 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:50:47 PM PDT 24
Peak memory	256048 kb
Host	smart-12e903e3-880a-4bf2-be3e-b0870a83e850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96090578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.96090578
Directory	/workspace/11.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3153184212
Short name	T551
Test name
Test status
Simulation time	4524948346 ps
CPU time	30.96 seconds
Started	May 23 02:42:57 PM PDT 24
Finished	May 23 02:43:29 PM PDT 24
Peak memory	240604 kb
Host	smart-1c047611-9104-4760-982c-1e0fd5c34d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153184212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl e.3153184212
Directory	/workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/11.spi_device_flash_mode.1754833501
Short name	T334
Test name
Test status
Simulation time	46740632 ps
CPU time	2.63 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	232548 kb
Host	smart-11fd4fec-c99f-4be1-98e2-1a9cd4fcb645
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754833501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1754833501
Directory	/workspace/11.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/11.spi_device_intercept.691336860
Short name	T955
Test name
Test status
Simulation time	851749332 ps
CPU time	5.87 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:43:05 PM PDT 24
Peak memory	219836 kb
Host	smart-5692b8e0-60f0-4cf4-bdb6-44d88405adbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691336860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.691336860
Directory	/workspace/11.spi_device_intercept/latest

Test location	/workspace/coverage/default/11.spi_device_mailbox.2490065793
Short name	T572
Test name
Test status
Simulation time	155882681 ps
CPU time	3.43 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:43:03 PM PDT 24
Peak memory	234412 kb
Host	smart-287037f9-112d-47b1-9e26-c9c9acba729d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490065793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2490065793
Directory	/workspace/11.spi_device_mailbox/latest

Test location	/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.584396539
Short name	T612
Test name
Test status
Simulation time	132441151 ps
CPU time	2.75 seconds
Started	May 23 02:43:00 PM PDT 24
Finished	May 23 02:43:04 PM PDT 24
Peak memory	221280 kb
Host	smart-a90f1c4c-df82-4a92-bdb7-10ad9ed03d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584396539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap .584396539
Directory	/workspace/11.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/11.spi_device_pass_cmd_filtering.147128112
Short name	T854
Test name
Test status
Simulation time	772834083 ps
CPU time	8.64 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:43:07 PM PDT 24
Peak memory	230140 kb
Host	smart-10a92bfe-bd47-4268-b631-677206e71b2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147128112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.147128112
Directory	/workspace/11.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/11.spi_device_read_buffer_direct.2156014085
Short name	T322
Test name
Test status
Simulation time	1234325782 ps
CPU time	17.44 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:43:16 PM PDT 24
Peak memory	222648 kb
Host	smart-e9fc5112-3c85-4995-a75d-705d6d2d1035
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2156014085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir ect.2156014085
Directory	/workspace/11.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/11.spi_device_stress_all.653375519
Short name	T794
Test name
Test status
Simulation time	56213531216 ps
CPU time	274.12 seconds
Started	May 23 02:43:02 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	260068 kb
Host	smart-e8918f57-28c4-49f1-a4a4-f9b3fc9ba78c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653375519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres s_all.653375519
Directory	/workspace/11.spi_device_stress_all/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_all.3888406473
Short name	T835
Test name
Test status
Simulation time	5981652892 ps
CPU time	24.32 seconds
Started	May 23 02:43:01 PM PDT 24
Finished	May 23 02:43:26 PM PDT 24
Peak memory	216224 kb
Host	smart-c3867457-5544-4329-b838-e6200c3adc00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888406473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3888406473
Directory	/workspace/11.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.108956323
Short name	T478
Test name
Test status
Simulation time	939273353 ps
CPU time	2.2 seconds
Started	May 23 02:42:48 PM PDT 24
Finished	May 23 02:42:51 PM PDT 24
Peak memory	216016 kb
Host	smart-4e5216cb-eb02-4cee-a4e2-4addd09e33f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108956323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.108956323
Directory	/workspace/11.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_rw.3207344531
Short name	T354
Test name
Test status
Simulation time	36483142 ps
CPU time	1.93 seconds
Started	May 23 02:43:00 PM PDT 24
Finished	May 23 02:43:02 PM PDT 24
Peak memory	216124 kb
Host	smart-521795ae-25ea-4295-82b0-db92ef3f9b24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207344531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3207344531
Directory	/workspace/11.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_sts_read.1466525750
Short name	T46
Test name
Test status
Simulation time	42538292 ps
CPU time	0.92 seconds
Started	May 23 02:42:58 PM PDT 24
Finished	May 23 02:42:59 PM PDT 24
Peak memory	206756 kb
Host	smart-d5c2059b-964c-44a9-ba71-a1682530ea93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466525750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1466525750
Directory	/workspace/11.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/11.spi_device_upload.1132545678
Short name	T438
Test name
Test status
Simulation time	2510830525 ps
CPU time	11.57 seconds
Started	May 23 02:43:01 PM PDT 24
Finished	May 23 02:43:13 PM PDT 24
Peak memory	233836 kb
Host	smart-37e879ab-fe78-4f9b-8170-d3bd56e0725d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132545678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1132545678
Directory	/workspace/11.spi_device_upload/latest

Test location	/workspace/coverage/default/12.spi_device_alert_test.242791166
Short name	T804
Test name
Test status
Simulation time	14013582 ps
CPU time	0.72 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:11 PM PDT 24
Peak memory	205620 kb
Host	smart-36832681-c840-4288-90b7-acb32a4c768f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242791166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.242791166
Directory	/workspace/12.spi_device_alert_test/latest

Test location	/workspace/coverage/default/12.spi_device_cfg_cmd.3094973197
Short name	T90
Test name
Test status
Simulation time	830856680 ps
CPU time	7.53 seconds
Started	May 23 02:43:08 PM PDT 24
Finished	May 23 02:43:16 PM PDT 24
Peak memory	220084 kb
Host	smart-951cd55a-a5b6-4ba0-a9cf-6fc494fd267b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094973197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3094973197
Directory	/workspace/12.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/12.spi_device_csb_read.1790091587
Short name	T951
Test name
Test status
Simulation time	18369338 ps
CPU time	0.8 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	206472 kb
Host	smart-18ae6cbb-0224-4f27-95ed-063fb4218b12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790091587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1790091587
Directory	/workspace/12.spi_device_csb_read/latest

Test location	/workspace/coverage/default/12.spi_device_flash_all.3500527518
Short name	T832
Test name
Test status
Simulation time	24376303471 ps
CPU time	175.37 seconds
Started	May 23 02:43:10 PM PDT 24
Finished	May 23 02:46:06 PM PDT 24
Peak memory	257204 kb
Host	smart-5cc9ed9a-7c83-4985-83fd-58bff7df7ebd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500527518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3500527518
Directory	/workspace/12.spi_device_flash_all/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm.2308783830
Short name	T885
Test name
Test status
Simulation time	2785300601 ps
CPU time	33.31 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:43 PM PDT 24
Peak memory	224528 kb
Host	smart-c03199fb-eca4-4e64-a5e3-84bf725f589f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308783830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2308783830
Directory	/workspace/12.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3806697743
Short name	T667
Test name
Test status
Simulation time	36125906087 ps
CPU time	150.01 seconds
Started	May 23 02:43:10 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	239244 kb
Host	smart-b37640cb-efb4-4c54-8ac9-1570e6cad2f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806697743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl e.3806697743
Directory	/workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/12.spi_device_intercept.1638028070
Short name	T861
Test name
Test status
Simulation time	3666200516 ps
CPU time	25.91 seconds
Started	May 23 02:43:10 PM PDT 24
Finished	May 23 02:43:37 PM PDT 24
Peak memory	219720 kb
Host	smart-fe7cf252-908d-49ac-94b4-4b46b6c887fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638028070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1638028070
Directory	/workspace/12.spi_device_intercept/latest

Test location	/workspace/coverage/default/12.spi_device_mailbox.4028971862
Short name	T770
Test name
Test status
Simulation time	24148366053 ps
CPU time	19.31 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:30 PM PDT 24
Peak memory	223596 kb
Host	smart-b2a4d66f-0dfb-4b96-8bae-4f20acf432b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028971862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4028971862
Directory	/workspace/12.spi_device_mailbox/latest

Test location	/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1101748876
Short name	T755
Test name
Test status
Simulation time	11060806019 ps
CPU time	15.41 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:26 PM PDT 24
Peak memory	229488 kb
Host	smart-abe2dc36-5547-420f-8e5d-2ec2a49bc162
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101748876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.1101748876
Directory	/workspace/12.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/12.spi_device_pass_cmd_filtering.3279882620
Short name	T650
Test name
Test status
Simulation time	3901450345 ps
CPU time	8 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:18 PM PDT 24
Peak memory	239684 kb
Host	smart-67e2d327-cecc-45b6-83d3-f3a4365dc0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279882620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3279882620
Directory	/workspace/12.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/12.spi_device_read_buffer_direct.1206162475
Short name	T737
Test name
Test status
Simulation time	2705357097 ps
CPU time	10.14 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:20 PM PDT 24
Peak memory	219992 kb
Host	smart-e22c32f1-b7f2-4d93-8c45-5c481de208a4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1206162475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir ect.1206162475
Directory	/workspace/12.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/12.spi_device_stress_all.4201718423
Short name	T765
Test name
Test status
Simulation time	154969428 ps
CPU time	1.01 seconds
Started	May 23 02:43:10 PM PDT 24
Finished	May 23 02:43:12 PM PDT 24
Peak memory	206940 kb
Host	smart-938fa6eb-869e-427d-a1f4-c292ef1b0fb2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201718423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre ss_all.4201718423
Directory	/workspace/12.spi_device_stress_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_all.373498298
Short name	T338
Test name
Test status
Simulation time	5115914984 ps
CPU time	7.08 seconds
Started	May 23 02:43:02 PM PDT 24
Finished	May 23 02:43:10 PM PDT 24
Peak memory	216280 kb
Host	smart-ca70f06f-df9c-4fc1-8ef8-e88b4487af85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373498298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.373498298
Directory	/workspace/12.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3508597559
Short name	T535
Test name
Test status
Simulation time	735113925 ps
CPU time	3.4 seconds
Started	May 23 02:43:02 PM PDT 24
Finished	May 23 02:43:06 PM PDT 24
Peak memory	216080 kb
Host	smart-0db031eb-ea3f-442b-9df0-110a7ba4db04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508597559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3508597559
Directory	/workspace/12.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_rw.2902697623
Short name	T654
Test name
Test status
Simulation time	80712750 ps
CPU time	1.52 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:12 PM PDT 24
Peak memory	216132 kb
Host	smart-c13c26c4-f213-4863-a98c-3379a01a36fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902697623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2902697623
Directory	/workspace/12.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_sts_read.2047182264
Short name	T679
Test name
Test status
Simulation time	222425359 ps
CPU time	1.02 seconds
Started	May 23 02:42:59 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	206800 kb
Host	smart-daede729-0b04-42a9-bd4e-11566e7955f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047182264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2047182264
Directory	/workspace/12.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/12.spi_device_upload.2699662725
Short name	T870
Test name
Test status
Simulation time	2377661164 ps
CPU time	6.47 seconds
Started	May 23 02:43:09 PM PDT 24
Finished	May 23 02:43:16 PM PDT 24
Peak memory	234104 kb
Host	smart-91a84629-bbb3-446c-84b6-70455dfb2fea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699662725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2699662725
Directory	/workspace/12.spi_device_upload/latest

Test location	/workspace/coverage/default/13.spi_device_alert_test.2164166211
Short name	T67
Test name
Test status
Simulation time	38421135 ps
CPU time	0.72 seconds
Started	May 23 02:43:20 PM PDT 24
Finished	May 23 02:43:22 PM PDT 24
Peak memory	205308 kb
Host	smart-2263edf5-3919-41e8-ac8f-7ca3632f26d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164166211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test. 2164166211
Directory	/workspace/13.spi_device_alert_test/latest

Test location	/workspace/coverage/default/13.spi_device_cfg_cmd.3950057076
Short name	T754
Test name
Test status
Simulation time	396197631 ps
CPU time	2.56 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:43:25 PM PDT 24
Peak memory	233544 kb
Host	smart-39c1c3b2-4eb3-49ca-b2a0-4127b758d0c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950057076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3950057076
Directory	/workspace/13.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/13.spi_device_csb_read.69190279
Short name	T497
Test name
Test status
Simulation time	132410579 ps
CPU time	0.78 seconds
Started	May 23 02:43:12 PM PDT 24
Finished	May 23 02:43:14 PM PDT 24
Peak memory	206464 kb
Host	smart-430678c4-7898-4676-975c-a1c119fbb627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69190279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.69190279
Directory	/workspace/13.spi_device_csb_read/latest

Test location	/workspace/coverage/default/13.spi_device_flash_all.3415003404
Short name	T229
Test name
Test status
Simulation time	4206602400 ps
CPU time	30.35 seconds
Started	May 23 02:43:23 PM PDT 24
Finished	May 23 02:43:54 PM PDT 24
Peak memory	253920 kb
Host	smart-1ab2780c-fc6b-444e-b0d3-d031f440125b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415003404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3415003404
Directory	/workspace/13.spi_device_flash_all/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm.2208629424
Short name	T267
Test name
Test status
Simulation time	22442651167 ps
CPU time	298.89 seconds
Started	May 23 02:43:22 PM PDT 24
Finished	May 23 02:48:22 PM PDT 24
Peak memory	265040 kb
Host	smart-6df283bb-68a6-48cb-ba73-7ba037aae466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208629424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2208629424
Directory	/workspace/13.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.477654663
Short name	T240
Test name
Test status
Simulation time	5413734188 ps
CPU time	23.83 seconds
Started	May 23 02:43:23 PM PDT 24
Finished	May 23 02:43:48 PM PDT 24
Peak memory	249052 kb
Host	smart-97116ed4-1e13-4c8f-b431-fc57d49f0a30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477654663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle .477654663
Directory	/workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/13.spi_device_flash_mode.985078801
Short name	T923
Test name
Test status
Simulation time	1486852554 ps
CPU time	16.08 seconds
Started	May 23 02:43:22 PM PDT 24
Finished	May 23 02:43:39 PM PDT 24
Peak memory	249836 kb
Host	smart-c04b112e-99f3-4356-8b9a-f6d59d7ba974
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985078801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.985078801
Directory	/workspace/13.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/13.spi_device_intercept.1355745106
Short name	T666
Test name
Test status
Simulation time	6022120137 ps
CPU time	10.51 seconds
Started	May 23 02:43:20 PM PDT 24
Finished	May 23 02:43:31 PM PDT 24
Peak memory	221444 kb
Host	smart-97b11659-db87-4d5d-a050-109289d3103c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355745106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1355745106
Directory	/workspace/13.spi_device_intercept/latest

Test location	/workspace/coverage/default/13.spi_device_mailbox.724140177
Short name	T448
Test name
Test status
Simulation time	4685750621 ps
CPU time	11.42 seconds
Started	May 23 02:43:19 PM PDT 24
Finished	May 23 02:43:31 PM PDT 24
Peak memory	235160 kb
Host	smart-85ba00d1-815d-43ec-b21f-acc3e34b9ba4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724140177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.724140177
Directory	/workspace/13.spi_device_mailbox/latest

Test location	/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2480860415
Short name	T766
Test name
Test status
Simulation time	160083889 ps
CPU time	4.39 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:43:26 PM PDT 24
Peak memory	234660 kb
Host	smart-ed7a060b-c752-4ea1-8b25-6a4b179fb4d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480860415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa p.2480860415
Directory	/workspace/13.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/13.spi_device_pass_cmd_filtering.461611165
Short name	T783
Test name
Test status
Simulation time	18679994568 ps
CPU time	8.49 seconds
Started	May 23 02:43:18 PM PDT 24
Finished	May 23 02:43:28 PM PDT 24
Peak memory	218952 kb
Host	smart-2349afa9-50ad-479d-8c49-b4133cc295f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461611165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.461611165
Directory	/workspace/13.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/13.spi_device_read_buffer_direct.3336858516
Short name	T45
Test name
Test status
Simulation time	6555699134 ps
CPU time	17.88 seconds
Started	May 23 02:43:22 PM PDT 24
Finished	May 23 02:43:41 PM PDT 24
Peak memory	219096 kb
Host	smart-594666ba-81f3-4dbc-944d-2dbcf3dbc3b3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3336858516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.3336858516
Directory	/workspace/13.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/13.spi_device_stress_all.3139498271
Short name	T711
Test name
Test status
Simulation time	19990939610 ps
CPU time	178.1 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	251608 kb
Host	smart-1bfaeee4-f5fe-4320-9ab0-d938c5fa7072
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139498271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre ss_all.3139498271
Directory	/workspace/13.spi_device_stress_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_all.1962082105
Short name	T408
Test name
Test status
Simulation time	2110131320 ps
CPU time	13.31 seconds
Started	May 23 02:43:20 PM PDT 24
Finished	May 23 02:43:34 PM PDT 24
Peak memory	216220 kb
Host	smart-c1b2aaef-685e-4773-8466-df622b9fe0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962082105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1962082105
Directory	/workspace/13.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3804703732
Short name	T903
Test name
Test status
Simulation time	6578118846 ps
CPU time	10.29 seconds
Started	May 23 02:43:10 PM PDT 24
Finished	May 23 02:43:21 PM PDT 24
Peak memory	215988 kb
Host	smart-32b6be60-fbc0-4277-86da-d6f3af9761ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804703732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3804703732
Directory	/workspace/13.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_rw.3781246781
Short name	T587
Test name
Test status
Simulation time	326103268 ps
CPU time	4.45 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:43:26 PM PDT 24
Peak memory	216144 kb
Host	smart-51ae6598-f0fc-4780-8351-3d1e1de9f3fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781246781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3781246781
Directory	/workspace/13.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_sts_read.3442715120
Short name	T653
Test name
Test status
Simulation time	57331050 ps
CPU time	0.76 seconds
Started	May 23 02:43:20 PM PDT 24
Finished	May 23 02:43:21 PM PDT 24
Peak memory	205760 kb
Host	smart-d648c6f7-da70-48aa-b095-0ae42ef1e815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442715120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3442715120
Directory	/workspace/13.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/13.spi_device_upload.2743394827
Short name	T715
Test name
Test status
Simulation time	24001413644 ps
CPU time	20.34 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:43:42 PM PDT 24
Peak memory	234316 kb
Host	smart-09ed78c5-8d8e-46be-88c5-939b3500a5fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743394827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2743394827
Directory	/workspace/13.spi_device_upload/latest

Test location	/workspace/coverage/default/14.spi_device_alert_test.1546059170
Short name	T602
Test name
Test status
Simulation time	22743536 ps
CPU time	0.74 seconds
Started	May 23 02:43:36 PM PDT 24
Finished	May 23 02:43:38 PM PDT 24
Peak memory	205276 kb
Host	smart-ceeeb4c0-ba85-49fc-8f49-6bb0b41c94ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546059170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 1546059170
Directory	/workspace/14.spi_device_alert_test/latest

Test location	/workspace/coverage/default/14.spi_device_cfg_cmd.1990489122
Short name	T482
Test name
Test status
Simulation time	1367611624 ps
CPU time	10.29 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:45 PM PDT 24
Peak memory	233516 kb
Host	smart-9a262538-55f6-4010-a2ca-47accb558149
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990489122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1990489122
Directory	/workspace/14.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/14.spi_device_csb_read.3388266147
Short name	T384
Test name
Test status
Simulation time	16860755 ps
CPU time	0.75 seconds
Started	May 23 02:43:21 PM PDT 24
Finished	May 23 02:43:23 PM PDT 24
Peak memory	205416 kb
Host	smart-5f340c3c-39f8-4a06-8375-93a35d7f58ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388266147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3388266147
Directory	/workspace/14.spi_device_csb_read/latest

Test location	/workspace/coverage/default/14.spi_device_flash_all.3814948899
Short name	T549
Test name
Test status
Simulation time	5401680207 ps
CPU time	46.57 seconds
Started	May 23 02:43:37 PM PDT 24
Finished	May 23 02:44:24 PM PDT 24
Peak memory	250156 kb
Host	smart-6fdf022c-8295-4b46-b6f0-5e820a90031c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814948899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3814948899
Directory	/workspace/14.spi_device_flash_all/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1621603099
Short name	T196
Test name
Test status
Simulation time	15765094019 ps
CPU time	38.89 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:44:14 PM PDT 24
Peak memory	240944 kb
Host	smart-74b0cdef-194f-4b78-88ef-f8faa65ceeab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621603099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl e.1621603099
Directory	/workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/14.spi_device_flash_mode.2179003843
Short name	T486
Test name
Test status
Simulation time	9272646105 ps
CPU time	35.22 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:44:11 PM PDT 24
Peak memory	232628 kb
Host	smart-1d1341ec-16b9-48f0-8f16-c3f1e4431ac0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179003843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2179003843
Directory	/workspace/14.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/14.spi_device_intercept.1898990205
Short name	T409
Test name
Test status
Simulation time	110577857 ps
CPU time	2.7 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:37 PM PDT 24
Peak memory	218324 kb
Host	smart-d6d406d2-78f4-4b64-aa0d-6c7e992f1beb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898990205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1898990205
Directory	/workspace/14.spi_device_intercept/latest

Test location	/workspace/coverage/default/14.spi_device_mailbox.472863665
Short name	T256
Test name
Test status
Simulation time	166680276 ps
CPU time	2.84 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:43:39 PM PDT 24
Peak memory	218448 kb
Host	smart-3289d462-5505-4882-8dd3-4f19fb5e7f82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472863665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.472863665
Directory	/workspace/14.spi_device_mailbox/latest

Test location	/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1888403454
Short name	T272
Test name
Test status
Simulation time	147605054 ps
CPU time	4.41 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:43:40 PM PDT 24
Peak memory	233640 kb
Host	smart-3e6bc98f-d336-4ea1-83ee-c309f4c61719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888403454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.1888403454
Directory	/workspace/14.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/14.spi_device_pass_cmd_filtering.2488565464
Short name	T35
Test name
Test status
Simulation time	12490661012 ps
CPU time	9.32 seconds
Started	May 23 02:43:33 PM PDT 24
Finished	May 23 02:43:43 PM PDT 24
Peak memory	235124 kb
Host	smart-3ed73fb1-973d-4da8-8264-1f8389f8eb5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488565464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2488565464
Directory	/workspace/14.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/14.spi_device_read_buffer_direct.2038663446
Short name	T344
Test name
Test status
Simulation time	1961273806 ps
CPU time	12.79 seconds
Started	May 23 02:43:35 PM PDT 24
Finished	May 23 02:43:48 PM PDT 24
Peak memory	222676 kb
Host	smart-79d3d99e-7fef-441f-8d5f-69da00a3393c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2038663446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir ect.2038663446
Directory	/workspace/14.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_all.457014970
Short name	T911
Test name
Test status
Simulation time	5436092371 ps
CPU time	18.64 seconds
Started	May 23 02:43:33 PM PDT 24
Finished	May 23 02:43:52 PM PDT 24
Peak memory	216348 kb
Host	smart-0a3acb2b-768e-4bb4-9094-fe8e0b6cdac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457014970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.457014970
Directory	/workspace/14.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1269270994
Short name	T732
Test name
Test status
Simulation time	9995716471 ps
CPU time	26.02 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:44:01 PM PDT 24
Peak memory	216136 kb
Host	smart-923226a9-204a-4532-b58f-56ea9a855a4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269270994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1269270994
Directory	/workspace/14.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_rw.2326758810
Short name	T483
Test name
Test status
Simulation time	352976357 ps
CPU time	2.36 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:37 PM PDT 24
Peak memory	216268 kb
Host	smart-26f7578e-1174-459e-8922-5aee09b9eb57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326758810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2326758810
Directory	/workspace/14.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_sts_read.2776280038
Short name	T600
Test name
Test status
Simulation time	47157813 ps
CPU time	0.88 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:36 PM PDT 24
Peak memory	205740 kb
Host	smart-18ef156c-80d5-4b98-a198-025b4e717e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776280038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2776280038
Directory	/workspace/14.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/14.spi_device_upload.1974935058
Short name	T398
Test name
Test status
Simulation time	6783269565 ps
CPU time	20.79 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:56 PM PDT 24
Peak memory	233384 kb
Host	smart-7bf3694e-341e-4dbd-b057-3d397830b507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974935058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1974935058
Directory	/workspace/14.spi_device_upload/latest

Test location	/workspace/coverage/default/15.spi_device_alert_test.1938338842
Short name	T792
Test name
Test status
Simulation time	14905045 ps
CPU time	0.74 seconds
Started	May 23 02:43:54 PM PDT 24
Finished	May 23 02:43:56 PM PDT 24
Peak memory	204740 kb
Host	smart-4e324463-ec5f-4fe2-8e20-ce1d1afcd0d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938338842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 1938338842
Directory	/workspace/15.spi_device_alert_test/latest

Test location	/workspace/coverage/default/15.spi_device_cfg_cmd.2091936716
Short name	T412
Test name
Test status
Simulation time	4431567332 ps
CPU time	12.2 seconds
Started	May 23 02:43:53 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	237784 kb
Host	smart-16f735ed-3a9f-4942-8450-4458a71dfa4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091936716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2091936716
Directory	/workspace/15.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/15.spi_device_csb_read.3328463511
Short name	T499
Test name
Test status
Simulation time	56666639 ps
CPU time	0.79 seconds
Started	May 23 02:43:36 PM PDT 24
Finished	May 23 02:43:37 PM PDT 24
Peak memory	206468 kb
Host	smart-8f1d9fb9-fed7-4a1f-903f-ef21cf03bcb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328463511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3328463511
Directory	/workspace/15.spi_device_csb_read/latest

Test location	/workspace/coverage/default/15.spi_device_flash_all.800639235
Short name	T550
Test name
Test status
Simulation time	9969343700 ps
CPU time	58.45 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:44:55 PM PDT 24
Peak memory	249844 kb
Host	smart-cc76a39c-37ac-4b96-a2e5-c6cdd753e605
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800639235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.800639235
Directory	/workspace/15.spi_device_flash_all/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm.2163541746
Short name	T784
Test name
Test status
Simulation time	2354609502 ps
CPU time	26.68 seconds
Started	May 23 02:43:53 PM PDT 24
Finished	May 23 02:44:20 PM PDT 24
Peak memory	220600 kb
Host	smart-c9df0cee-6d51-47ff-b190-d116142d12de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163541746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2163541746
Directory	/workspace/15.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3795495287
Short name	T269
Test name
Test status
Simulation time	2218410005 ps
CPU time	59.89 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:44:56 PM PDT 24
Peak memory	265496 kb
Host	smart-c02caa37-287b-47ef-b841-d48502b8b9ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795495287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl e.3795495287
Directory	/workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/15.spi_device_flash_mode.2465082989
Short name	T47
Test name
Test status
Simulation time	3606690543 ps
CPU time	10.45 seconds
Started	May 23 02:43:59 PM PDT 24
Finished	May 23 02:44:11 PM PDT 24
Peak memory	237532 kb
Host	smart-633089b0-a14f-44ad-95ad-c8ec8fb6d8ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465082989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2465082989
Directory	/workspace/15.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/15.spi_device_intercept.2749342078
Short name	T176
Test name
Test status
Simulation time	1212904328 ps
CPU time	14.24 seconds
Started	May 23 02:43:34 PM PDT 24
Finished	May 23 02:43:49 PM PDT 24
Peak memory	233428 kb
Host	smart-c90eac73-421d-4cbd-94d4-60d0800ea827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749342078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2749342078
Directory	/workspace/15.spi_device_intercept/latest

Test location	/workspace/coverage/default/15.spi_device_mailbox.834535169
Short name	T645
Test name
Test status
Simulation time	44599735889 ps
CPU time	101.53 seconds
Started	May 23 02:43:54 PM PDT 24
Finished	May 23 02:45:36 PM PDT 24
Peak memory	231504 kb
Host	smart-f3a09530-e793-4fd5-bd06-4a5f2b7aff87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834535169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.834535169
Directory	/workspace/15.spi_device_mailbox/latest

Test location	/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2813110124
Short name	T191
Test name
Test status
Simulation time	42346736282 ps
CPU time	19.74 seconds
Started	May 23 02:43:36 PM PDT 24
Finished	May 23 02:43:56 PM PDT 24
Peak memory	233120 kb
Host	smart-35bd9774-389d-44f1-9c07-d5811b0e20b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813110124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa p.2813110124
Directory	/workspace/15.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/15.spi_device_pass_cmd_filtering.1514983380
Short name	T442
Test name
Test status
Simulation time	1641111565 ps
CPU time	5.79 seconds
Started	May 23 02:43:37 PM PDT 24
Finished	May 23 02:43:44 PM PDT 24
Peak memory	233128 kb
Host	smart-27b562c5-5d7d-4b0a-b27e-3dccaa1e5bf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514983380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1514983380
Directory	/workspace/15.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/15.spi_device_read_buffer_direct.246245358
Short name	T548
Test name
Test status
Simulation time	190437686 ps
CPU time	4.19 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:44:00 PM PDT 24
Peak memory	222860 kb
Host	smart-49c8a002-a7eb-465f-bf9a-110218ad1f73
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=246245358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire ct.246245358
Directory	/workspace/15.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/15.spi_device_stress_all.1411950293
Short name	T750
Test name
Test status
Simulation time	25913543866 ps
CPU time	239.63 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:47:56 PM PDT 24
Peak memory	250960 kb
Host	smart-d13c90a7-a6c5-4894-8aa8-47b85006503f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411950293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre ss_all.1411950293
Directory	/workspace/15.spi_device_stress_all/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_all.1728726129
Short name	T827
Test name
Test status
Simulation time	4617710242 ps
CPU time	27.08 seconds
Started	May 23 02:43:38 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	216256 kb
Host	smart-43946d1a-35e3-4720-b758-f508ee5747de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728726129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1728726129
Directory	/workspace/15.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1258151195
Short name	T692
Test name
Test status
Simulation time	5780379698 ps
CPU time	10.42 seconds
Started	May 23 02:43:36 PM PDT 24
Finished	May 23 02:43:48 PM PDT 24
Peak memory	216144 kb
Host	smart-9e1e4dbe-2664-42cc-ba58-5446b08eeac8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258151195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1258151195
Directory	/workspace/15.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_rw.2058966547
Short name	T516
Test name
Test status
Simulation time	151793711 ps
CPU time	1.56 seconds
Started	May 23 02:43:38 PM PDT 24
Finished	May 23 02:43:41 PM PDT 24
Peak memory	216188 kb
Host	smart-451cc957-6401-4443-9dab-c11630d00e0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058966547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2058966547
Directory	/workspace/15.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_sts_read.3959080711
Short name	T712
Test name
Test status
Simulation time	139935026 ps
CPU time	1.11 seconds
Started	May 23 02:43:38 PM PDT 24
Finished	May 23 02:43:40 PM PDT 24
Peak memory	206200 kb
Host	smart-8159b588-e334-4a48-b017-c33a79a1dd27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959080711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3959080711
Directory	/workspace/15.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/15.spi_device_upload.1339816512
Short name	T830
Test name
Test status
Simulation time	12026578591 ps
CPU time	21.5 seconds
Started	May 23 02:43:54 PM PDT 24
Finished	May 23 02:44:16 PM PDT 24
Peak memory	234416 kb
Host	smart-e8ea3c68-e108-4688-ad73-9d29a46f726f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339816512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1339816512
Directory	/workspace/15.spi_device_upload/latest

Test location	/workspace/coverage/default/16.spi_device_alert_test.3023257964
Short name	T933
Test name
Test status
Simulation time	62780979 ps
CPU time	0.72 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:43:57 PM PDT 24
Peak memory	205284 kb
Host	smart-8dd2b39c-ab1b-4287-b0ec-462d227d5fd1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023257964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 3023257964
Directory	/workspace/16.spi_device_alert_test/latest

Test location	/workspace/coverage/default/16.spi_device_cfg_cmd.4111479653
Short name	T514
Test name
Test status
Simulation time	39350426 ps
CPU time	2.67 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:43:58 PM PDT 24
Peak memory	234068 kb
Host	smart-cad311b8-e52d-46d7-8c56-4296ad15b80c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111479653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4111479653
Directory	/workspace/16.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/16.spi_device_csb_read.12212834
Short name	T361
Test name
Test status
Simulation time	17842857 ps
CPU time	0.85 seconds
Started	May 23 02:43:58 PM PDT 24
Finished	May 23 02:43:59 PM PDT 24
Peak memory	206460 kb
Host	smart-add21508-f0ec-419a-804e-e8237594ee07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12212834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.12212834
Directory	/workspace/16.spi_device_csb_read/latest

Test location	/workspace/coverage/default/16.spi_device_flash_all.1676046360
Short name	T61
Test name
Test status
Simulation time	6114520122 ps
CPU time	29.46 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:44:26 PM PDT 24
Peak memory	235380 kb
Host	smart-e5d1b04e-7b79-43da-853f-d5341a83c509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676046360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1676046360
Directory	/workspace/16.spi_device_flash_all/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm.3503423212
Short name	T275
Test name
Test status
Simulation time	315049913033 ps
CPU time	729.41 seconds
Started	May 23 02:43:58 PM PDT 24
Finished	May 23 02:56:08 PM PDT 24
Peak memory	264276 kb
Host	smart-65f4ef1a-e666-4484-93ed-8a569d590804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503423212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3503423212
Directory	/workspace/16.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.716537659
Short name	T228
Test name
Test status
Simulation time	5178331543 ps
CPU time	87.51 seconds
Started	May 23 02:43:59 PM PDT 24
Finished	May 23 02:45:28 PM PDT 24
Peak memory	249108 kb
Host	smart-f2e8c8c1-4a67-46ab-bcc6-54c645fd2493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716537659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle .716537659
Directory	/workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/16.spi_device_flash_mode.97258973
Short name	T577
Test name
Test status
Simulation time	58466839 ps
CPU time	3.22 seconds
Started	May 23 02:43:59 PM PDT 24
Finished	May 23 02:44:03 PM PDT 24
Peak memory	232576 kb
Host	smart-cda14259-58d2-4fcc-94d6-6f27ea414864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97258973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.97258973
Directory	/workspace/16.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/16.spi_device_intercept.548998572
Short name	T487
Test name
Test status
Simulation time	251785690 ps
CPU time	3.11 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:44:00 PM PDT 24
Peak memory	218572 kb
Host	smart-1ad878e2-83f7-4d9b-9d19-002c7fe7d15c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548998572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.548998572
Directory	/workspace/16.spi_device_intercept/latest

Test location	/workspace/coverage/default/16.spi_device_mailbox.2637141500
Short name	T595
Test name
Test status
Simulation time	9617711643 ps
CPU time	28.87 seconds
Started	May 23 02:43:57 PM PDT 24
Finished	May 23 02:44:27 PM PDT 24
Peak memory	233280 kb
Host	smart-b067ab65-be45-4836-8a31-b262d7ca676d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637141500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2637141500
Directory	/workspace/16.spi_device_mailbox/latest

Test location	/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.292384776
Short name	T696
Test name
Test status
Simulation time	9631041935 ps
CPU time	12.02 seconds
Started	May 23 02:43:56 PM PDT 24
Finished	May 23 02:44:08 PM PDT 24
Peak memory	236292 kb
Host	smart-9a458dbe-b1b4-4b44-9d54-33d7d4ee1b0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292384776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap .292384776
Directory	/workspace/16.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/16.spi_device_read_buffer_direct.369318780
Short name	T143
Test name
Test status
Simulation time	729677187 ps
CPU time	4.12 seconds
Started	May 23 02:43:58 PM PDT 24
Finished	May 23 02:44:03 PM PDT 24
Peak memory	218976 kb
Host	smart-0025b114-7f23-4ab1-afdd-b5f1f95e8b6a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=369318780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire ct.369318780
Directory	/workspace/16.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_all.2752984245
Short name	T476
Test name
Test status
Simulation time	39484750 ps
CPU time	0.72 seconds
Started	May 23 02:43:57 PM PDT 24
Finished	May 23 02:43:59 PM PDT 24
Peak memory	205592 kb
Host	smart-d6f9fe7c-dc6c-43cc-8f60-aef74b5dae76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752984245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2752984245
Directory	/workspace/16.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2703303161
Short name	T362
Test name
Test status
Simulation time	152726286 ps
CPU time	1.86 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:43:57 PM PDT 24
Peak memory	207768 kb
Host	smart-9cc26db3-1a0a-4a2c-8075-1f6986b6c137
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703303161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2703303161
Directory	/workspace/16.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_rw.1629476599
Short name	T17
Test name
Test status
Simulation time	370734033 ps
CPU time	1.83 seconds
Started	May 23 02:43:55 PM PDT 24
Finished	May 23 02:43:57 PM PDT 24
Peak memory	216452 kb
Host	smart-6bf05ba8-1496-4e74-b716-5c2839e3cda5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629476599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1629476599
Directory	/workspace/16.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_sts_read.84006619
Short name	T518
Test name
Test status
Simulation time	150647791 ps
CPU time	0.88 seconds
Started	May 23 02:43:58 PM PDT 24
Finished	May 23 02:43:59 PM PDT 24
Peak memory	205696 kb
Host	smart-7c8a6bdd-fe4a-4ec3-abf0-7b9a7b14a099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84006619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.84006619
Directory	/workspace/16.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/16.spi_device_upload.1297575622
Short name	T698
Test name
Test status
Simulation time	5654207917 ps
CPU time	9.15 seconds
Started	May 23 02:43:57 PM PDT 24
Finished	May 23 02:44:07 PM PDT 24
Peak memory	222248 kb
Host	smart-e28e1e61-3727-46f9-955a-d969ae5a8e3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297575622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1297575622
Directory	/workspace/16.spi_device_upload/latest

Test location	/workspace/coverage/default/17.spi_device_alert_test.3876134784
Short name	T329
Test name
Test status
Simulation time	50940678 ps
CPU time	0.73 seconds
Started	May 23 02:44:12 PM PDT 24
Finished	May 23 02:44:14 PM PDT 24
Peak memory	204756 kb
Host	smart-86f9f9f2-8a1e-413c-b2ac-1f5bffb361bd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876134784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 3876134784
Directory	/workspace/17.spi_device_alert_test/latest

Test location	/workspace/coverage/default/17.spi_device_cfg_cmd.3975530894
Short name	T569
Test name
Test status
Simulation time	863904043 ps
CPU time	8.77 seconds
Started	May 23 02:44:06 PM PDT 24
Finished	May 23 02:44:16 PM PDT 24
Peak memory	234212 kb
Host	smart-a9a2c61f-6bc2-4c57-957e-3278e9281fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975530894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3975530894
Directory	/workspace/17.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/17.spi_device_csb_read.2730707547
Short name	T304
Test name
Test status
Simulation time	54106363 ps
CPU time	0.75 seconds
Started	May 23 02:44:05 PM PDT 24
Finished	May 23 02:44:08 PM PDT 24
Peak memory	205784 kb
Host	smart-9da67817-191a-409f-abe8-a89dfdf21c0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730707547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2730707547
Directory	/workspace/17.spi_device_csb_read/latest

Test location	/workspace/coverage/default/17.spi_device_flash_all.615529156
Short name	T236
Test name
Test status
Simulation time	4146073032 ps
CPU time	56.48 seconds
Started	May 23 02:44:04 PM PDT 24
Finished	May 23 02:45:02 PM PDT 24
Peak memory	240832 kb
Host	smart-1ceee453-e9ba-4c81-8b04-cdb6657e6e32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615529156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.615529156
Directory	/workspace/17.spi_device_flash_all/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm.228949639
Short name	T901
Test name
Test status
Simulation time	1758287303 ps
CPU time	44.64 seconds
Started	May 23 02:44:11 PM PDT 24
Finished	May 23 02:44:57 PM PDT 24
Peak memory	249036 kb
Host	smart-a76be63f-308c-4f9b-8447-bf9b9a338a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228949639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.228949639
Directory	/workspace/17.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3033476347
Short name	T883
Test name
Test status
Simulation time	3787935994 ps
CPU time	46.07 seconds
Started	May 23 02:44:10 PM PDT 24
Finished	May 23 02:44:58 PM PDT 24
Peak memory	234012 kb
Host	smart-30c76549-2e5a-4ce3-8163-94cb9f5b8c5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033476347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl e.3033476347
Directory	/workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/17.spi_device_flash_mode.97940796
Short name	T285
Test name
Test status
Simulation time	962481821 ps
CPU time	21.37 seconds
Started	May 23 02:44:11 PM PDT 24
Finished	May 23 02:44:34 PM PDT 24
Peak memory	232532 kb
Host	smart-20fc1ccb-8597-4a82-85b7-d287fd812484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97940796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.97940796
Directory	/workspace/17.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/17.spi_device_intercept.3088409159
Short name	T219
Test name
Test status
Simulation time	1232746169 ps
CPU time	2.29 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	218428 kb
Host	smart-6c26d3b7-4cc3-485d-80ee-46dd005165cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088409159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3088409159
Directory	/workspace/17.spi_device_intercept/latest

Test location	/workspace/coverage/default/17.spi_device_mailbox.449645558
Short name	T724
Test name
Test status
Simulation time	1340644856 ps
CPU time	29.9 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:35 PM PDT 24
Peak memory	240192 kb
Host	smart-138689eb-72b4-4b59-b46a-2f2d710784fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449645558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.449645558
Directory	/workspace/17.spi_device_mailbox/latest

Test location	/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2330167903
Short name	T181
Test name
Test status
Simulation time	278482992 ps
CPU time	2.75 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	233664 kb
Host	smart-74a9a5f5-0fb3-4f86-a9f7-ee5809118e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330167903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa p.2330167903
Directory	/workspace/17.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/17.spi_device_pass_cmd_filtering.1818511278
Short name	T782
Test name
Test status
Simulation time	18049835397 ps
CPU time	25.5 seconds
Started	May 23 02:44:05 PM PDT 24
Finished	May 23 02:44:32 PM PDT 24
Peak memory	229516 kb
Host	smart-7149a9d1-7743-40a4-b74f-ffda1db2b18b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818511278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1818511278
Directory	/workspace/17.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/17.spi_device_read_buffer_direct.2241450792
Short name	T79
Test name
Test status
Simulation time	207229550 ps
CPU time	4.88 seconds
Started	May 23 02:44:10 PM PDT 24
Finished	May 23 02:44:17 PM PDT 24
Peak memory	221116 kb
Host	smart-b0f9ac2f-6ec0-47de-a3c5-501af84a3080
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2241450792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir ect.2241450792
Directory	/workspace/17.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/17.spi_device_stress_all.353938742
Short name	T368
Test name
Test status
Simulation time	152744108 ps
CPU time	1.11 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	206932 kb
Host	smart-f5427f68-c979-4fae-b3e4-2ccebceb19ef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353938742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres s_all.353938742
Directory	/workspace/17.spi_device_stress_all/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_all.4027577196
Short name	T610
Test name
Test status
Simulation time	942645756 ps
CPU time	12.66 seconds
Started	May 23 02:44:02 PM PDT 24
Finished	May 23 02:44:15 PM PDT 24
Peak memory	219076 kb
Host	smart-2593b998-7250-46c9-a7b9-a6a92d23f992
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027577196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4027577196
Directory	/workspace/17.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4177050464
Short name	T327
Test name
Test status
Simulation time	18759435747 ps
CPU time	12.84 seconds
Started	May 23 02:44:02 PM PDT 24
Finished	May 23 02:44:15 PM PDT 24
Peak memory	216220 kb
Host	smart-6262daec-84b1-4932-80ea-aa803a11c194
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177050464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4177050464
Directory	/workspace/17.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_rw.324004690
Short name	T346
Test name
Test status
Simulation time	330732175 ps
CPU time	3.61 seconds
Started	May 23 02:44:04 PM PDT 24
Finished	May 23 02:44:09 PM PDT 24
Peak memory	216208 kb
Host	smart-144d4d8a-57cc-4e5a-bc6a-52c0c2929205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324004690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.324004690
Directory	/workspace/17.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_sts_read.2439119384
Short name	T925
Test name
Test status
Simulation time	24931213 ps
CPU time	0.8 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:05 PM PDT 24
Peak memory	205684 kb
Host	smart-9496e1ef-13b6-47c4-b69f-a1201e3c3440
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439119384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2439119384
Directory	/workspace/17.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/17.spi_device_upload.2740965439
Short name	T182
Test name
Test status
Simulation time	16205383187 ps
CPU time	14.35 seconds
Started	May 23 02:44:04 PM PDT 24
Finished	May 23 02:44:20 PM PDT 24
Peak memory	219056 kb
Host	smart-ec93106a-ebe4-4f07-8305-b4cfc246de72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740965439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2740965439
Directory	/workspace/17.spi_device_upload/latest

Test location	/workspace/coverage/default/18.spi_device_alert_test.72847164
Short name	T305
Test name
Test status
Simulation time	11729984 ps
CPU time	0.71 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:26 PM PDT 24
Peak memory	205612 kb
Host	smart-c36cc887-819f-4d80-b4f8-53167528ae9f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72847164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.72847164
Directory	/workspace/18.spi_device_alert_test/latest

Test location	/workspace/coverage/default/18.spi_device_cfg_cmd.966115864
Short name	T892
Test name
Test status
Simulation time	1126461823 ps
CPU time	13.61 seconds
Started	May 23 02:44:22 PM PDT 24
Finished	May 23 02:44:38 PM PDT 24
Peak memory	234664 kb
Host	smart-10bea3d4-33a8-450f-87ee-010f44412507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966115864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.966115864
Directory	/workspace/18.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/18.spi_device_csb_read.1215992830
Short name	T721
Test name
Test status
Simulation time	21807450 ps
CPU time	0.83 seconds
Started	May 23 02:44:04 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	206800 kb
Host	smart-de0bb23b-8b31-4a52-a6e2-44986fdc6ab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215992830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1215992830
Directory	/workspace/18.spi_device_csb_read/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm.1216245282
Short name	T668
Test name
Test status
Simulation time	6725915835 ps
CPU time	100.48 seconds
Started	May 23 02:44:22 PM PDT 24
Finished	May 23 02:46:04 PM PDT 24
Peak memory	247004 kb
Host	smart-5490fb80-d2e1-4ba7-a724-462a99e513e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216245282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1216245282
Directory	/workspace/18.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1713156936
Short name	T729
Test name
Test status
Simulation time	69728929264 ps
CPU time	140.96 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:46:46 PM PDT 24
Peak memory	232636 kb
Host	smart-60677216-d380-4e80-8617-88dcb7c302b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713156936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl e.1713156936
Directory	/workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/18.spi_device_flash_mode.3887551048
Short name	T51
Test name
Test status
Simulation time	281369621 ps
CPU time	2.6 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:28 PM PDT 24
Peak memory	232300 kb
Host	smart-b70a97aa-377c-41da-98bb-e7f5bd0fbd42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3887551048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3887551048
Directory	/workspace/18.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/18.spi_device_intercept.842942624
Short name	T563
Test name
Test status
Simulation time	2024022635 ps
CPU time	18.27 seconds
Started	May 23 02:44:22 PM PDT 24
Finished	May 23 02:44:43 PM PDT 24
Peak memory	224264 kb
Host	smart-3725c8b7-11bf-45f0-a3c1-1c211a138449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842942624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.842942624
Directory	/workspace/18.spi_device_intercept/latest

Test location	/workspace/coverage/default/18.spi_device_mailbox.2011323475
Short name	T366
Test name
Test status
Simulation time	380039976 ps
CPU time	10.08 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:35 PM PDT 24
Peak memory	243544 kb
Host	smart-7e5f6899-58e9-480f-b6f5-73985256c5fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011323475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2011323475
Directory	/workspace/18.spi_device_mailbox/latest

Test location	/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1832159673
Short name	T218
Test name
Test status
Simulation time	494471383 ps
CPU time	3.95 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:29 PM PDT 24
Peak memory	218524 kb
Host	smart-b2746700-bb55-43ea-8da9-99334564d5d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832159673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa p.1832159673
Directory	/workspace/18.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/18.spi_device_pass_cmd_filtering.2514431104
Short name	T175
Test name
Test status
Simulation time	11298353452 ps
CPU time	13.96 seconds
Started	May 23 02:44:05 PM PDT 24
Finished	May 23 02:44:21 PM PDT 24
Peak memory	218460 kb
Host	smart-69376dc8-9e5e-40e2-b820-f925e7dcbafc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514431104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2514431104
Directory	/workspace/18.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/18.spi_device_read_buffer_direct.3306052891
Short name	T441
Test name
Test status
Simulation time	22376093040 ps
CPU time	16.6 seconds
Started	May 23 02:44:22 PM PDT 24
Finished	May 23 02:44:41 PM PDT 24
Peak memory	222772 kb
Host	smart-7e78b04c-541f-4293-b37a-5a3d1a5938f6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3306052891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.3306052891
Directory	/workspace/18.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/18.spi_device_stress_all.4218929602
Short name	T452
Test name
Test status
Simulation time	48190325 ps
CPU time	1.04 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:26 PM PDT 24
Peak memory	206964 kb
Host	smart-e6b2a178-f0de-4377-abb9-f185ae7034e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218929602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre ss_all.4218929602
Directory	/workspace/18.spi_device_stress_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_all.3182197808
Short name	T916
Test name
Test status
Simulation time	3098435085 ps
CPU time	22.01 seconds
Started	May 23 02:44:05 PM PDT 24
Finished	May 23 02:44:28 PM PDT 24
Peak memory	216272 kb
Host	smart-1a25061f-2e6f-4431-afbd-aab4d1848bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182197808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3182197808
Directory	/workspace/18.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3158279964
Short name	T905
Test name
Test status
Simulation time	817128296 ps
CPU time	3.8 seconds
Started	May 23 02:44:07 PM PDT 24
Finished	May 23 02:44:12 PM PDT 24
Peak memory	216084 kb
Host	smart-4e3e25b9-b77e-4d7b-8564-5237035e8e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158279964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3158279964
Directory	/workspace/18.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_rw.8251162
Short name	T433
Test name
Test status
Simulation time	62554443 ps
CPU time	1.25 seconds
Started	May 23 02:44:03 PM PDT 24
Finished	May 23 02:44:06 PM PDT 24
Peak memory	207956 kb
Host	smart-73da9bd4-cdc9-4ece-ba4e-e8189ecb3841
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8251162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.8251162
Directory	/workspace/18.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_sts_read.3980057914
Short name	T759
Test name
Test status
Simulation time	303376876 ps
CPU time	0.79 seconds
Started	May 23 02:44:11 PM PDT 24
Finished	May 23 02:44:13 PM PDT 24
Peak memory	205716 kb
Host	smart-cbd48815-91cb-47f0-a3dd-4719659ec2fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980057914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3980057914
Directory	/workspace/18.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/18.spi_device_upload.3682803145
Short name	T786
Test name
Test status
Simulation time	6288505356 ps
CPU time	14.35 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:39 PM PDT 24
Peak memory	234276 kb
Host	smart-85a5d5b2-3fcb-4459-b8d4-80383528ea2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682803145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3682803145
Directory	/workspace/18.spi_device_upload/latest

Test location	/workspace/coverage/default/19.spi_device_alert_test.315546760
Short name	T632
Test name
Test status
Simulation time	182592807 ps
CPU time	0.76 seconds
Started	May 23 02:44:41 PM PDT 24
Finished	May 23 02:44:42 PM PDT 24
Peak memory	205328 kb
Host	smart-b5522f41-27a8-4340-897b-1f69838cd4f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315546760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.315546760
Directory	/workspace/19.spi_device_alert_test/latest

Test location	/workspace/coverage/default/19.spi_device_cfg_cmd.2448398985
Short name	T423
Test name
Test status
Simulation time	1666019513 ps
CPU time	5.61 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:44:44 PM PDT 24
Peak memory	233640 kb
Host	smart-1e3cbf10-74d9-4a4e-83ef-42ce01749eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448398985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2448398985
Directory	/workspace/19.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/19.spi_device_csb_read.3244222594
Short name	T922
Test name
Test status
Simulation time	24392161 ps
CPU time	0.73 seconds
Started	May 23 02:44:23 PM PDT 24
Finished	May 23 02:44:26 PM PDT 24
Peak memory	205236 kb
Host	smart-0e8f17e0-0026-4f5c-8db2-ffbc254c9e79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244222594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3244222594
Directory	/workspace/19.spi_device_csb_read/latest

Test location	/workspace/coverage/default/19.spi_device_flash_all.136013523
Short name	T491
Test name
Test status
Simulation time	33194447356 ps
CPU time	194.98 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:47:53 PM PDT 24
Peak memory	250364 kb
Host	smart-6dbdb906-d962-4d48-aa21-0b0a89ab636a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136013523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.136013523
Directory	/workspace/19.spi_device_flash_all/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm.3103784314
Short name	T748
Test name
Test status
Simulation time	8105326620 ps
CPU time	62.75 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	239840 kb
Host	smart-d8e6cbef-c4e4-4f40-9212-638986432596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103784314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3103784314
Directory	/workspace/19.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1847780365
Short name	T276
Test name
Test status
Simulation time	5734238242 ps
CPU time	35.44 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:45:13 PM PDT 24
Peak memory	232708 kb
Host	smart-851833ca-37ea-48a7-99f5-dd5358eee07b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847780365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl e.1847780365
Directory	/workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/19.spi_device_flash_mode.401098637
Short name	T820
Test name
Test status
Simulation time	1051835315 ps
CPU time	20.12 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:58 PM PDT 24
Peak memory	224424 kb
Host	smart-250e7080-843e-4392-a703-a89f4a466f06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401098637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.401098637
Directory	/workspace/19.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/19.spi_device_intercept.733041030
Short name	T2
Test name
Test status
Simulation time	1539972313 ps
CPU time	7.26 seconds
Started	May 23 02:44:35 PM PDT 24
Finished	May 23 02:44:44 PM PDT 24
Peak memory	233472 kb
Host	smart-fe0234a5-9720-429c-b7ac-f7c792c4dace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733041030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.733041030
Directory	/workspace/19.spi_device_intercept/latest

Test location	/workspace/coverage/default/19.spi_device_mailbox.1108600434
Short name	T467
Test name
Test status
Simulation time	12039891578 ps
CPU time	64.68 seconds
Started	May 23 02:44:35 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	234452 kb
Host	smart-a80330a6-d400-470e-9788-7ea918d21182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108600434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1108600434
Directory	/workspace/19.spi_device_mailbox/latest

Test location	/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.282311644
Short name	T253
Test name
Test status
Simulation time	92782485 ps
CPU time	2.52 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:40 PM PDT 24
Peak memory	233924 kb
Host	smart-a56e68b8-132f-4768-86ea-7b80a8e2d5d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282311644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap .282311644
Directory	/workspace/19.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/19.spi_device_pass_cmd_filtering.120782697
Short name	T436
Test name
Test status
Simulation time	3875670569 ps
CPU time	5.15 seconds
Started	May 23 02:44:33 PM PDT 24
Finished	May 23 02:44:39 PM PDT 24
Peak memory	218528 kb
Host	smart-13389ffe-1d3b-4e67-b085-e1a448ee2274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120782697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.120782697
Directory	/workspace/19.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/19.spi_device_read_buffer_direct.1658880723
Short name	T826
Test name
Test status
Simulation time	5951045414 ps
CPU time	13.09 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:51 PM PDT 24
Peak memory	218460 kb
Host	smart-0b039755-8a00-4630-a71f-86e56573acea
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1658880723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir ect.1658880723
Directory	/workspace/19.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/19.spi_device_stress_all.3629636780
Short name	T952
Test name
Test status
Simulation time	236775714565 ps
CPU time	542.47 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:53:40 PM PDT 24
Peak memory	255704 kb
Host	smart-5eca0dc5-d0cb-4e9b-8559-ebd563f25959
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629636780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre ss_all.3629636780
Directory	/workspace/19.spi_device_stress_all/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_all.310674866
Short name	T918
Test name
Test status
Simulation time	1477725152 ps
CPU time	7.98 seconds
Started	May 23 02:44:24 PM PDT 24
Finished	May 23 02:44:34 PM PDT 24
Peak memory	216412 kb
Host	smart-bb062036-9900-4acf-906c-7a3887bb842b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310674866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.310674866
Directory	/workspace/19.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2413015092
Short name	T543
Test name
Test status
Simulation time	881247160 ps
CPU time	2.14 seconds
Started	May 23 02:44:22 PM PDT 24
Finished	May 23 02:44:25 PM PDT 24
Peak memory	215980 kb
Host	smart-d34e444e-6a3b-463c-8d65-39b9b1e93e55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413015092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2413015092
Directory	/workspace/19.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_rw.3727384185
Short name	T303
Test name
Test status
Simulation time	46798633 ps
CPU time	1.35 seconds
Started	May 23 02:44:34 PM PDT 24
Finished	May 23 02:44:36 PM PDT 24
Peak memory	216120 kb
Host	smart-25dfa49f-5ed4-441e-aa32-5fffd25c4122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727384185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3727384185
Directory	/workspace/19.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_sts_read.1393440530
Short name	T917
Test name
Test status
Simulation time	52324908 ps
CPU time	0.91 seconds
Started	May 23 02:44:35 PM PDT 24
Finished	May 23 02:44:38 PM PDT 24
Peak memory	205724 kb
Host	smart-c8c9c6fd-2d8a-4ad3-a3bc-03cfc8c47279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393440530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1393440530
Directory	/workspace/19.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/19.spi_device_upload.3211529071
Short name	T3
Test name
Test status
Simulation time	11529481945 ps
CPU time	10.34 seconds
Started	May 23 02:44:34 PM PDT 24
Finished	May 23 02:44:45 PM PDT 24
Peak memory	235316 kb
Host	smart-6b264c62-76c1-4c32-afcc-b7c7b9ad7ad6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211529071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3211529071
Directory	/workspace/19.spi_device_upload/latest

Test location	/workspace/coverage/default/2.spi_device_alert_test.279083702
Short name	T638
Test name
Test status
Simulation time	37564737 ps
CPU time	0.73 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:00 PM PDT 24
Peak memory	205328 kb
Host	smart-92efb994-e709-4283-abf0-0dbf04dd0fb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279083702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.279083702
Directory	/workspace/2.spi_device_alert_test/latest

Test location	/workspace/coverage/default/2.spi_device_cfg_cmd.1467394642
Short name	T816
Test name
Test status
Simulation time	597987278 ps
CPU time	4.24 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:03 PM PDT 24
Peak memory	234156 kb
Host	smart-c3370f84-67fd-4d5c-9b99-eca6fe377a9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467394642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1467394642
Directory	/workspace/2.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/2.spi_device_csb_read.1970343580
Short name	T780
Test name
Test status
Simulation time	61550244 ps
CPU time	0.82 seconds
Started	May 23 02:40:33 PM PDT 24
Finished	May 23 02:40:35 PM PDT 24
Peak memory	206464 kb
Host	smart-ae2f2f77-278c-49e5-85d8-a08ca86b7bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970343580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1970343580
Directory	/workspace/2.spi_device_csb_read/latest

Test location	/workspace/coverage/default/2.spi_device_flash_all.3276991698
Short name	T261
Test name
Test status
Simulation time	132607788521 ps
CPU time	268.72 seconds
Started	May 23 02:40:57 PM PDT 24
Finished	May 23 02:45:27 PM PDT 24
Peak memory	264432 kb
Host	smart-3c33ffc2-005a-4912-83dd-0d691dabb70f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276991698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3276991698
Directory	/workspace/2.spi_device_flash_all/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm.257938320
Short name	T134
Test name
Test status
Simulation time	80216090639 ps
CPU time	213.41 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:44:32 PM PDT 24
Peak memory	257216 kb
Host	smart-5bc8eb65-8626-413d-bf8e-6409baa67eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257938320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.257938320
Directory	/workspace/2.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1795532099
Short name	T871
Test name
Test status
Simulation time	14220919493 ps
CPU time	41.58 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:41 PM PDT 24
Peak memory	255004 kb
Host	smart-896df8cc-7a1e-4704-b8c7-1c3ba795e5eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795532099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle .1795532099
Directory	/workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/2.spi_device_flash_mode.1720381992
Short name	T284
Test name
Test status
Simulation time	870702179 ps
CPU time	16.49 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:16 PM PDT 24
Peak memory	234560 kb
Host	smart-56554bc0-720c-4bcd-947b-f1d28eebe1e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720381992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1720381992
Directory	/workspace/2.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/2.spi_device_intercept.390555361
Short name	T14
Test name
Test status
Simulation time	654943072 ps
CPU time	10.08 seconds
Started	May 23 02:40:45 PM PDT 24
Finished	May 23 02:40:57 PM PDT 24
Peak memory	218552 kb
Host	smart-70a243dc-0263-4b76-b29c-8ca76c01c48d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390555361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.390555361
Directory	/workspace/2.spi_device_intercept/latest

Test location	/workspace/coverage/default/2.spi_device_mailbox.3335866847
Short name	T636
Test name
Test status
Simulation time	400922864 ps
CPU time	5.07 seconds
Started	May 23 02:40:45 PM PDT 24
Finished	May 23 02:40:52 PM PDT 24
Peak memory	218348 kb
Host	smart-e5169c24-c16c-429c-ae87-cfd95097cfb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335866847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3335866847
Directory	/workspace/2.spi_device_mailbox/latest

Test location	/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.831074593
Short name	T250
Test name
Test status
Simulation time	1723658042 ps
CPU time	9.05 seconds
Started	May 23 02:40:47 PM PDT 24
Finished	May 23 02:40:58 PM PDT 24
Peak memory	216996 kb
Host	smart-5e7adcb7-c8d1-4d8c-afc7-5ea9c25b9e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831074593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap. 831074593
Directory	/workspace/2.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2770253055
Short name	T745
Test name
Test status
Simulation time	278286052 ps
CPU time	4.29 seconds
Started	May 23 02:40:45 PM PDT 24
Finished	May 23 02:40:52 PM PDT 24
Peak memory	223180 kb
Host	smart-ba5f27c0-4d11-4632-8965-acd6ac847788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770253055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2770253055
Directory	/workspace/2.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/2.spi_device_read_buffer_direct.456739001
Short name	T326
Test name
Test status
Simulation time	4438731888 ps
CPU time	5.93 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:05 PM PDT 24
Peak memory	222488 kb
Host	smart-e4f16782-f13e-4224-9a78-de6dc18f9475
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=456739001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc t.456739001
Directory	/workspace/2.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/2.spi_device_sec_cm.3852645803
Short name	T75
Test name
Test status
Simulation time	374385074 ps
CPU time	1.24 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:01 PM PDT 24
Peak memory	234636 kb
Host	smart-9539f3b1-a40f-460b-90a8-3e7f279bc7f7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852645803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3852645803
Directory	/workspace/2.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_all.1232857088
Short name	T881
Test name
Test status
Simulation time	6712443011 ps
CPU time	21.08 seconds
Started	May 23 02:40:47 PM PDT 24
Finished	May 23 02:41:11 PM PDT 24
Peak memory	216276 kb
Host	smart-bd07ce8c-cdb3-435c-973f-605f6b9fd128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232857088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1232857088
Directory	/workspace/2.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2086549156
Short name	T351
Test name
Test status
Simulation time	12133151299 ps
CPU time	10.86 seconds
Started	May 23 02:40:44 PM PDT 24
Finished	May 23 02:40:56 PM PDT 24
Peak memory	216212 kb
Host	smart-26851642-d104-419a-a410-fff1a2af0380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086549156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2086549156
Directory	/workspace/2.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_rw.830926482
Short name	T365
Test name
Test status
Simulation time	373514845 ps
CPU time	5.51 seconds
Started	May 23 02:40:46 PM PDT 24
Finished	May 23 02:40:54 PM PDT 24
Peak memory	216232 kb
Host	smart-e2377d7e-3753-4a59-848b-cd4f431a661d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830926482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.830926482
Directory	/workspace/2.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_sts_read.4087927098
Short name	T437
Test name
Test status
Simulation time	79051675 ps
CPU time	0.88 seconds
Started	May 23 02:40:45 PM PDT 24
Finished	May 23 02:40:49 PM PDT 24
Peak memory	205680 kb
Host	smart-0e9ae920-e8d5-47a3-a502-e2ce48698bb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087927098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4087927098
Directory	/workspace/2.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/2.spi_device_upload.2395294584
Short name	T245
Test name
Test status
Simulation time	88712900 ps
CPU time	2.96 seconds
Started	May 23 02:40:47 PM PDT 24
Finished	May 23 02:40:52 PM PDT 24
Peak memory	224360 kb
Host	smart-dc4f1535-8e6b-456f-93cd-0b3b1529d7fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395294584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2395294584
Directory	/workspace/2.spi_device_upload/latest

Test location	/workspace/coverage/default/20.spi_device_alert_test.2291663263
Short name	T59
Test name
Test status
Simulation time	12026524 ps
CPU time	0.71 seconds
Started	May 23 02:44:50 PM PDT 24
Finished	May 23 02:44:52 PM PDT 24
Peak memory	205276 kb
Host	smart-208e3bc2-6cc5-4344-a882-16173905cb58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291663263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test. 2291663263
Directory	/workspace/20.spi_device_alert_test/latest

Test location	/workspace/coverage/default/20.spi_device_cfg_cmd.2210799356
Short name	T753
Test name
Test status
Simulation time	340733664 ps
CPU time	6.52 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:45 PM PDT 24
Peak memory	234340 kb
Host	smart-61defeef-2123-4b8f-baca-970ab0c1c7ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210799356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2210799356
Directory	/workspace/20.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/20.spi_device_csb_read.4178996456
Short name	T422
Test name
Test status
Simulation time	20458869 ps
CPU time	0.81 seconds
Started	May 23 02:44:35 PM PDT 24
Finished	May 23 02:44:37 PM PDT 24
Peak memory	206484 kb
Host	smart-adf4803e-b348-404a-8c73-0b2a2c1795e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178996456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4178996456
Directory	/workspace/20.spi_device_csb_read/latest

Test location	/workspace/coverage/default/20.spi_device_flash_all.1004696189
Short name	T658
Test name
Test status
Simulation time	11453174331 ps
CPU time	80.64 seconds
Started	May 23 02:44:34 PM PDT 24
Finished	May 23 02:45:56 PM PDT 24
Peak memory	264028 kb
Host	smart-bfcff803-d9f8-4ae1-b6a4-26a4e55754a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004696189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1004696189
Directory	/workspace/20.spi_device_flash_all/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2029144093
Short name	T713
Test name
Test status
Simulation time	109390008262 ps
CPU time	175.48 seconds
Started	May 23 02:45:02 PM PDT 24
Finished	May 23 02:47:58 PM PDT 24
Peak memory	256700 kb
Host	smart-6ef0eb34-b11a-4f32-b469-142a5dbf3eb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029144093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl e.2029144093
Directory	/workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/20.spi_device_flash_mode.997760729
Short name	T282
Test name
Test status
Simulation time	973853705 ps
CPU time	7.91 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:44:47 PM PDT 24
Peak memory	232564 kb
Host	smart-168681b0-9992-4796-a63b-64b4e3bfa628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997760729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.997760729
Directory	/workspace/20.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/20.spi_device_intercept.1394944867
Short name	T312
Test name
Test status
Simulation time	3298606647 ps
CPU time	9.62 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:47 PM PDT 24
Peak memory	218356 kb
Host	smart-e0a3f665-5376-465e-b47b-8cd0811b53f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394944867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1394944867
Directory	/workspace/20.spi_device_intercept/latest

Test location	/workspace/coverage/default/20.spi_device_mailbox.1854471492
Short name	T393
Test name
Test status
Simulation time	309462594 ps
CPU time	8.55 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:44:47 PM PDT 24
Peak memory	239540 kb
Host	smart-646f1437-fee6-4826-9929-831d90e7491f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854471492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1854471492
Directory	/workspace/20.spi_device_mailbox/latest

Test location	/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2661443704
Short name	T652
Test name
Test status
Simulation time	76291350 ps
CPU time	2.5 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:40 PM PDT 24
Peak memory	215992 kb
Host	smart-d27aac4f-e0c4-4573-b630-f2f501e808d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661443704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.2661443704
Directory	/workspace/20.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/20.spi_device_pass_cmd_filtering.4241090836
Short name	T193
Test name
Test status
Simulation time	984723772 ps
CPU time	4.84 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:44:43 PM PDT 24
Peak memory	232596 kb
Host	smart-a1126c15-eae3-46f0-af88-ff90c5c07198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241090836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4241090836
Directory	/workspace/20.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/20.spi_device_read_buffer_direct.2943378587
Short name	T954
Test name
Test status
Simulation time	2517652353 ps
CPU time	4.49 seconds
Started	May 23 02:44:34 PM PDT 24
Finished	May 23 02:44:40 PM PDT 24
Peak memory	222444 kb
Host	smart-2b2f046a-0538-4083-af1e-0995bf43cde9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2943378587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.2943378587
Directory	/workspace/20.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_all.272893056
Short name	T470
Test name
Test status
Simulation time	431441212 ps
CPU time	2.52 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:41 PM PDT 24
Peak memory	216404 kb
Host	smart-b9eb25d9-fe04-4692-b3ce-86b43c097661
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272893056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.272893056
Directory	/workspace/20.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.835716605
Short name	T492
Test name
Test status
Simulation time	385607270 ps
CPU time	1.5 seconds
Started	May 23 02:44:36 PM PDT 24
Finished	May 23 02:44:39 PM PDT 24
Peak memory	207812 kb
Host	smart-6123d481-de73-44b0-a4eb-23d5bbb5071b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835716605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.835716605
Directory	/workspace/20.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_rw.3454056678
Short name	T453
Test name
Test status
Simulation time	252892317 ps
CPU time	1.04 seconds
Started	May 23 02:44:40 PM PDT 24
Finished	May 23 02:44:42 PM PDT 24
Peak memory	206984 kb
Host	smart-a07ebf45-0468-4f67-83fd-a0e12c888cbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454056678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3454056678
Directory	/workspace/20.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_sts_read.2259561634
Short name	T342
Test name
Test status
Simulation time	16150427 ps
CPU time	0.7 seconds
Started	May 23 02:44:40 PM PDT 24
Finished	May 23 02:44:41 PM PDT 24
Peak memory	205500 kb
Host	smart-4a496a5f-ef6f-4027-8d23-65ab23a8be07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259561634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2259561634
Directory	/workspace/20.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/20.spi_device_upload.4201275445
Short name	T908
Test name
Test status
Simulation time	271648811 ps
CPU time	6.55 seconds
Started	May 23 02:44:37 PM PDT 24
Finished	May 23 02:44:45 PM PDT 24
Peak memory	233772 kb
Host	smart-26fb7f3a-590f-43db-bd28-1341c88d5344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201275445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4201275445
Directory	/workspace/20.spi_device_upload/latest

Test location	/workspace/coverage/default/21.spi_device_alert_test.2186506402
Short name	T736
Test name
Test status
Simulation time	35419746 ps
CPU time	0.69 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:44:51 PM PDT 24
Peak memory	205284 kb
Host	smart-159f8340-7cf3-404d-9b73-f0a33a5a8d99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186506402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test. 2186506402
Directory	/workspace/21.spi_device_alert_test/latest

Test location	/workspace/coverage/default/21.spi_device_cfg_cmd.520153735
Short name	T348
Test name
Test status
Simulation time	249969034 ps
CPU time	4.4 seconds
Started	May 23 02:44:51 PM PDT 24
Finished	May 23 02:44:56 PM PDT 24
Peak memory	236396 kb
Host	smart-5aa89a5d-60eb-4d8f-92de-8ac58335791d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520153735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.520153735
Directory	/workspace/21.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/21.spi_device_csb_read.3748419158
Short name	T372
Test name
Test status
Simulation time	18564906 ps
CPU time	0.77 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:44:49 PM PDT 24
Peak memory	205440 kb
Host	smart-6690ea66-0617-4784-b812-31fab9c67bb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748419158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3748419158
Directory	/workspace/21.spi_device_csb_read/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm.3967356708
Short name	T135
Test name
Test status
Simulation time	9709827351 ps
CPU time	132.96 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:47:01 PM PDT 24
Peak memory	251004 kb
Host	smart-11140d47-f96e-43a3-9534-563b16085cb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967356708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3967356708
Directory	/workspace/21.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3954903177
Short name	T22
Test name
Test status
Simulation time	43660408473 ps
CPU time	167.54 seconds
Started	May 23 02:45:02 PM PDT 24
Finished	May 23 02:47:50 PM PDT 24
Peak memory	236960 kb
Host	smart-2e1f56ba-8240-4b31-b33d-fe427390049e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954903177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl e.3954903177
Directory	/workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/21.spi_device_flash_mode.3927096702
Short name	T809
Test name
Test status
Simulation time	790135071 ps
CPU time	9.26 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:44:59 PM PDT 24
Peak memory	232584 kb
Host	smart-333bcab3-6b6d-4bb1-a899-06544f9d5982
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3927096702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3927096702
Directory	/workspace/21.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/21.spi_device_intercept.1089369364
Short name	T49
Test name
Test status
Simulation time	7238912844 ps
CPU time	6.37 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:44:55 PM PDT 24
Peak memory	234172 kb
Host	smart-f6eb3769-2786-41d7-bbcd-1c8752a4ea9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089369364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1089369364
Directory	/workspace/21.spi_device_intercept/latest

Test location	/workspace/coverage/default/21.spi_device_mailbox.172625561
Short name	T189
Test name
Test status
Simulation time	2492047279 ps
CPU time	8.8 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:44:58 PM PDT 24
Peak memory	235600 kb
Host	smart-e25e1ba9-6c0f-49aa-9f27-076b57a4a333
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172625561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.172625561
Directory	/workspace/21.spi_device_mailbox/latest

Test location	/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2136860820
Short name	T785
Test name
Test status
Simulation time	259860561 ps
CPU time	5.44 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:44:54 PM PDT 24
Peak memory	232968 kb
Host	smart-5045488c-95f4-41c6-814b-23587b901a5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136860820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa p.2136860820
Directory	/workspace/21.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1767220333
Short name	T937
Test name
Test status
Simulation time	5382315568 ps
CPU time	11.12 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:44:59 PM PDT 24
Peak memory	233520 kb
Host	smart-ee033c31-80f1-4afd-8e38-a6185767edfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767220333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1767220333
Directory	/workspace/21.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/21.spi_device_read_buffer_direct.742324809
Short name	T749
Test name
Test status
Simulation time	1713789383 ps
CPU time	7.78 seconds
Started	May 23 02:45:01 PM PDT 24
Finished	May 23 02:45:09 PM PDT 24
Peak memory	222860 kb
Host	smart-bd307c55-c76e-49a4-b847-23439f19f80f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=742324809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire ct.742324809
Directory	/workspace/21.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/21.spi_device_stress_all.2535507677
Short name	T640
Test name
Test status
Simulation time	87792297797 ps
CPU time	182.31 seconds
Started	May 23 02:45:02 PM PDT 24
Finished	May 23 02:48:05 PM PDT 24
Peak memory	249128 kb
Host	smart-4e177b9b-0872-4b17-92cd-72269bee2162
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535507677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre ss_all.2535507677
Directory	/workspace/21.spi_device_stress_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_all.1556199910
Short name	T942
Test name
Test status
Simulation time	1641753267 ps
CPU time	9.81 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:45:00 PM PDT 24
Peak memory	216160 kb
Host	smart-10f04627-96ef-4a8f-af70-9054816fdd26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556199910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1556199910
Directory	/workspace/21.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2285659573
Short name	T939
Test name
Test status
Simulation time	18700702595 ps
CPU time	11.02 seconds
Started	May 23 02:45:02 PM PDT 24
Finished	May 23 02:45:14 PM PDT 24
Peak memory	216152 kb
Host	smart-10145455-de12-4510-9239-a8cb1a29dc69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285659573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2285659573
Directory	/workspace/21.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_rw.691538164
Short name	T669
Test name
Test status
Simulation time	422953909 ps
CPU time	2.25 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:44:50 PM PDT 24
Peak memory	216208 kb
Host	smart-a27683b5-a5bc-48d3-b99b-12447613349b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691538164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.691538164
Directory	/workspace/21.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_sts_read.2097573643
Short name	T343
Test name
Test status
Simulation time	80106708 ps
CPU time	1 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:44:51 PM PDT 24
Peak memory	205728 kb
Host	smart-60eb9f78-4814-48c5-ab0e-a10f2a229039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097573643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2097573643
Directory	/workspace/21.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/21.spi_device_upload.3025566594
Short name	T694
Test name
Test status
Simulation time	7822064192 ps
CPU time	10.08 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:45:00 PM PDT 24
Peak memory	235788 kb
Host	smart-b546e228-9ca8-4932-9801-f78f936710bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025566594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3025566594
Directory	/workspace/21.spi_device_upload/latest

Test location	/workspace/coverage/default/22.spi_device_alert_test.3418623649
Short name	T443
Test name
Test status
Simulation time	12801220 ps
CPU time	0.72 seconds
Started	May 23 02:45:08 PM PDT 24
Finished	May 23 02:45:10 PM PDT 24
Peak memory	204716 kb
Host	smart-43299cea-c930-4a31-a25f-e97f3a0c5c3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418623649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 3418623649
Directory	/workspace/22.spi_device_alert_test/latest

Test location	/workspace/coverage/default/22.spi_device_csb_read.161268795
Short name	T626
Test name
Test status
Simulation time	41979321 ps
CPU time	0.82 seconds
Started	May 23 02:45:01 PM PDT 24
Finished	May 23 02:45:03 PM PDT 24
Peak memory	206500 kb
Host	smart-91fe86a5-3ec6-4f33-b0a4-0ed41dd4449b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161268795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.161268795
Directory	/workspace/22.spi_device_csb_read/latest

Test location	/workspace/coverage/default/22.spi_device_flash_all.3883715992
Short name	T178
Test name
Test status
Simulation time	3132736211 ps
CPU time	31.73 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:45:22 PM PDT 24
Peak memory	240808 kb
Host	smart-3fa4825b-3b73-4e03-bd23-76b4f9c4817e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883715992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3883715992
Directory	/workspace/22.spi_device_flash_all/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm.1111621926
Short name	T635
Test name
Test status
Simulation time	11803848090 ps
CPU time	67.48 seconds
Started	May 23 02:45:08 PM PDT 24
Finished	May 23 02:46:17 PM PDT 24
Peak memory	248992 kb
Host	smart-9b8bb93d-6d72-4da1-bcbb-2c66230da627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111621926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1111621926
Directory	/workspace/22.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1250769752
Short name	T909
Test name
Test status
Simulation time	24019667345 ps
CPU time	215.71 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	253944 kb
Host	smart-84fb3d01-5f39-450e-a99a-350917dc1ee3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250769752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl e.1250769752
Directory	/workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/22.spi_device_flash_mode.4009298223
Short name	T519
Test name
Test status
Simulation time	632168812 ps
CPU time	2.89 seconds
Started	May 23 02:44:50 PM PDT 24
Finished	May 23 02:44:54 PM PDT 24
Peak memory	224388 kb
Host	smart-0d3bf3c7-0a21-45b4-a353-006ddcd54b2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009298223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4009298223
Directory	/workspace/22.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/22.spi_device_intercept.3171593934
Short name	T670
Test name
Test status
Simulation time	37331917 ps
CPU time	2.71 seconds
Started	May 23 02:44:48 PM PDT 24
Finished	May 23 02:44:52 PM PDT 24
Peak memory	232588 kb
Host	smart-2efeb886-c462-42f2-bc65-b3da6e67c3ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171593934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3171593934
Directory	/workspace/22.spi_device_intercept/latest

Test location	/workspace/coverage/default/22.spi_device_mailbox.2167523764
Short name	T509
Test name
Test status
Simulation time	7233450805 ps
CPU time	61.17 seconds
Started	May 23 02:45:01 PM PDT 24
Finished	May 23 02:46:04 PM PDT 24
Peak memory	239372 kb
Host	smart-18d04444-26ff-40ca-a7ad-1ee3f4f9ec41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167523764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2167523764
Directory	/workspace/22.spi_device_mailbox/latest

Test location	/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1755570744
Short name	T277
Test name
Test status
Simulation time	775361889 ps
CPU time	3.78 seconds
Started	May 23 02:44:47 PM PDT 24
Finished	May 23 02:44:52 PM PDT 24
Peak memory	218252 kb
Host	smart-204d3c4b-447b-40b3-85bf-9288b6e74772
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755570744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa p.1755570744
Directory	/workspace/22.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/22.spi_device_pass_cmd_filtering.2385970578
Short name	T414
Test name
Test status
Simulation time	2328302422 ps
CPU time	16.19 seconds
Started	May 23 02:45:02 PM PDT 24
Finished	May 23 02:45:19 PM PDT 24
Peak memory	232212 kb
Host	smart-c2db54f5-2381-4a07-8779-46f2cb844f06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385970578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2385970578
Directory	/workspace/22.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/22.spi_device_read_buffer_direct.3113964493
Short name	T915
Test name
Test status
Simulation time	1320513912 ps
CPU time	5.78 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:44:56 PM PDT 24
Peak memory	219840 kb
Host	smart-642e168a-3437-497b-b123-e71e98ea572b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3113964493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir ect.3113964493
Directory	/workspace/22.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_all.215555155
Short name	T506
Test name
Test status
Simulation time	1034993643 ps
CPU time	13.7 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:45:04 PM PDT 24
Peak memory	216172 kb
Host	smart-895b45f5-cd51-430c-adf0-03ddabef620c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215555155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.215555155
Directory	/workspace/22.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_rw.1708399613
Short name	T374
Test name
Test status
Simulation time	12662244 ps
CPU time	0.69 seconds
Started	May 23 02:44:50 PM PDT 24
Finished	May 23 02:44:52 PM PDT 24
Peak memory	205428 kb
Host	smart-0a1c47df-995c-44c7-8033-6b2511f66267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708399613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1708399613
Directory	/workspace/22.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_sts_read.3990518729
Short name	T900
Test name
Test status
Simulation time	146181004 ps
CPU time	0.83 seconds
Started	May 23 02:44:49 PM PDT 24
Finished	May 23 02:44:51 PM PDT 24
Peak memory	205704 kb
Host	smart-5b034f5c-9544-4483-91b9-e18fab7801eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990518729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3990518729
Directory	/workspace/22.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/22.spi_device_upload.4247357939
Short name	T608
Test name
Test status
Simulation time	499486672 ps
CPU time	4.13 seconds
Started	May 23 02:44:46 PM PDT 24
Finished	May 23 02:44:52 PM PDT 24
Peak memory	218832 kb
Host	smart-f48cc389-7ceb-4566-8955-573667cab4f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247357939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4247357939
Directory	/workspace/22.spi_device_upload/latest

Test location	/workspace/coverage/default/23.spi_device_alert_test.3968727571
Short name	T898
Test name
Test status
Simulation time	21247751 ps
CPU time	0.73 seconds
Started	May 23 02:45:08 PM PDT 24
Finished	May 23 02:45:10 PM PDT 24
Peak memory	204532 kb
Host	smart-ea61cb9f-a7ae-4b8b-9d1a-afb7b9127404
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968727571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test. 3968727571
Directory	/workspace/23.spi_device_alert_test/latest

Test location	/workspace/coverage/default/23.spi_device_cfg_cmd.548762446
Short name	T537
Test name
Test status
Simulation time	167177681 ps
CPU time	4.57 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:11 PM PDT 24
Peak memory	235140 kb
Host	smart-a0aacbcd-6af1-44db-b118-832e0791086f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548762446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.548762446
Directory	/workspace/23.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/23.spi_device_csb_read.348982406
Short name	T574
Test name
Test status
Simulation time	24339282 ps
CPU time	0.79 seconds
Started	May 23 02:45:05 PM PDT 24
Finished	May 23 02:45:07 PM PDT 24
Peak memory	206852 kb
Host	smart-e714cfad-a9f1-4ab3-bdb2-68b52ab9c827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348982406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.348982406
Directory	/workspace/23.spi_device_csb_read/latest

Test location	/workspace/coverage/default/23.spi_device_flash_all.1356548509
Short name	T251
Test name
Test status
Simulation time	4260682159 ps
CPU time	10.03 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:45:18 PM PDT 24
Peak memory	249032 kb
Host	smart-3f2762b9-6c36-45f7-a46f-865c9c58a7e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356548509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1356548509
Directory	/workspace/23.spi_device_flash_all/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm.2113576131
Short name	T744
Test name
Test status
Simulation time	2847276706 ps
CPU time	38.7 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:45:46 PM PDT 24
Peak memory	249072 kb
Host	smart-93bf03bf-96d1-474e-ab6a-c13facf98250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113576131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2113576131
Directory	/workspace/23.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2997403428
Short name	T31
Test name
Test status
Simulation time	67519518725 ps
CPU time	461.56 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:52:48 PM PDT 24
Peak memory	255228 kb
Host	smart-d0804f3a-0bd6-41cc-8dbb-ebc674a3a90d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997403428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl e.2997403428
Directory	/workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/23.spi_device_flash_mode.4007900278
Short name	T335
Test name
Test status
Simulation time	839669636 ps
CPU time	6.68 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:14 PM PDT 24
Peak memory	232596 kb
Host	smart-308d81ad-ce92-4c13-9245-98518f49b786
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007900278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4007900278
Directory	/workspace/23.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/23.spi_device_intercept.3321225970
Short name	T671
Test name
Test status
Simulation time	942947160 ps
CPU time	9.1 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:16 PM PDT 24
Peak memory	234368 kb
Host	smart-5cb19c8d-f5aa-46b0-8b9a-1752b60df873
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321225970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3321225970
Directory	/workspace/23.spi_device_intercept/latest

Test location	/workspace/coverage/default/23.spi_device_mailbox.3221118415
Short name	T695
Test name
Test status
Simulation time	2230840154 ps
CPU time	12.83 seconds
Started	May 23 02:45:05 PM PDT 24
Finished	May 23 02:45:19 PM PDT 24
Peak memory	240872 kb
Host	smart-bb6eb1fd-c958-4d3e-9e7d-2341909acdde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221118415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3221118415
Directory	/workspace/23.spi_device_mailbox/latest

Test location	/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3067964687
Short name	T271
Test name
Test status
Simulation time	7781832585 ps
CPU time	7.96 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:15 PM PDT 24
Peak memory	237768 kb
Host	smart-df964c96-150a-424e-97e2-49c84142c10c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067964687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa p.3067964687
Directory	/workspace/23.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/23.spi_device_pass_cmd_filtering.92778161
Short name	T403
Test name
Test status
Simulation time	9220169079 ps
CPU time	24.08 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:45:33 PM PDT 24
Peak memory	236380 kb
Host	smart-5547d193-eb67-4194-b0ba-3972045ef901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92778161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.92778161
Directory	/workspace/23.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/23.spi_device_read_buffer_direct.962454263
Short name	T399
Test name
Test status
Simulation time	3513603259 ps
CPU time	5.65 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:13 PM PDT 24
Peak memory	218624 kb
Host	smart-1f120550-4101-405d-a302-6a84a77fa652
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=962454263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire ct.962454263
Directory	/workspace/23.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/23.spi_device_stress_all.3681621485
Short name	T263
Test name
Test status
Simulation time	10417891092 ps
CPU time	45.96 seconds
Started	May 23 02:45:15 PM PDT 24
Finished	May 23 02:46:01 PM PDT 24
Peak memory	240880 kb
Host	smart-0c44d57e-4099-4905-8508-23cbcdc0caa2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681621485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre ss_all.3681621485
Directory	/workspace/23.spi_device_stress_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_all.2612228384
Short name	T321
Test name
Test status
Simulation time	822150742 ps
CPU time	5.73 seconds
Started	May 23 02:45:06 PM PDT 24
Finished	May 23 02:45:13 PM PDT 24
Peak memory	216180 kb
Host	smart-96f7c224-34a9-421b-b010-37aa6a23708b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612228384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2612228384
Directory	/workspace/23.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.960379790
Short name	T637
Test name
Test status
Simulation time	461299934 ps
CPU time	1.74 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:45:10 PM PDT 24
Peak memory	207780 kb
Host	smart-dc27f58e-dc87-43d9-8517-723111d7952e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960379790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.960379790
Directory	/workspace/23.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_rw.1910020607
Short name	T373
Test name
Test status
Simulation time	479304016 ps
CPU time	9.54 seconds
Started	May 23 02:45:08 PM PDT 24
Finished	May 23 02:45:19 PM PDT 24
Peak memory	216096 kb
Host	smart-5164c404-a2ba-4027-ae50-b25dd38bcc34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910020607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1910020607
Directory	/workspace/23.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_sts_read.660194220
Short name	T129
Test name
Test status
Simulation time	342871230 ps
CPU time	1.04 seconds
Started	May 23 02:45:07 PM PDT 24
Finished	May 23 02:45:09 PM PDT 24
Peak memory	205728 kb
Host	smart-81acaa58-7044-4cd9-9fd7-83b0ae7b92cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660194220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.660194220
Directory	/workspace/23.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/23.spi_device_upload.380468181
Short name	T642
Test name
Test status
Simulation time	463093253 ps
CPU time	5.57 seconds
Started	May 23 02:45:04 PM PDT 24
Finished	May 23 02:45:11 PM PDT 24
Peak memory	223236 kb
Host	smart-9a00ed69-2021-491b-b588-ce5859907534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380468181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.380468181
Directory	/workspace/23.spi_device_upload/latest

Test location	/workspace/coverage/default/24.spi_device_alert_test.580873846
Short name	T677
Test name
Test status
Simulation time	45127610 ps
CPU time	0.75 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	204760 kb
Host	smart-98ae3a6a-0249-4a76-89d4-327209aaa16b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580873846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.580873846
Directory	/workspace/24.spi_device_alert_test/latest

Test location	/workspace/coverage/default/24.spi_device_cfg_cmd.2352493506
Short name	T844
Test name
Test status
Simulation time	3141049509 ps
CPU time	8.88 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:32 PM PDT 24
Peak memory	219504 kb
Host	smart-c67b4142-3b15-4814-bae1-6266189a2b16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352493506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2352493506
Directory	/workspace/24.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/24.spi_device_csb_read.1042744535
Short name	T823
Test name
Test status
Simulation time	33719456 ps
CPU time	0.8 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:24 PM PDT 24
Peak memory	206492 kb
Host	smart-087a4ec7-21d1-4182-9f73-d3223753a4fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042744535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1042744535
Directory	/workspace/24.spi_device_csb_read/latest

Test location	/workspace/coverage/default/24.spi_device_flash_all.2388031305
Short name	T703
Test name
Test status
Simulation time	14156649 ps
CPU time	0.76 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	215840 kb
Host	smart-cc44f84f-ed7f-4c61-9dd4-06c23f9abfaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388031305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2388031305
Directory	/workspace/24.spi_device_flash_all/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm.3367538204
Short name	T618
Test name
Test status
Simulation time	3341688215 ps
CPU time	70.17 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:46:33 PM PDT 24
Peak memory	249100 kb
Host	smart-5fc51a08-1271-4f01-9ff4-705821124e29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367538204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3367538204
Directory	/workspace/24.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1048077817
Short name	T38
Test name
Test status
Simulation time	78920453070 ps
CPU time	208.59 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:48:52 PM PDT 24
Peak memory	249108 kb
Host	smart-4106e6cd-2e0c-484a-9d80-85d005a0362d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048077817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl e.1048077817
Directory	/workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/24.spi_device_intercept.3609986088
Short name	T641
Test name
Test status
Simulation time	182295047 ps
CPU time	4.03 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:27 PM PDT 24
Peak memory	233316 kb
Host	smart-c4374d9a-4032-4034-b5ac-de9fe3cf60fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609986088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3609986088
Directory	/workspace/24.spi_device_intercept/latest

Test location	/workspace/coverage/default/24.spi_device_mailbox.2626585851
Short name	T914
Test name
Test status
Simulation time	2109920367 ps
CPU time	12.4 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:36 PM PDT 24
Peak memory	245956 kb
Host	smart-5eefc2e0-65cf-441e-9f33-cd326c46a9e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626585851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2626585851
Directory	/workspace/24.spi_device_mailbox/latest

Test location	/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.429681745
Short name	T490
Test name
Test status
Simulation time	78689421 ps
CPU time	2.53 seconds
Started	May 23 02:45:21 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	232608 kb
Host	smart-35f5f187-81f3-43ce-ae06-9cdaefcb8574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429681745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap .429681745
Directory	/workspace/24.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/24.spi_device_pass_cmd_filtering.3395806842
Short name	T156
Test name
Test status
Simulation time	13209510705 ps
CPU time	16.4 seconds
Started	May 23 02:45:21 PM PDT 24
Finished	May 23 02:45:38 PM PDT 24
Peak memory	249776 kb
Host	smart-9cfd7456-80ab-4680-8ba7-925d72071064
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395806842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3395806842
Directory	/workspace/24.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/24.spi_device_read_buffer_direct.2827342841
Short name	T946
Test name
Test status
Simulation time	234719912 ps
CPU time	4.49 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:29 PM PDT 24
Peak memory	218860 kb
Host	smart-c61b6bf6-abfd-4a7f-a131-54cc185bc004
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2827342841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir ect.2827342841
Directory	/workspace/24.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/24.spi_device_stress_all.1644993743
Short name	T912
Test name
Test status
Simulation time	59237359144 ps
CPU time	319 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:50:43 PM PDT 24
Peak memory	256216 kb
Host	smart-d1093417-807e-42d2-b37c-324d27585324
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644993743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre ss_all.1644993743
Directory	/workspace/24.spi_device_stress_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_all.3144184989
Short name	T44
Test name
Test status
Simulation time	14612475670 ps
CPU time	30.5 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:53 PM PDT 24
Peak memory	216268 kb
Host	smart-4684350b-4f36-4b16-8a34-2e4f24c217da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144184989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3144184989
Directory	/workspace/24.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2490254312
Short name	T489
Test name
Test status
Simulation time	145942876 ps
CPU time	1.36 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:26 PM PDT 24
Peak memory	207760 kb
Host	smart-43747d19-976e-4488-bf5c-d0027933cf30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490254312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2490254312
Directory	/workspace/24.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_rw.2752111282
Short name	T293
Test name
Test status
Simulation time	542200880 ps
CPU time	2.26 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	216212 kb
Host	smart-984c6fee-8456-4c71-b4dd-c2d48725dbd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752111282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2752111282
Directory	/workspace/24.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_sts_read.2024895558
Short name	T586
Test name
Test status
Simulation time	61387287 ps
CPU time	0.77 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:26 PM PDT 24
Peak memory	205696 kb
Host	smart-5dffe9b8-bc16-42f1-b926-eb68a6a310cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024895558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2024895558
Directory	/workspace/24.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/24.spi_device_upload.535357108
Short name	T235
Test name
Test status
Simulation time	2276293361 ps
CPU time	9.94 seconds
Started	May 23 02:45:24 PM PDT 24
Finished	May 23 02:45:35 PM PDT 24
Peak memory	233744 kb
Host	smart-ce7a02ce-0d63-4e06-8416-469bdb75c3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535357108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.535357108
Directory	/workspace/24.spi_device_upload/latest

Test location	/workspace/coverage/default/25.spi_device_alert_test.2042036303
Short name	T938
Test name
Test status
Simulation time	45513096 ps
CPU time	0.77 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:36 PM PDT 24
Peak memory	205692 kb
Host	smart-10327aab-70e8-4e90-9785-dfb291f2c8ce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042036303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 2042036303
Directory	/workspace/25.spi_device_alert_test/latest

Test location	/workspace/coverage/default/25.spi_device_cfg_cmd.657376522
Short name	T232
Test name
Test status
Simulation time	4679738918 ps
CPU time	12.11 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:48 PM PDT 24
Peak memory	234220 kb
Host	smart-e0f96752-e342-4c58-9779-c4a02b44a1bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657376522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.657376522
Directory	/workspace/25.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/25.spi_device_csb_read.1764556190
Short name	T370
Test name
Test status
Simulation time	20036268 ps
CPU time	0.79 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	206496 kb
Host	smart-24c20919-36b0-4198-bec1-ded872c51264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764556190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1764556190
Directory	/workspace/25.spi_device_csb_read/latest

Test location	/workspace/coverage/default/25.spi_device_flash_all.505406174
Short name	T207
Test name
Test status
Simulation time	44434857636 ps
CPU time	145.74 seconds
Started	May 23 02:45:38 PM PDT 24
Finished	May 23 02:48:05 PM PDT 24
Peak memory	239732 kb
Host	smart-add0d600-6103-4b8d-885e-ede95c6f44b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505406174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.505406174
Directory	/workspace/25.spi_device_flash_all/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3212283209
Short name	T82
Test name
Test status
Simulation time	13406840069 ps
CPU time	109.52 seconds
Started	May 23 02:45:39 PM PDT 24
Finished	May 23 02:47:29 PM PDT 24
Peak memory	240816 kb
Host	smart-a5bdb6ac-b38b-43c9-b5a8-761d7cf16e91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212283209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl e.3212283209
Directory	/workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/25.spi_device_flash_mode.214907489
Short name	T427
Test name
Test status
Simulation time	1787711381 ps
CPU time	10.9 seconds
Started	May 23 02:45:42 PM PDT 24
Finished	May 23 02:45:54 PM PDT 24
Peak memory	238364 kb
Host	smart-02da1ba7-02a8-4b56-a1d9-8cec97d6ecee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214907489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.214907489
Directory	/workspace/25.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/25.spi_device_intercept.2063252850
Short name	T58
Test name
Test status
Simulation time	15743263396 ps
CPU time	10.66 seconds
Started	May 23 02:45:22 PM PDT 24
Finished	May 23 02:45:34 PM PDT 24
Peak memory	233136 kb
Host	smart-7c0a36f3-b766-4f87-a9d6-b45c9e89bfc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063252850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2063252850
Directory	/workspace/25.spi_device_intercept/latest

Test location	/workspace/coverage/default/25.spi_device_mailbox.95864060
Short name	T239
Test name
Test status
Simulation time	946950031 ps
CPU time	17.29 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	236952 kb
Host	smart-8115e526-e420-4575-aa55-b1912d568542
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95864060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.95864060
Directory	/workspace/25.spi_device_mailbox/latest

Test location	/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1163206738
Short name	T265
Test name
Test status
Simulation time	3698193162 ps
CPU time	7.07 seconds
Started	May 23 02:45:25 PM PDT 24
Finished	May 23 02:45:33 PM PDT 24
Peak memory	233168 kb
Host	smart-1b98a939-605b-4dc0-9ba5-7aade60ca5f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163206738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa p.1163206738
Directory	/workspace/25.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/25.spi_device_pass_cmd_filtering.3015398611
Short name	T208
Test name
Test status
Simulation time	25175825387 ps
CPU time	20.18 seconds
Started	May 23 02:45:21 PM PDT 24
Finished	May 23 02:45:42 PM PDT 24
Peak memory	233808 kb
Host	smart-1b021597-9af9-4f72-8c9f-552189b7371b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015398611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3015398611
Directory	/workspace/25.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/25.spi_device_read_buffer_direct.2593435236
Short name	T932
Test name
Test status
Simulation time	295541537 ps
CPU time	3.84 seconds
Started	May 23 02:45:34 PM PDT 24
Finished	May 23 02:45:38 PM PDT 24
Peak memory	218628 kb
Host	smart-915f9d9e-5ec0-4d5a-a339-3646db996915
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2593435236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir ect.2593435236
Directory	/workspace/25.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_all.67736068
Short name	T906
Test name
Test status
Simulation time	6346191496 ps
CPU time	22.21 seconds
Started	May 23 02:45:21 PM PDT 24
Finished	May 23 02:45:44 PM PDT 24
Peak memory	216244 kb
Host	smart-21b27bca-f3ae-42ae-b65d-5a20b1b683df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67736068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.67736068
Directory	/workspace/25.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.481256210
Short name	T318
Test name
Test status
Simulation time	1380121967 ps
CPU time	6.43 seconds
Started	May 23 02:45:23 PM PDT 24
Finished	May 23 02:45:30 PM PDT 24
Peak memory	216084 kb
Host	smart-29b36f59-9d41-4f56-9df7-ec8d3f1e7758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481256210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.481256210
Directory	/workspace/25.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_rw.1796413373
Short name	T928
Test name
Test status
Simulation time	166213181 ps
CPU time	2.95 seconds
Started	May 23 02:45:21 PM PDT 24
Finished	May 23 02:45:25 PM PDT 24
Peak memory	216128 kb
Host	smart-4a9c932d-9faf-49c2-830e-518eaa4d6ddb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796413373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1796413373
Directory	/workspace/25.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_sts_read.3404388356
Short name	T7
Test name
Test status
Simulation time	133600703 ps
CPU time	0.79 seconds
Started	May 23 02:45:20 PM PDT 24
Finished	May 23 02:45:22 PM PDT 24
Peak memory	205712 kb
Host	smart-048172ed-fad7-4b98-9650-015ea6ac4429
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404388356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3404388356
Directory	/workspace/25.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/25.spi_device_upload.2070188382
Short name	T787
Test name
Test status
Simulation time	794151175 ps
CPU time	4.87 seconds
Started	May 23 02:45:41 PM PDT 24
Finished	May 23 02:45:46 PM PDT 24
Peak memory	233956 kb
Host	smart-b58744dd-faab-44c0-89c2-8afcb18e5572
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070188382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2070188382
Directory	/workspace/25.spi_device_upload/latest

Test location	/workspace/coverage/default/26.spi_device_alert_test.4262262965
Short name	T919
Test name
Test status
Simulation time	15060841 ps
CPU time	0.75 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:39 PM PDT 24
Peak memory	205272 kb
Host	smart-9a695fdd-1a7d-44b7-b1a9-2468a6437dd8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262262965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test. 4262262965
Directory	/workspace/26.spi_device_alert_test/latest

Test location	/workspace/coverage/default/26.spi_device_cfg_cmd.4139320914
Short name	T92
Test name
Test status
Simulation time	1325899340 ps
CPU time	14.77 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:52 PM PDT 24
Peak memory	234280 kb
Host	smart-68f95528-90f6-4637-804a-35248d9cb5cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139320914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4139320914
Directory	/workspace/26.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/26.spi_device_csb_read.3783640752
Short name	T66
Test name
Test status
Simulation time	102132195 ps
CPU time	0.78 seconds
Started	May 23 02:45:39 PM PDT 24
Finished	May 23 02:45:40 PM PDT 24
Peak memory	206492 kb
Host	smart-4f8645da-778d-4745-9445-bbd6c488d177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783640752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3783640752
Directory	/workspace/26.spi_device_csb_read/latest

Test location	/workspace/coverage/default/26.spi_device_flash_all.1889552826
Short name	T735
Test name
Test status
Simulation time	27209992 ps
CPU time	0.79 seconds
Started	May 23 02:45:36 PM PDT 24
Finished	May 23 02:45:38 PM PDT 24
Peak memory	215852 kb
Host	smart-3b80500e-8e94-4cd2-aa06-d85b9c02a805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889552826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1889552826
Directory	/workspace/26.spi_device_flash_all/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm.1719856140
Short name	T137
Test name
Test status
Simulation time	23151273125 ps
CPU time	84.17 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:47:02 PM PDT 24
Peak memory	256324 kb
Host	smart-9307e036-29c7-42b1-b7d7-52ceec7ab9c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719856140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1719856140
Directory	/workspace/26.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2345454887
Short name	T508
Test name
Test status
Simulation time	125050087597 ps
CPU time	278.12 seconds
Started	May 23 02:45:38 PM PDT 24
Finished	May 23 02:50:17 PM PDT 24
Peak memory	251616 kb
Host	smart-bbe4e292-a63f-43ed-9d0f-1c65824d34d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345454887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl e.2345454887
Directory	/workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/26.spi_device_flash_mode.1094688137
Short name	T614
Test name
Test status
Simulation time	1015457789 ps
CPU time	16.47 seconds
Started	May 23 02:45:41 PM PDT 24
Finished	May 23 02:45:58 PM PDT 24
Peak memory	233656 kb
Host	smart-2d224d82-e9e4-4e21-a913-eb91758af991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094688137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1094688137
Directory	/workspace/26.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/26.spi_device_intercept.2620389654
Short name	T512
Test name
Test status
Simulation time	3187085500 ps
CPU time	10.23 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:46 PM PDT 24
Peak memory	233852 kb
Host	smart-582791fd-4cf3-4674-956a-fa36e6672d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620389654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2620389654
Directory	/workspace/26.spi_device_intercept/latest

Test location	/workspace/coverage/default/26.spi_device_mailbox.2340247678
Short name	T420
Test name
Test status
Simulation time	1529487539 ps
CPU time	5.94 seconds
Started	May 23 02:45:39 PM PDT 24
Finished	May 23 02:45:46 PM PDT 24
Peak memory	224404 kb
Host	smart-4415c5d5-c572-4cde-a1b6-30e4b4122e77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340247678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2340247678
Directory	/workspace/26.spi_device_mailbox/latest

Test location	/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.322350272
Short name	T474
Test name
Test status
Simulation time	651659554 ps
CPU time	3.73 seconds
Started	May 23 02:45:40 PM PDT 24
Finished	May 23 02:45:44 PM PDT 24
Peak memory	233416 kb
Host	smart-3f436ede-98fd-4ff6-b2ae-42ced5232bc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322350272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap .322350272
Directory	/workspace/26.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/26.spi_device_pass_cmd_filtering.4265414331
Short name	T210
Test name
Test status
Simulation time	3516360040 ps
CPU time	8.31 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:43 PM PDT 24
Peak memory	236012 kb
Host	smart-666ece1d-1194-4191-ad6d-a186528d3217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265414331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4265414331
Directory	/workspace/26.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/26.spi_device_read_buffer_direct.2150045574
Short name	T888
Test name
Test status
Simulation time	327353565 ps
CPU time	4.45 seconds
Started	May 23 02:45:34 PM PDT 24
Finished	May 23 02:45:39 PM PDT 24
Peak memory	219008 kb
Host	smart-81ba29e3-f980-4428-a925-d855e1e1c92e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2150045574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir ect.2150045574
Directory	/workspace/26.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/26.spi_device_stress_all.3334825000
Short name	T153
Test name
Test status
Simulation time	5348578768 ps
CPU time	43.5 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	240904 kb
Host	smart-560e2693-f3a4-4df9-92db-56ce51d7d5e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334825000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre ss_all.3334825000
Directory	/workspace/26.spi_device_stress_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_all.1879050293
Short name	T528
Test name
Test status
Simulation time	6392734961 ps
CPU time	8.13 seconds
Started	May 23 02:45:36 PM PDT 24
Finished	May 23 02:45:45 PM PDT 24
Peak memory	216252 kb
Host	smart-8b017183-a271-49fa-862f-e5560ae5febb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879050293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1879050293
Directory	/workspace/26.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1933080821
Short name	T397
Test name
Test status
Simulation time	10524530523 ps
CPU time	9.37 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:46 PM PDT 24
Peak memory	216184 kb
Host	smart-4e5c86b8-7480-4bf2-94d6-32ccd5eb0afb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933080821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1933080821
Directory	/workspace/26.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_rw.4204784587
Short name	T26
Test name
Test status
Simulation time	145930801 ps
CPU time	4.09 seconds
Started	May 23 02:45:40 PM PDT 24
Finished	May 23 02:45:45 PM PDT 24
Peak memory	216184 kb
Host	smart-5fdfb42d-7fa0-4d72-8df4-544deeb9677a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204784587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4204784587
Directory	/workspace/26.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_sts_read.2497951656
Short name	T429
Test name
Test status
Simulation time	204695366 ps
CPU time	0.79 seconds
Started	May 23 02:45:35 PM PDT 24
Finished	May 23 02:45:37 PM PDT 24
Peak memory	205696 kb
Host	smart-bd2206dc-314f-4d4b-bae9-ebb25b905520
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497951656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2497951656
Directory	/workspace/26.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/26.spi_device_upload.435526238
Short name	T533
Test name
Test status
Simulation time	10674691322 ps
CPU time	5.76 seconds
Started	May 23 02:45:40 PM PDT 24
Finished	May 23 02:45:47 PM PDT 24
Peak memory	216216 kb
Host	smart-578246df-7467-4d65-8e13-575b134edfef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435526238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.435526238
Directory	/workspace/26.spi_device_upload/latest

Test location	/workspace/coverage/default/27.spi_device_alert_test.3164476851
Short name	T580
Test name
Test status
Simulation time	27054944 ps
CPU time	0.71 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:45:51 PM PDT 24
Peak memory	205292 kb
Host	smart-9e2e808b-8874-4841-9526-d05de6657aeb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164476851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test. 3164476851
Directory	/workspace/27.spi_device_alert_test/latest

Test location	/workspace/coverage/default/27.spi_device_cfg_cmd.96161464
Short name	T244
Test name
Test status
Simulation time	1350415572 ps
CPU time	4.94 seconds
Started	May 23 02:45:48 PM PDT 24
Finished	May 23 02:45:55 PM PDT 24
Peak memory	218528 kb
Host	smart-f6bc8c41-7c7f-442c-b1bc-9c4a4afea9d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96161464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.96161464
Directory	/workspace/27.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/27.spi_device_csb_read.3209587306
Short name	T891
Test name
Test status
Simulation time	13898098 ps
CPU time	0.83 seconds
Started	May 23 02:45:36 PM PDT 24
Finished	May 23 02:45:38 PM PDT 24
Peak memory	206784 kb
Host	smart-056a190d-7538-427e-b41a-c734116cc515
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209587306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3209587306
Directory	/workspace/27.spi_device_csb_read/latest

Test location	/workspace/coverage/default/27.spi_device_flash_all.816130740
Short name	T649
Test name
Test status
Simulation time	60961338471 ps
CPU time	82.97 seconds
Started	May 23 02:45:48 PM PDT 24
Finished	May 23 02:47:12 PM PDT 24
Peak memory	249088 kb
Host	smart-aad69828-ce66-4e5a-8ed3-cdf22823431b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816130740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.816130740
Directory	/workspace/27.spi_device_flash_all/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm.1418421949
Short name	T565
Test name
Test status
Simulation time	428035542 ps
CPU time	7.44 seconds
Started	May 23 02:45:55 PM PDT 24
Finished	May 23 02:46:03 PM PDT 24
Peak memory	217496 kb
Host	smart-d1b4eb27-f5aa-473c-8a75-4888bd3f4871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418421949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1418421949
Directory	/workspace/27.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3829655508
Short name	T200
Test name
Test status
Simulation time	12388535678 ps
CPU time	73.83 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:47:05 PM PDT 24
Peak memory	224516 kb
Host	smart-39bb7d8c-03a0-47f0-9596-6ace04f51224
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829655508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl e.3829655508
Directory	/workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/27.spi_device_flash_mode.2670414289
Short name	T584
Test name
Test status
Simulation time	251944037 ps
CPU time	8.71 seconds
Started	May 23 02:46:00 PM PDT 24
Finished	May 23 02:46:11 PM PDT 24
Peak memory	240504 kb
Host	smart-73e170c9-3dda-49f6-81f7-d45d8330f8ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670414289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2670414289
Directory	/workspace/27.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/27.spi_device_intercept.1427227213
Short name	T941
Test name
Test status
Simulation time	2168358976 ps
CPU time	19.07 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:57 PM PDT 24
Peak memory	218720 kb
Host	smart-74ac383b-c9b0-4a4f-aa3b-0db05a05f14c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427227213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1427227213
Directory	/workspace/27.spi_device_intercept/latest

Test location	/workspace/coverage/default/27.spi_device_mailbox.1206823114
Short name	T764
Test name
Test status
Simulation time	5285612942 ps
CPU time	16.87 seconds
Started	May 23 02:45:41 PM PDT 24
Finished	May 23 02:45:58 PM PDT 24
Peak memory	236060 kb
Host	smart-7cce91d7-6f59-41e6-b476-d4f603099a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206823114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1206823114
Directory	/workspace/27.spi_device_mailbox/latest

Test location	/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2103209989
Short name	T674
Test name
Test status
Simulation time	32219917 ps
CPU time	2.82 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	220892 kb
Host	smart-1dc3880c-4b98-4504-ab37-fb7250c9efa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103209989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.2103209989
Directory	/workspace/27.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/27.spi_device_pass_cmd_filtering.3606022239
Short name	T840
Test name
Test status
Simulation time	101315338 ps
CPU time	2.51 seconds
Started	May 23 02:45:38 PM PDT 24
Finished	May 23 02:45:41 PM PDT 24
Peak memory	232572 kb
Host	smart-30625297-835f-4254-bb97-1b9b29f60f5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606022239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3606022239
Directory	/workspace/27.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/27.spi_device_read_buffer_direct.3777029466
Short name	T615
Test name
Test status
Simulation time	2681070810 ps
CPU time	8.7 seconds
Started	May 23 02:45:52 PM PDT 24
Finished	May 23 02:46:01 PM PDT 24
Peak memory	219520 kb
Host	smart-8763b1e1-4bbd-42ab-a21a-da1962b5e2fa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3777029466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.3777029466
Directory	/workspace/27.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/27.spi_device_stress_all.1423759290
Short name	T243
Test name
Test status
Simulation time	19047379364 ps
CPU time	180.01 seconds
Started	May 23 02:45:51 PM PDT 24
Finished	May 23 02:48:52 PM PDT 24
Peak memory	254236 kb
Host	smart-519cc3c1-c2a2-406e-94cd-ba28f55cb84a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423759290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre ss_all.1423759290
Directory	/workspace/27.spi_device_stress_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_all.3920782828
Short name	T10
Test name
Test status
Simulation time	27689993825 ps
CPU time	36.92 seconds
Started	May 23 02:45:40 PM PDT 24
Finished	May 23 02:46:17 PM PDT 24
Peak memory	216252 kb
Host	smart-42c9f9bc-32bb-4e77-9d8d-677b212f67f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920782828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3920782828
Directory	/workspace/27.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4037325385
Short name	T720
Test name
Test status
Simulation time	16371427677 ps
CPU time	12.6 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:51 PM PDT 24
Peak memory	216136 kb
Host	smart-82a4e3d0-40bc-4917-ac1d-6950077d2978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037325385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4037325385
Directory	/workspace/27.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_rw.3078613938
Short name	T921
Test name
Test status
Simulation time	279249780 ps
CPU time	2.75 seconds
Started	May 23 02:45:40 PM PDT 24
Finished	May 23 02:45:44 PM PDT 24
Peak memory	216180 kb
Host	smart-e90a1d90-4e7c-4f04-9c20-b7ebf5e8b3cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078613938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3078613938
Directory	/workspace/27.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_sts_read.2592062498
Short name	T849
Test name
Test status
Simulation time	58539832 ps
CPU time	0.98 seconds
Started	May 23 02:45:37 PM PDT 24
Finished	May 23 02:45:39 PM PDT 24
Peak memory	206004 kb
Host	smart-a8c642c0-d2f9-41e5-91c6-25ad15bc52ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592062498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2592062498
Directory	/workspace/27.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/27.spi_device_upload.380059670
Short name	T943
Test name
Test status
Simulation time	4777224243 ps
CPU time	18.24 seconds
Started	May 23 02:45:38 PM PDT 24
Finished	May 23 02:45:57 PM PDT 24
Peak memory	229448 kb
Host	smart-be28004e-8b1c-4406-820c-c293f45e22b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380059670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.380059670
Directory	/workspace/27.spi_device_upload/latest

Test location	/workspace/coverage/default/28.spi_device_alert_test.3103510764
Short name	T430
Test name
Test status
Simulation time	20085954 ps
CPU time	0.71 seconds
Started	May 23 02:46:03 PM PDT 24
Finished	May 23 02:46:05 PM PDT 24
Peak memory	205340 kb
Host	smart-5371a1f2-8813-4e1d-b3f7-94495b9c0a12
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103510764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 3103510764
Directory	/workspace/28.spi_device_alert_test/latest

Test location	/workspace/coverage/default/28.spi_device_cfg_cmd.425742057
Short name	T571
Test name
Test status
Simulation time	604878759 ps
CPU time	8.75 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:46:00 PM PDT 24
Peak memory	234040 kb
Host	smart-46324de7-0f90-4935-a056-f3f89f525ff9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425742057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.425742057
Directory	/workspace/28.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/28.spi_device_csb_read.3891393783
Short name	T316
Test name
Test status
Simulation time	24728349 ps
CPU time	0.78 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:45:51 PM PDT 24
Peak memory	206484 kb
Host	smart-5b9ddf8f-c000-4793-bb32-6fd587f278d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891393783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3891393783
Directory	/workspace/28.spi_device_csb_read/latest

Test location	/workspace/coverage/default/28.spi_device_flash_all.1685268945
Short name	T480
Test name
Test status
Simulation time	4323696465 ps
CPU time	22.02 seconds
Started	May 23 02:45:57 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	239968 kb
Host	smart-8fb285fc-5fbb-41bc-a989-fe84398ce5e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685268945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1685268945
Directory	/workspace/28.spi_device_flash_all/latest

Test location	/workspace/coverage/default/28.spi_device_flash_and_tpm.3605831055
Short name	T578
Test name
Test status
Simulation time	5583918649 ps
CPU time	39.35 seconds
Started	May 23 02:45:50 PM PDT 24
Finished	May 23 02:46:31 PM PDT 24
Peak memory	217256 kb
Host	smart-8066eb28-4ca2-4d70-98aa-e0325eb3a184
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605831055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3605831055
Directory	/workspace/28.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2027267328
Short name	T899
Test name
Test status
Simulation time	162732573346 ps
CPU time	373.27 seconds
Started	May 23 02:46:07 PM PDT 24
Finished	May 23 02:52:21 PM PDT 24
Peak memory	249104 kb
Host	smart-8ca6de7c-0411-49ef-b062-314d0abb3df4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027267328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl e.2027267328
Directory	/workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/28.spi_device_flash_mode.2127649375
Short name	T702
Test name
Test status
Simulation time	1184423867 ps
CPU time	8.23 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:45:58 PM PDT 24
Peak memory	239260 kb
Host	smart-a108db17-1fd3-4c1d-bc14-33b75b765aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127649375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2127649375
Directory	/workspace/28.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/28.spi_device_intercept.2826004787
Short name	T800
Test name
Test status
Simulation time	378058940 ps
CPU time	2.36 seconds
Started	May 23 02:45:52 PM PDT 24
Finished	May 23 02:45:55 PM PDT 24
Peak memory	218528 kb
Host	smart-0f385d22-db46-43c3-bc2e-219f15f99ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826004787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2826004787
Directory	/workspace/28.spi_device_intercept/latest

Test location	/workspace/coverage/default/28.spi_device_mailbox.184145397
Short name	T935
Test name
Test status
Simulation time	14449846423 ps
CPU time	116.93 seconds
Started	May 23 02:45:50 PM PDT 24
Finished	May 23 02:47:48 PM PDT 24
Peak memory	240828 kb
Host	smart-adf99865-5ee1-4ae9-92ff-53c7754ade64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184145397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.184145397
Directory	/workspace/28.spi_device_mailbox/latest

Test location	/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.333647220
Short name	T788
Test name
Test status
Simulation time	724517941 ps
CPU time	6.54 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:45:57 PM PDT 24
Peak memory	218700 kb
Host	smart-8779db29-2f7c-4506-8d3b-5be7a754ac29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333647220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap .333647220
Directory	/workspace/28.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/28.spi_device_pass_cmd_filtering.1957452715
Short name	T406
Test name
Test status
Simulation time	166434443 ps
CPU time	2.15 seconds
Started	May 23 02:45:56 PM PDT 24
Finished	May 23 02:46:00 PM PDT 24
Peak memory	218396 kb
Host	smart-77ede0ba-52ca-42ca-9f4c-fcf16e20b036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957452715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1957452715
Directory	/workspace/28.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/28.spi_device_read_buffer_direct.4081093610
Short name	T546
Test name
Test status
Simulation time	3139945819 ps
CPU time	5.85 seconds
Started	May 23 02:45:56 PM PDT 24
Finished	May 23 02:46:03 PM PDT 24
Peak memory	222832 kb
Host	smart-fd4877e1-0a44-4eb5-9506-3d2aee92d9ce
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4081093610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir ect.4081093610
Directory	/workspace/28.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/28.spi_device_stress_all.3348916692
Short name	T132
Test name
Test status
Simulation time	26300862612 ps
CPU time	338.38 seconds
Started	May 23 02:46:04 PM PDT 24
Finished	May 23 02:51:44 PM PDT 24
Peak memory	273064 kb
Host	smart-ae28c4cf-f01c-4c02-809b-de02815d8601
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348916692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre ss_all.3348916692
Directory	/workspace/28.spi_device_stress_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_all.516581201
Short name	T391
Test name
Test status
Simulation time	2063960686 ps
CPU time	17.45 seconds
Started	May 23 02:45:55 PM PDT 24
Finished	May 23 02:46:13 PM PDT 24
Peak memory	216384 kb
Host	smart-3f8e8885-d472-4155-8de8-87ec0c2c3a6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516581201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.516581201
Directory	/workspace/28.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2907451596
Short name	T663
Test name
Test status
Simulation time	1005536183 ps
CPU time	4.32 seconds
Started	May 23 02:45:56 PM PDT 24
Finished	May 23 02:46:02 PM PDT 24
Peak memory	216096 kb
Host	smart-347cb983-54c7-45d3-a53b-504120e7fdca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907451596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2907451596
Directory	/workspace/28.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_rw.4051047535
Short name	T575
Test name
Test status
Simulation time	184575345 ps
CPU time	2.1 seconds
Started	May 23 02:45:57 PM PDT 24
Finished	May 23 02:46:00 PM PDT 24
Peak memory	216120 kb
Host	smart-c13df052-f983-44f9-b0a7-7c511d521350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051047535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4051047535
Directory	/workspace/28.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_sts_read.153479560
Short name	T296
Test name
Test status
Simulation time	29280055 ps
CPU time	0.71 seconds
Started	May 23 02:45:48 PM PDT 24
Finished	May 23 02:45:50 PM PDT 24
Peak memory	205492 kb
Host	smart-2c8eabfd-b54d-409b-b1b3-b4998171adf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153479560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.153479560
Directory	/workspace/28.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/28.spi_device_upload.1128946618
Short name	T631
Test name
Test status
Simulation time	4639173809 ps
CPU time	11.01 seconds
Started	May 23 02:45:49 PM PDT 24
Finished	May 23 02:46:02 PM PDT 24
Peak memory	234428 kb
Host	smart-9328577f-bfc4-496a-8c95-bfc0d3c294e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128946618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1128946618
Directory	/workspace/28.spi_device_upload/latest

Test location	/workspace/coverage/default/29.spi_device_alert_test.276265529
Short name	T5
Test name
Test status
Simulation time	57288326 ps
CPU time	0.77 seconds
Started	May 23 02:46:09 PM PDT 24
Finished	May 23 02:46:11 PM PDT 24
Peak memory	205340 kb
Host	smart-51538b27-2ee9-467c-abc4-641243ae25db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276265529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.276265529
Directory	/workspace/29.spi_device_alert_test/latest

Test location	/workspace/coverage/default/29.spi_device_cfg_cmd.1451868627
Short name	T91
Test name
Test status
Simulation time	3695100215 ps
CPU time	9.1 seconds
Started	May 23 02:46:03 PM PDT 24
Finished	May 23 02:46:14 PM PDT 24
Peak memory	233868 kb
Host	smart-eb99f2ed-37f6-4984-adbf-d36a9cdebf5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451868627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1451868627
Directory	/workspace/29.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/29.spi_device_csb_read.218418709
Short name	T779
Test name
Test status
Simulation time	43177337 ps
CPU time	0.77 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:10 PM PDT 24
Peak memory	206828 kb
Host	smart-c3d7d0fb-96fe-4e55-bd71-0b9360dda128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218418709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.218418709
Directory	/workspace/29.spi_device_csb_read/latest

Test location	/workspace/coverage/default/29.spi_device_flash_all.3567007326
Short name	T416
Test name
Test status
Simulation time	38892523643 ps
CPU time	112.87 seconds
Started	May 23 02:46:06 PM PDT 24
Finished	May 23 02:48:00 PM PDT 24
Peak memory	249044 kb
Host	smart-a0236386-5393-421a-90de-e7880473ec29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567007326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3567007326
Directory	/workspace/29.spi_device_flash_all/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.587742948
Short name	T161
Test name
Test status
Simulation time	53027157781 ps
CPU time	466.08 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:53:56 PM PDT 24
Peak memory	249172 kb
Host	smart-9b8e1091-8adf-4349-a271-63837e2f5cf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587742948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle .587742948
Directory	/workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/29.spi_device_flash_mode.3825969907
Short name	T311
Test name
Test status
Simulation time	72591354 ps
CPU time	3.16 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:13 PM PDT 24
Peak memory	232568 kb
Host	smart-7c07dc41-f6c3-497f-a511-5614e2d8a6a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825969907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3825969907
Directory	/workspace/29.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/29.spi_device_intercept.1151060368
Short name	T589
Test name
Test status
Simulation time	7676267318 ps
CPU time	29.94 seconds
Started	May 23 02:46:07 PM PDT 24
Finished	May 23 02:46:38 PM PDT 24
Peak memory	222484 kb
Host	smart-751f4917-43ec-4462-8197-59f40a6b808a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151060368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1151060368
Directory	/workspace/29.spi_device_intercept/latest

Test location	/workspace/coverage/default/29.spi_device_mailbox.3884216666
Short name	T627
Test name
Test status
Simulation time	11504785209 ps
CPU time	14.53 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:24 PM PDT 24
Peak memory	235528 kb
Host	smart-8f18edd6-682c-4d34-9f7d-f7323d0dc948
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884216666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3884216666
Directory	/workspace/29.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4125832761
Short name	T279
Test name
Test status
Simulation time	1732686977 ps
CPU time	9.06 seconds
Started	May 23 02:46:03 PM PDT 24
Finished	May 23 02:46:14 PM PDT 24
Peak memory	223380 kb
Host	smart-09fa0173-6685-4c38-bbe0-50a7937cb8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4125832761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa p.4125832761
Directory	/workspace/29.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/29.spi_device_pass_cmd_filtering.2018481105
Short name	T619
Test name
Test status
Simulation time	37335257395 ps
CPU time	28.58 seconds
Started	May 23 02:46:04 PM PDT 24
Finished	May 23 02:46:34 PM PDT 24
Peak memory	240124 kb
Host	smart-300738c1-8c60-4cb5-98aa-a46ae6be2272
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018481105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2018481105
Directory	/workspace/29.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/29.spi_device_read_buffer_direct.4183792321
Short name	T375
Test name
Test status
Simulation time	4011824413 ps
CPU time	20.4 seconds
Started	May 23 02:46:04 PM PDT 24
Finished	May 23 02:46:27 PM PDT 24
Peak memory	222084 kb
Host	smart-a9eb0577-8cd4-461a-bbdd-1eb43e14a653
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4183792321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir ect.4183792321
Directory	/workspace/29.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_all.3583058551
Short name	T464
Test name
Test status
Simulation time	2114035568 ps
CPU time	5.91 seconds
Started	May 23 02:46:03 PM PDT 24
Finished	May 23 02:46:11 PM PDT 24
Peak memory	215980 kb
Host	smart-0324859a-a858-4b2e-b94d-10ea7fb93ecc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583058551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3583058551
Directory	/workspace/29.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3005479574
Short name	T307
Test name
Test status
Simulation time	1740512799 ps
CPU time	6.81 seconds
Started	May 23 02:46:03 PM PDT 24
Finished	May 23 02:46:12 PM PDT 24
Peak memory	216108 kb
Host	smart-4dccfb3f-1661-4846-ad7c-12801a731398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005479574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3005479574
Directory	/workspace/29.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_rw.2832062796
Short name	T857
Test name
Test status
Simulation time	182568614 ps
CPU time	1.2 seconds
Started	May 23 02:46:09 PM PDT 24
Finished	May 23 02:46:11 PM PDT 24
Peak memory	208016 kb
Host	smart-563d4115-bcb6-4274-b0b7-f0cf0d82948e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832062796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2832062796
Directory	/workspace/29.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_sts_read.558625338
Short name	T628
Test name
Test status
Simulation time	163669471 ps
CPU time	0.94 seconds
Started	May 23 02:46:05 PM PDT 24
Finished	May 23 02:46:07 PM PDT 24
Peak memory	205968 kb
Host	smart-8845306a-62a4-4631-8cbb-2660b84f8924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558625338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.558625338
Directory	/workspace/29.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/29.spi_device_upload.3411983443
Short name	T616
Test name
Test status
Simulation time	2093134634 ps
CPU time	4.15 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:14 PM PDT 24
Peak memory	233656 kb
Host	smart-bf8f1285-a0ec-425a-85e2-f790ec044227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411983443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3411983443
Directory	/workspace/29.spi_device_upload/latest

Test location	/workspace/coverage/default/3.spi_device_alert_test.1150009048
Short name	T585
Test name
Test status
Simulation time	20044165 ps
CPU time	0.78 seconds
Started	May 23 02:41:22 PM PDT 24
Finished	May 23 02:41:23 PM PDT 24
Peak memory	205344 kb
Host	smart-e2f2264d-e1d1-4a75-80d4-6dfc1d35e991
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150009048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1 150009048
Directory	/workspace/3.spi_device_alert_test/latest

Test location	/workspace/coverage/default/3.spi_device_cfg_cmd.862410608
Short name	T541
Test name
Test status
Simulation time	15941127296 ps
CPU time	9.89 seconds
Started	May 23 02:41:12 PM PDT 24
Finished	May 23 02:41:22 PM PDT 24
Peak memory	233944 kb
Host	smart-1fc27bd2-d666-491f-9d5c-381f23491523
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862410608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.862410608
Directory	/workspace/3.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/3.spi_device_csb_read.1941178209
Short name	T378
Test name
Test status
Simulation time	56076032 ps
CPU time	0.79 seconds
Started	May 23 02:41:03 PM PDT 24
Finished	May 23 02:41:04 PM PDT 24
Peak memory	206468 kb
Host	smart-99dc179a-88e6-46f5-ad3e-3a4eb17dae74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941178209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1941178209
Directory	/workspace/3.spi_device_csb_read/latest

Test location	/workspace/coverage/default/3.spi_device_flash_all.2433762570
Short name	T601
Test name
Test status
Simulation time	3094911170 ps
CPU time	42.65 seconds
Started	May 23 02:41:13 PM PDT 24
Finished	May 23 02:41:56 PM PDT 24
Peak memory	239500 kb
Host	smart-6a38d3a5-27e1-4c12-ba09-c99c1f119a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433762570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2433762570
Directory	/workspace/3.spi_device_flash_all/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm.1485741755
Short name	T204
Test name
Test status
Simulation time	157210531498 ps
CPU time	422.6 seconds
Started	May 23 02:41:10 PM PDT 24
Finished	May 23 02:48:14 PM PDT 24
Peak memory	255340 kb
Host	smart-6c4d0fcc-c33e-42c2-807b-04cf2b8c5823
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485741755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1485741755
Directory	/workspace/3.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3595887747
Short name	T701
Test name
Test status
Simulation time	42431838301 ps
CPU time	145.34 seconds
Started	May 23 02:41:11 PM PDT 24
Finished	May 23 02:43:37 PM PDT 24
Peak memory	250872 kb
Host	smart-1d0c98ad-2df1-42aa-adbc-d350a4985d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595887747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle .3595887747
Directory	/workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/3.spi_device_flash_mode.742839744
Short name	T345
Test name
Test status
Simulation time	169895605 ps
CPU time	6.41 seconds
Started	May 23 02:41:11 PM PDT 24
Finished	May 23 02:41:18 PM PDT 24
Peak memory	240772 kb
Host	smart-b73881da-2e36-464e-b588-2f4475ce0d95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742839744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.742839744
Directory	/workspace/3.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/3.spi_device_intercept.768958085
Short name	T259
Test name
Test status
Simulation time	500348310 ps
CPU time	3.35 seconds
Started	May 23 02:41:11 PM PDT 24
Finished	May 23 02:41:15 PM PDT 24
Peak memory	233484 kb
Host	smart-16b5d713-eb85-4ada-adf5-3e6433e9964a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768958085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.768958085
Directory	/workspace/3.spi_device_intercept/latest

Test location	/workspace/coverage/default/3.spi_device_mailbox.897296549
Short name	T644
Test name
Test status
Simulation time	1242259035 ps
CPU time	18.07 seconds
Started	May 23 02:41:09 PM PDT 24
Finished	May 23 02:41:28 PM PDT 24
Peak memory	233728 kb
Host	smart-585caea8-b24d-410c-880c-10b0e17980d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897296549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.897296549
Directory	/workspace/3.spi_device_mailbox/latest

Test location	/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3249104557
Short name	T215
Test name
Test status
Simulation time	2155023317 ps
CPU time	6.97 seconds
Started	May 23 02:41:11 PM PDT 24
Finished	May 23 02:41:19 PM PDT 24
Peak memory	233588 kb
Host	smart-4fd8f502-ed2b-43d2-9949-9d86058c939d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249104557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap .3249104557
Directory	/workspace/3.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/3.spi_device_pass_cmd_filtering.1651584535
Short name	T813
Test name
Test status
Simulation time	440742915 ps
CPU time	3.86 seconds
Started	May 23 02:41:12 PM PDT 24
Finished	May 23 02:41:17 PM PDT 24
Peak memory	233304 kb
Host	smart-1060b9fe-3dc2-40e8-a2a3-8ae9373e8175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651584535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1651584535
Directory	/workspace/3.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/3.spi_device_read_buffer_direct.1414203177
Short name	T879
Test name
Test status
Simulation time	1878042742 ps
CPU time	8.39 seconds
Started	May 23 02:41:10 PM PDT 24
Finished	May 23 02:41:19 PM PDT 24
Peak memory	222868 kb
Host	smart-14ea4eca-48bb-420e-a07d-c7427e04b765
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1414203177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.1414203177
Directory	/workspace/3.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/3.spi_device_sec_cm.3446079914
Short name	T78
Test name
Test status
Simulation time	325932191 ps
CPU time	1.19 seconds
Started	May 23 02:41:23 PM PDT 24
Finished	May 23 02:41:25 PM PDT 24
Peak memory	234692 kb
Host	smart-7ae3a734-9475-4704-aa06-fa62c848b6de
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446079914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3446079914
Directory	/workspace/3.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/3.spi_device_stress_all.1082709378
Short name	T155
Test name
Test status
Simulation time	153455064 ps
CPU time	1.02 seconds
Started	May 23 02:41:11 PM PDT 24
Finished	May 23 02:41:13 PM PDT 24
Peak memory	206464 kb
Host	smart-8b789b7a-5a4d-476a-9350-954b9ba9ae3c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082709378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres s_all.1082709378
Directory	/workspace/3.spi_device_stress_all/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_all.3882813618
Short name	T505
Test name
Test status
Simulation time	7110818025 ps
CPU time	34.31 seconds
Started	May 23 02:40:59 PM PDT 24
Finished	May 23 02:41:35 PM PDT 24
Peak memory	216260 kb
Host	smart-d61d3517-64a6-431b-aa87-d1fc4548b135
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882813618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3882813618
Directory	/workspace/3.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1341127245
Short name	T742
Test name
Test status
Simulation time	1234708849 ps
CPU time	5.23 seconds
Started	May 23 02:41:00 PM PDT 24
Finished	May 23 02:41:07 PM PDT 24
Peak memory	216168 kb
Host	smart-dae5782c-500d-4f8c-92f9-8759d8ef5511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341127245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1341127245
Directory	/workspace/3.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_rw.4008932416
Short name	T798
Test name
Test status
Simulation time	255177975 ps
CPU time	9.01 seconds
Started	May 23 02:40:58 PM PDT 24
Finished	May 23 02:41:09 PM PDT 24
Peak memory	216192 kb
Host	smart-57d25f64-843f-4fd9-a7dc-15405683d342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008932416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4008932416
Directory	/workspace/3.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_sts_read.2947866516
Short name	T710
Test name
Test status
Simulation time	49453129 ps
CPU time	0.89 seconds
Started	May 23 02:41:00 PM PDT 24
Finished	May 23 02:41:03 PM PDT 24
Peak memory	205716 kb
Host	smart-090c134c-4e85-4868-895b-2ff79c3b6ab6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947866516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2947866516
Directory	/workspace/3.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/3.spi_device_upload.2188143147
Short name	T836
Test name
Test status
Simulation time	4481791557 ps
CPU time	6.72 seconds
Started	May 23 02:41:16 PM PDT 24
Finished	May 23 02:41:23 PM PDT 24
Peak memory	224356 kb
Host	smart-86f4f8b1-2330-4486-9d57-df02dd4179f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188143147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2188143147
Directory	/workspace/3.spi_device_upload/latest

Test location	/workspace/coverage/default/30.spi_device_alert_test.681004633
Short name	T646
Test name
Test status
Simulation time	14835087 ps
CPU time	0.75 seconds
Started	May 23 02:46:18 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	205240 kb
Host	smart-9e92ad33-4176-48a4-b1b0-be25e76c7ac8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681004633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.681004633
Directory	/workspace/30.spi_device_alert_test/latest

Test location	/workspace/coverage/default/30.spi_device_cfg_cmd.548779212
Short name	T401
Test name
Test status
Simulation time	57193866 ps
CPU time	2.41 seconds
Started	May 23 02:46:17 PM PDT 24
Finished	May 23 02:46:21 PM PDT 24
Peak memory	218664 kb
Host	smart-32438f12-dca3-41d3-be3a-5028042af8f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548779212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.548779212
Directory	/workspace/30.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/30.spi_device_csb_read.746392530
Short name	T62
Test name
Test status
Simulation time	13246087 ps
CPU time	0.75 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:10 PM PDT 24
Peak memory	205476 kb
Host	smart-53230ebd-0812-4823-8261-1b6324c1d02d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746392530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.746392530
Directory	/workspace/30.spi_device_csb_read/latest

Test location	/workspace/coverage/default/30.spi_device_flash_all.2362676043
Short name	T25
Test name
Test status
Simulation time	3383898034 ps
CPU time	42.69 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:47:00 PM PDT 24
Peak memory	248864 kb
Host	smart-29bc6766-7d8e-495d-9e4b-d10545796309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362676043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2362676043
Directory	/workspace/30.spi_device_flash_all/latest

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm.2911200998
Short name	T481
Test name
Test status
Simulation time	11254794164 ps
CPU time	76.09 seconds
Started	May 23 02:46:20 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	249332 kb
Host	smart-a3e10b35-6462-4c25-91db-ad739e5dfa61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911200998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2911200998
Directory	/workspace/30.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3594892759
Short name	T682
Test name
Test status
Simulation time	1809303724 ps
CPU time	29.24 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:46 PM PDT 24
Peak memory	224404 kb
Host	smart-078fdc76-6e88-45f9-9468-5e49fd2cae7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594892759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl e.3594892759
Directory	/workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/30.spi_device_flash_mode.2461427510
Short name	T831
Test name
Test status
Simulation time	3668097602 ps
CPU time	26.92 seconds
Started	May 23 02:46:18 PM PDT 24
Finished	May 23 02:46:46 PM PDT 24
Peak memory	249072 kb
Host	smart-46ce6350-7164-4110-9853-f18faf4c114c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461427510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2461427510
Directory	/workspace/30.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/30.spi_device_intercept.3610860332
Short name	T778
Test name
Test status
Simulation time	468055132 ps
CPU time	4.5 seconds
Started	May 23 02:46:22 PM PDT 24
Finished	May 23 02:46:27 PM PDT 24
Peak memory	233120 kb
Host	smart-0c3bf3a9-2fff-484a-88b0-cbd348171bba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610860332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3610860332
Directory	/workspace/30.spi_device_intercept/latest

Test location	/workspace/coverage/default/30.spi_device_mailbox.3155560182
Short name	T751
Test name
Test status
Simulation time	7936297560 ps
CPU time	28.85 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:46 PM PDT 24
Peak memory	221240 kb
Host	smart-635c1981-c95b-4938-aa17-fad3a24454f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155560182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3155560182
Directory	/workspace/30.spi_device_mailbox/latest

Test location	/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1844779293
Short name	T838
Test name
Test status
Simulation time	1728241908 ps
CPU time	3.85 seconds
Started	May 23 02:46:26 PM PDT 24
Finished	May 23 02:46:31 PM PDT 24
Peak memory	219952 kb
Host	smart-0e447cb5-5e3f-40f8-9c3b-110e0c7382c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844779293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa p.1844779293
Directory	/workspace/30.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/30.spi_device_pass_cmd_filtering.2383187192
Short name	T238
Test name
Test status
Simulation time	236895086 ps
CPU time	3.26 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:21 PM PDT 24
Peak memory	224464 kb
Host	smart-89230d7f-ad70-4868-8a2f-34498a54c4ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383187192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2383187192
Directory	/workspace/30.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/30.spi_device_read_buffer_direct.149046354
Short name	T380
Test name
Test status
Simulation time	275104298 ps
CPU time	3.58 seconds
Started	May 23 02:46:18 PM PDT 24
Finished	May 23 02:46:23 PM PDT 24
Peak memory	220204 kb
Host	smart-9e0e0ecd-ef43-46f9-ab94-24f7ce8fac0f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=149046354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire ct.149046354
Directory	/workspace/30.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/30.spi_device_stress_all.1621156700
Short name	T138
Test name
Test status
Simulation time	36481399004 ps
CPU time	140.61 seconds
Started	May 23 02:46:19 PM PDT 24
Finished	May 23 02:48:40 PM PDT 24
Peak memory	264152 kb
Host	smart-16f9f4b0-42b5-4381-9a19-fda42d43ff7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621156700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre ss_all.1621156700
Directory	/workspace/30.spi_device_stress_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_all.3842600145
Short name	T288
Test name
Test status
Simulation time	2377218297 ps
CPU time	6.26 seconds
Started	May 23 02:46:02 PM PDT 24
Finished	May 23 02:46:09 PM PDT 24
Peak memory	216264 kb
Host	smart-dc5512d9-06a6-4c20-939b-eb33dd056e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842600145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3842600145
Directory	/workspace/30.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2199329181
Short name	T579
Test name
Test status
Simulation time	777409635 ps
CPU time	1.94 seconds
Started	May 23 02:46:09 PM PDT 24
Finished	May 23 02:46:12 PM PDT 24
Peak memory	207840 kb
Host	smart-f4acdb0e-6658-4b3e-b924-4c81714c182f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199329181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2199329181
Directory	/workspace/30.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_rw.717149934
Short name	T884
Test name
Test status
Simulation time	248716268 ps
CPU time	1.3 seconds
Started	May 23 02:46:02 PM PDT 24
Finished	May 23 02:46:04 PM PDT 24
Peak memory	207472 kb
Host	smart-9348f429-8770-4d35-ad6f-a348b9ff1311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717149934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.717149934
Directory	/workspace/30.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_sts_read.2626657080
Short name	T673
Test name
Test status
Simulation time	108724610 ps
CPU time	0.9 seconds
Started	May 23 02:46:08 PM PDT 24
Finished	May 23 02:46:11 PM PDT 24
Peak memory	205740 kb
Host	smart-c676c605-2b95-4e70-95b2-0c75c1ada2d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626657080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2626657080
Directory	/workspace/30.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/30.spi_device_upload.192900259
Short name	T862
Test name
Test status
Simulation time	3602366880 ps
CPU time	5 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:22 PM PDT 24
Peak memory	233372 kb
Host	smart-cf2d62cf-1dbb-4c88-9ba0-b0c74d0f6591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192900259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.192900259
Directory	/workspace/30.spi_device_upload/latest

Test location	/workspace/coverage/default/31.spi_device_alert_test.2272144104
Short name	T306
Test name
Test status
Simulation time	48335784 ps
CPU time	0.73 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:37 PM PDT 24
Peak memory	205364 kb
Host	smart-f02af67f-8059-4c95-b902-4019dcab37f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272144104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test. 2272144104
Directory	/workspace/31.spi_device_alert_test/latest

Test location	/workspace/coverage/default/31.spi_device_cfg_cmd.4278491609
Short name	T597
Test name
Test status
Simulation time	682729494 ps
CPU time	4.77 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:22 PM PDT 24
Peak memory	220504 kb
Host	smart-52a3d6d1-f38c-4981-b2cf-0e81f08549d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278491609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4278491609
Directory	/workspace/31.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/31.spi_device_csb_read.878742937
Short name	T604
Test name
Test status
Simulation time	16815246 ps
CPU time	0.75 seconds
Started	May 23 02:46:26 PM PDT 24
Finished	May 23 02:46:28 PM PDT 24
Peak memory	205280 kb
Host	smart-746a3801-ab92-4d0e-8b33-4c55daf819ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878742937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.878742937
Directory	/workspace/31.spi_device_csb_read/latest

Test location	/workspace/coverage/default/31.spi_device_flash_all.3896315733
Short name	T555
Test name
Test status
Simulation time	20260689863 ps
CPU time	29.91 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:47:07 PM PDT 24
Peak memory	232664 kb
Host	smart-286ecb14-d9bb-4145-9615-849d994bb3fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896315733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3896315733
Directory	/workspace/31.spi_device_flash_all/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1113131614
Short name	T404
Test name
Test status
Simulation time	19476914652 ps
CPU time	188.59 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:49:45 PM PDT 24
Peak memory	249140 kb
Host	smart-6f111e87-8f2c-48f5-8a8b-d8d624b52437
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113131614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl e.1113131614
Directory	/workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/31.spi_device_flash_mode.3452234528
Short name	T893
Test name
Test status
Simulation time	4341687952 ps
CPU time	32.5 seconds
Started	May 23 02:46:19 PM PDT 24
Finished	May 23 02:46:52 PM PDT 24
Peak memory	232700 kb
Host	smart-4e1e2963-5b85-473a-8773-33501e61a87b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452234528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3452234528
Directory	/workspace/31.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/31.spi_device_intercept.3416076110
Short name	T714
Test name
Test status
Simulation time	107978944 ps
CPU time	2.09 seconds
Started	May 23 02:46:17 PM PDT 24
Finished	May 23 02:46:21 PM PDT 24
Peak memory	215972 kb
Host	smart-eba9adbc-580b-4832-9154-b591547f5c93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416076110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3416076110
Directory	/workspace/31.spi_device_intercept/latest

Test location	/workspace/coverage/default/31.spi_device_mailbox.3479907568
Short name	T100
Test name
Test status
Simulation time	3136521510 ps
CPU time	13.6 seconds
Started	May 23 02:46:17 PM PDT 24
Finished	May 23 02:46:32 PM PDT 24
Peak memory	234152 kb
Host	smart-b855f64d-61e3-49ee-a7f5-dfbf3fdf1ce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479907568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3479907568
Directory	/workspace/31.spi_device_mailbox/latest

Test location	/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2246275959
Short name	T248
Test name
Test status
Simulation time	5584925140 ps
CPU time	14.75 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:31 PM PDT 24
Peak memory	229628 kb
Host	smart-8390debf-cc22-4427-8ad9-a1149177f89a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246275959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa p.2246275959
Directory	/workspace/31.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/31.spi_device_pass_cmd_filtering.3267105585
Short name	T590
Test name
Test status
Simulation time	8409825893 ps
CPU time	19.33 seconds
Started	May 23 02:46:19 PM PDT 24
Finished	May 23 02:46:39 PM PDT 24
Peak memory	232652 kb
Host	smart-3c86405b-f87c-4a9c-8d27-072d01e5e9c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267105585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3267105585
Directory	/workspace/31.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/31.spi_device_read_buffer_direct.428112570
Short name	T359
Test name
Test status
Simulation time	5077001745 ps
CPU time	13.31 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:50 PM PDT 24
Peak memory	220344 kb
Host	smart-d09ee75f-4c23-4dd0-88d7-48f1f05dfe76
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=428112570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire ct.428112570
Directory	/workspace/31.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/31.spi_device_stress_all.83223976
Short name	T53
Test name
Test status
Simulation time	35873406427 ps
CPU time	79.92 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:47:55 PM PDT 24
Peak memory	240904 kb
Host	smart-5bd4538a-94e5-4595-8b8c-89c2ce47880c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83223976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress _all.83223976
Directory	/workspace/31.spi_device_stress_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_all.2941217590
Short name	T449
Test name
Test status
Simulation time	1323305985 ps
CPU time	9.25 seconds
Started	May 23 02:46:20 PM PDT 24
Finished	May 23 02:46:30 PM PDT 24
Peak memory	216172 kb
Host	smart-52c8b912-a3d3-4871-b95b-de5bb3d6844b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941217590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2941217590
Directory	/workspace/31.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1911614101
Short name	T131
Test name
Test status
Simulation time	340857809 ps
CPU time	2.57 seconds
Started	May 23 02:46:16 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	216064 kb
Host	smart-72a7f8c0-6102-42b1-a548-1fb348b6af43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911614101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1911614101
Directory	/workspace/31.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_rw.242057173
Short name	T819
Test name
Test status
Simulation time	1097303402 ps
CPU time	1.68 seconds
Started	May 23 02:46:17 PM PDT 24
Finished	May 23 02:46:20 PM PDT 24
Peak memory	216272 kb
Host	smart-bab3f3de-68cf-400f-a783-d78f06619ae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242057173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.242057173
Directory	/workspace/31.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_sts_read.3632480313
Short name	T913
Test name
Test status
Simulation time	149341223 ps
CPU time	0.81 seconds
Started	May 23 02:46:20 PM PDT 24
Finished	May 23 02:46:21 PM PDT 24
Peak memory	205680 kb
Host	smart-aee4836c-891b-48f9-80fb-718b4980a31a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632480313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3632480313
Directory	/workspace/31.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/31.spi_device_upload.234905919
Short name	T566
Test name
Test status
Simulation time	1766285737 ps
CPU time	10.97 seconds
Started	May 23 02:46:18 PM PDT 24
Finished	May 23 02:46:30 PM PDT 24
Peak memory	233040 kb
Host	smart-484b54e1-dc98-479b-9244-5515785b8394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234905919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.234905919
Directory	/workspace/31.spi_device_upload/latest

Test location	/workspace/coverage/default/32.spi_device_alert_test.2051746749
Short name	T413
Test name
Test status
Simulation time	144306528 ps
CPU time	0.71 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:46:38 PM PDT 24
Peak memory	205692 kb
Host	smart-87a04588-315a-44b7-942a-3cbcd591b762
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051746749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 2051746749
Directory	/workspace/32.spi_device_alert_test/latest

Test location	/workspace/coverage/default/32.spi_device_cfg_cmd.3510464588
Short name	T651
Test name
Test status
Simulation time	1379056194 ps
CPU time	4.13 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:41 PM PDT 24
Peak memory	218476 kb
Host	smart-dc1234d8-dd91-405c-b1e5-35498ec8fd81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510464588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3510464588
Directory	/workspace/32.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/32.spi_device_csb_read.1990572570
Short name	T6
Test name
Test status
Simulation time	26951456 ps
CPU time	0.76 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:37 PM PDT 24
Peak memory	206772 kb
Host	smart-3c91d0fa-e111-46ed-a9c7-a0d098eefe95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990572570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1990572570
Directory	/workspace/32.spi_device_csb_read/latest

Test location	/workspace/coverage/default/32.spi_device_flash_all.2402837117
Short name	T428
Test name
Test status
Simulation time	28174980140 ps
CPU time	134.64 seconds
Started	May 23 02:46:37 PM PDT 24
Finished	May 23 02:48:53 PM PDT 24
Peak memory	249012 kb
Host	smart-e2b4efc1-68a6-4077-952f-44df4aaa1e45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402837117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2402837117
Directory	/workspace/32.spi_device_flash_all/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm.4278869220
Short name	T817
Test name
Test status
Simulation time	65778850854 ps
CPU time	138.23 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:48:53 PM PDT 24
Peak memory	249120 kb
Host	smart-5f48783c-8c94-4e73-9777-516996cab94a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278869220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4278869220
Directory	/workspace/32.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2783218371
Short name	T222
Test name
Test status
Simulation time	203561035529 ps
CPU time	439.66 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:53:56 PM PDT 24
Peak memory	265552 kb
Host	smart-09a00fa1-35ee-4290-8a89-debe94ab5a21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783218371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl e.2783218371
Directory	/workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/32.spi_device_flash_mode.4237706336
Short name	T689
Test name
Test status
Simulation time	891589482 ps
CPU time	12.3 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:49 PM PDT 24
Peak memory	240600 kb
Host	smart-0e3d06c9-adc9-4d14-b12b-54da37d39653
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237706336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4237706336
Directory	/workspace/32.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/32.spi_device_intercept.1697648522
Short name	T690
Test name
Test status
Simulation time	663168252 ps
CPU time	6.71 seconds
Started	May 23 02:46:38 PM PDT 24
Finished	May 23 02:46:46 PM PDT 24
Peak memory	234052 kb
Host	smart-28c1e5bd-f230-4da8-8473-68ad79ffe739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697648522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1697648522
Directory	/workspace/32.spi_device_intercept/latest

Test location	/workspace/coverage/default/32.spi_device_mailbox.1191085917
Short name	T500
Test name
Test status
Simulation time	30241560 ps
CPU time	2.77 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:39 PM PDT 24
Peak memory	221532 kb
Host	smart-da1caea0-987b-4b1b-99ec-46a8e8a785c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191085917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1191085917
Directory	/workspace/32.spi_device_mailbox/latest

Test location	/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1283772766
Short name	T498
Test name
Test status
Simulation time	5955565739 ps
CPU time	5.46 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:46:43 PM PDT 24
Peak memory	218628 kb
Host	smart-ad03fcdb-12e9-4867-90c8-0645f7af4c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283772766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.1283772766
Directory	/workspace/32.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/32.spi_device_pass_cmd_filtering.3545097509
Short name	T561
Test name
Test status
Simulation time	19571795040 ps
CPU time	9.61 seconds
Started	May 23 02:46:38 PM PDT 24
Finished	May 23 02:46:48 PM PDT 24
Peak memory	218844 kb
Host	smart-94f68177-d3e5-4d1e-a76a-abc59cf6fe46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545097509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3545097509
Directory	/workspace/32.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/32.spi_device_read_buffer_direct.3518536359
Short name	T705
Test name
Test status
Simulation time	642151932 ps
CPU time	4.8 seconds
Started	May 23 02:46:37 PM PDT 24
Finished	May 23 02:46:43 PM PDT 24
Peak memory	219632 kb
Host	smart-97fb7b30-581a-4dc2-a159-b394a88b6f4c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3518536359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir ect.3518536359
Directory	/workspace/32.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/32.spi_device_stress_all.85272074
Short name	T42
Test name
Test status
Simulation time	91889554416 ps
CPU time	326.67 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:52:04 PM PDT 24
Peak memory	260676 kb
Host	smart-74fc8772-930b-43c7-9be3-0e544b7c5e27
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85272074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress _all.85272074
Directory	/workspace/32.spi_device_stress_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_all.1582694054
Short name	T686
Test name
Test status
Simulation time	27879675 ps
CPU time	0.71 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:46:38 PM PDT 24
Peak memory	205604 kb
Host	smart-4c4e42c1-93ee-495a-835c-701970e419c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582694054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1582694054
Directory	/workspace/32.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3515777624
Short name	T622
Test name
Test status
Simulation time	11650572865 ps
CPU time	9.55 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:47 PM PDT 24
Peak memory	217308 kb
Host	smart-a2948afb-df7c-428a-88e2-b4b4455a1c5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515777624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3515777624
Directory	/workspace/32.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_rw.2921386870
Short name	T716
Test name
Test status
Simulation time	177375981 ps
CPU time	1.02 seconds
Started	May 23 02:46:39 PM PDT 24
Finished	May 23 02:46:41 PM PDT 24
Peak memory	207712 kb
Host	smart-0b4a5b5e-ae97-4dff-873f-015dd2cadc88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921386870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2921386870
Directory	/workspace/32.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_sts_read.1233399178
Short name	T687
Test name
Test status
Simulation time	21711622 ps
CPU time	0.78 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:46:38 PM PDT 24
Peak memory	205664 kb
Host	smart-d8fb04e5-7b20-49c9-83e7-9b02ea88af65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233399178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1233399178
Directory	/workspace/32.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/32.spi_device_upload.3542906137
Short name	T295
Test name
Test status
Simulation time	137745388 ps
CPU time	2.12 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:39 PM PDT 24
Peak memory	207748 kb
Host	smart-0841d712-367c-4d76-9a02-fee06cb4b52c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542906137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3542906137
Directory	/workspace/32.spi_device_upload/latest

Test location	/workspace/coverage/default/33.spi_device_alert_test.1939753988
Short name	T865
Test name
Test status
Simulation time	22863573 ps
CPU time	0.7 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:46:51 PM PDT 24
Peak memory	205324 kb
Host	smart-40c200ef-7d31-46af-95dd-dcc8830246ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939753988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 1939753988
Directory	/workspace/33.spi_device_alert_test/latest

Test location	/workspace/coverage/default/33.spi_device_cfg_cmd.3114977630
Short name	T89
Test name
Test status
Simulation time	1145780408 ps
CPU time	6.99 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:43 PM PDT 24
Peak memory	218432 kb
Host	smart-6308c37f-1a16-475a-9b24-d1211a30bb76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114977630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3114977630
Directory	/workspace/33.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/33.spi_device_csb_read.2804039638
Short name	T407
Test name
Test status
Simulation time	91668415 ps
CPU time	0.76 seconds
Started	May 23 02:46:35 PM PDT 24
Finished	May 23 02:46:37 PM PDT 24
Peak memory	205416 kb
Host	smart-7962b872-e5b1-4210-92b5-2ae28955a9b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804039638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2804039638
Directory	/workspace/33.spi_device_csb_read/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm.3903754104
Short name	T874
Test name
Test status
Simulation time	4127636893 ps
CPU time	20.32 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:47:11 PM PDT 24
Peak memory	249140 kb
Host	smart-26761a18-0188-49a8-8966-383be338100b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903754104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3903754104
Directory	/workspace/33.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1324936548
Short name	T400
Test name
Test status
Simulation time	4907538762 ps
CPU time	25.06 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:47:15 PM PDT 24
Peak memory	219208 kb
Host	smart-29426df7-0fc2-4a04-92ca-b3f0c324e56c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324936548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl e.1324936548
Directory	/workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/33.spi_device_flash_mode.1558295195
Short name	T853
Test name
Test status
Simulation time	523005295 ps
CPU time	14.22 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:46:49 PM PDT 24
Peak memory	232512 kb
Host	smart-e5ee025d-4343-4554-8916-84b189ea0408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558295195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1558295195
Directory	/workspace/33.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/33.spi_device_intercept.47106778
Short name	T127
Test name
Test status
Simulation time	99553126 ps
CPU time	2.15 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:46:37 PM PDT 24
Peak memory	215936 kb
Host	smart-2534f96c-1edd-444e-8842-9f479c909d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47106778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.47106778
Directory	/workspace/33.spi_device_intercept/latest

Test location	/workspace/coverage/default/33.spi_device_mailbox.2531179795
Short name	T634
Test name
Test status
Simulation time	74952243 ps
CPU time	2.37 seconds
Started	May 23 02:46:38 PM PDT 24
Finished	May 23 02:46:41 PM PDT 24
Peak memory	215952 kb
Host	smart-7d822cc0-289a-4ac8-a567-9928c4fdd161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531179795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2531179795
Directory	/workspace/33.spi_device_mailbox/latest

Test location	/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.228583810
Short name	T180
Test name
Test status
Simulation time	236103418 ps
CPU time	3.33 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:46:41 PM PDT 24
Peak memory	233024 kb
Host	smart-d8b57b6c-ad09-4e89-ac3f-dc3c01fcac61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228583810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap .228583810
Directory	/workspace/33.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/33.spi_device_pass_cmd_filtering.3286721646
Short name	T513
Test name
Test status
Simulation time	1931564106 ps
CPU time	9.67 seconds
Started	May 23 02:46:38 PM PDT 24
Finished	May 23 02:46:49 PM PDT 24
Peak memory	219656 kb
Host	smart-d85516ea-44ea-40ec-aeef-79dbf3afb785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286721646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3286721646
Directory	/workspace/33.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/33.spi_device_read_buffer_direct.3986588107
Short name	T140
Test name
Test status
Simulation time	654569277 ps
CPU time	10.4 seconds
Started	May 23 02:46:46 PM PDT 24
Finished	May 23 02:46:57 PM PDT 24
Peak memory	220308 kb
Host	smart-38bcd4d5-b325-4ee5-b85c-148652e2f5fc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3986588107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.3986588107
Directory	/workspace/33.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/33.spi_device_stress_all.464859623
Short name	T173
Test name
Test status
Simulation time	47298482659 ps
CPU time	377.66 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:53:07 PM PDT 24
Peak memory	282388 kb
Host	smart-5ec8984a-5a8a-40d1-9d44-1deacd8df02a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464859623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres s_all.464859623
Directory	/workspace/33.spi_device_stress_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_all.442356970
Short name	T868
Test name
Test status
Simulation time	11828124072 ps
CPU time	59.57 seconds
Started	May 23 02:46:36 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	216200 kb
Host	smart-fcb1fab6-741d-4436-b0ba-a03d2c99d700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442356970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.442356970
Directory	/workspace/33.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2801532903
Short name	T539
Test name
Test status
Simulation time	779114350 ps
CPU time	4.37 seconds
Started	May 23 02:46:38 PM PDT 24
Finished	May 23 02:46:44 PM PDT 24
Peak memory	216116 kb
Host	smart-20aacd75-2420-437c-8c47-02f5cfc66ad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801532903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2801532903
Directory	/workspace/33.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_rw.2915436012
Short name	T323
Test name
Test status
Simulation time	54467844 ps
CPU time	1.13 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:46:36 PM PDT 24
Peak memory	207216 kb
Host	smart-22d71daa-ce9e-4f1f-9ac9-671161a7abde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915436012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2915436012
Directory	/workspace/33.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_sts_read.1633247501
Short name	T456
Test name
Test status
Simulation time	63581525 ps
CPU time	0.73 seconds
Started	May 23 02:46:34 PM PDT 24
Finished	May 23 02:46:35 PM PDT 24
Peak memory	205736 kb
Host	smart-bba40cf3-efa9-4f24-8e67-f4bd145fd4fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633247501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1633247501
Directory	/workspace/33.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/33.spi_device_upload.2132155475
Short name	T340
Test name
Test status
Simulation time	161491153 ps
CPU time	2.63 seconds
Started	May 23 02:46:37 PM PDT 24
Finished	May 23 02:46:41 PM PDT 24
Peak memory	216188 kb
Host	smart-bb287c61-c5bf-4414-a244-bfde2844db3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132155475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2132155475
Directory	/workspace/33.spi_device_upload/latest

Test location	/workspace/coverage/default/34.spi_device_alert_test.1549938144
Short name	T761
Test name
Test status
Simulation time	34051151 ps
CPU time	0.67 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:46:49 PM PDT 24
Peak memory	204660 kb
Host	smart-69438a23-c3ff-4afb-8f2a-4313407fb42f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549938144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 1549938144
Directory	/workspace/34.spi_device_alert_test/latest

Test location	/workspace/coverage/default/34.spi_device_cfg_cmd.2201781199
Short name	T583
Test name
Test status
Simulation time	154170251 ps
CPU time	3.1 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:46:55 PM PDT 24
Peak memory	218996 kb
Host	smart-8b0f8475-9dfa-4048-9e9b-24ec2bc59985
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201781199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2201781199
Directory	/workspace/34.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/34.spi_device_csb_read.1593904338
Short name	T19
Test name
Test status
Simulation time	36883079 ps
CPU time	0.72 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:46:49 PM PDT 24
Peak memory	205464 kb
Host	smart-55fc3c0c-21c7-42c6-abf7-4dbeae8f46c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593904338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1593904338
Directory	/workspace/34.spi_device_csb_read/latest

Test location	/workspace/coverage/default/34.spi_device_flash_all.4184862442
Short name	T633
Test name
Test status
Simulation time	53675719 ps
CPU time	0.79 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:46:51 PM PDT 24
Peak memory	215808 kb
Host	smart-09aad760-1780-48c9-906e-6471cd8c3bea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184862442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4184862442
Directory	/workspace/34.spi_device_flash_all/latest

Test location	/workspace/coverage/default/34.spi_device_flash_and_tpm.3438772677
Short name	T503
Test name
Test status
Simulation time	1504470970 ps
CPU time	25.77 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:47:18 PM PDT 24
Peak memory	237684 kb
Host	smart-c0b7adc3-9816-4f39-973f-91ebf2f7a969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438772677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3438772677
Directory	/workspace/34.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2129826479
Short name	T32
Test name
Test status
Simulation time	139162403093 ps
CPU time	361.49 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:52:49 PM PDT 24
Peak memory	253176 kb
Host	smart-3deb9060-b68a-4023-82ff-3d5923ed6e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129826479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl e.2129826479
Directory	/workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/34.spi_device_flash_mode.3076143497
Short name	T741
Test name
Test status
Simulation time	81756223 ps
CPU time	4.28 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:54 PM PDT 24
Peak memory	232480 kb
Host	smart-7500dc28-ea85-43e6-be20-84c13a0a2d3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076143497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3076143497
Directory	/workspace/34.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/34.spi_device_intercept.2926245773
Short name	T172
Test name
Test status
Simulation time	2747952353 ps
CPU time	14.2 seconds
Started	May 23 02:46:46 PM PDT 24
Finished	May 23 02:47:01 PM PDT 24
Peak memory	234132 kb
Host	smart-32891da3-de00-4518-9319-9a6f83b53a82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926245773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2926245773
Directory	/workspace/34.spi_device_intercept/latest

Test location	/workspace/coverage/default/34.spi_device_mailbox.1680587749
Short name	T934
Test name
Test status
Simulation time	828085661 ps
CPU time	12.12 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:47:02 PM PDT 24
Peak memory	232564 kb
Host	smart-74c05295-5da3-4da1-aa8a-5b9fe6f9af93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680587749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1680587749
Directory	/workspace/34.spi_device_mailbox/latest

Test location	/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.620169034
Short name	T396
Test name
Test status
Simulation time	108231288 ps
CPU time	2.35 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:46:55 PM PDT 24
Peak memory	215964 kb
Host	smart-dc185c72-fae5-43ea-ad42-a8da83571f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620169034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap .620169034
Directory	/workspace/34.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/34.spi_device_pass_cmd_filtering.2471796465
Short name	T382
Test name
Test status
Simulation time	765357316 ps
CPU time	3.07 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:46:51 PM PDT 24
Peak memory	233248 kb
Host	smart-2f0c50f3-c43e-4714-8d89-37a98f1c8304
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471796465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2471796465
Directory	/workspace/34.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/34.spi_device_read_buffer_direct.4086322985
Short name	T573
Test name
Test status
Simulation time	3864457993 ps
CPU time	9.69 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:59 PM PDT 24
Peak memory	222920 kb
Host	smart-45471ef0-33cb-4e34-9b75-ef4d4f8a511c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4086322985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.4086322985
Directory	/workspace/34.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/34.spi_device_stress_all.1889649476
Short name	T154
Test name
Test status
Simulation time	79107607265 ps
CPU time	732.42 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:59:01 PM PDT 24
Peak memory	273696 kb
Host	smart-3b027208-ba31-46a0-9640-2d046e9fd169
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889649476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre ss_all.1889649476
Directory	/workspace/34.spi_device_stress_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_all.2532131091
Short name	T688
Test name
Test status
Simulation time	24109515432 ps
CPU time	9.44 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:47:00 PM PDT 24
Peak memory	216128 kb
Host	smart-905da09c-0695-4b3a-9854-e6116b053507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532131091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2532131091
Directory	/workspace/34.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1982815813
Short name	T867
Test name
Test status
Simulation time	103133285 ps
CPU time	0.72 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:50 PM PDT 24
Peak memory	205616 kb
Host	smart-4b3c7ef6-9090-4954-8c82-ae5a73099d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982815813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1982815813
Directory	/workspace/34.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_rw.3860681348
Short name	T313
Test name
Test status
Simulation time	52210014 ps
CPU time	2.05 seconds
Started	May 23 02:46:52 PM PDT 24
Finished	May 23 02:46:55 PM PDT 24
Peak memory	216224 kb
Host	smart-fd5c3933-1c69-4ff9-bb90-2dbf2cc64894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860681348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3860681348
Directory	/workspace/34.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_sts_read.550248790
Short name	T774
Test name
Test status
Simulation time	100648052 ps
CPU time	1.04 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:46:53 PM PDT 24
Peak memory	206736 kb
Host	smart-3fa12eeb-faa6-4704-8fad-ba5cbec32e05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550248790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.550248790
Directory	/workspace/34.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/34.spi_device_upload.2985160477
Short name	T527
Test name
Test status
Simulation time	44460817734 ps
CPU time	19.42 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:47:11 PM PDT 24
Peak memory	232592 kb
Host	smart-7026e820-90de-47ed-9e10-ee318d54fb1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985160477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2985160477
Directory	/workspace/34.spi_device_upload/latest

Test location	/workspace/coverage/default/35.spi_device_alert_test.2301116479
Short name	T552
Test name
Test status
Simulation time	21657106 ps
CPU time	0.73 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:03 PM PDT 24
Peak memory	204724 kb
Host	smart-bbb6ee17-0264-4430-8662-86ab7f1e6995
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301116479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test. 2301116479
Directory	/workspace/35.spi_device_alert_test/latest

Test location	/workspace/coverage/default/35.spi_device_cfg_cmd.2758491379
Short name	T241
Test name
Test status
Simulation time	530455535 ps
CPU time	10.43 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:47:00 PM PDT 24
Peak memory	220948 kb
Host	smart-ea47ea6a-2414-4199-a90f-7dfa7befbaf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758491379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2758491379
Directory	/workspace/35.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/35.spi_device_csb_read.2048063627
Short name	T623
Test name
Test status
Simulation time	18049073 ps
CPU time	0.77 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:51 PM PDT 24
Peak memory	205792 kb
Host	smart-d367f45e-f813-4080-8ac6-93258a6b4dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048063627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2048063627
Directory	/workspace/35.spi_device_csb_read/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm.1406110474
Short name	T440
Test name
Test status
Simulation time	9344343735 ps
CPU time	30.3 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:34 PM PDT 24
Peak memory	238180 kb
Host	smart-2340966b-4b79-4b6e-9b0b-866171d41b68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406110474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1406110474
Directory	/workspace/35.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.368867959
Short name	T33
Test name
Test status
Simulation time	5005870240 ps
CPU time	49.12 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:52 PM PDT 24
Peak memory	249232 kb
Host	smart-5141be36-c791-4e11-9358-2712ff5d0159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368867959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle .368867959
Directory	/workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/35.spi_device_flash_mode.3274725984
Short name	T350
Test name
Test status
Simulation time	4090760871 ps
CPU time	5.11 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:46:56 PM PDT 24
Peak memory	232612 kb
Host	smart-a0b35279-1e4e-485b-8fbf-ceacd79694aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274725984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3274725984
Directory	/workspace/35.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/35.spi_device_intercept.643345327
Short name	T659
Test name
Test status
Simulation time	5027629077 ps
CPU time	15.03 seconds
Started	May 23 02:46:52 PM PDT 24
Finished	May 23 02:47:09 PM PDT 24
Peak memory	219548 kb
Host	smart-bbd4203d-42cb-4a70-83fb-a2afada355d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643345327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.643345327
Directory	/workspace/35.spi_device_intercept/latest

Test location	/workspace/coverage/default/35.spi_device_mailbox.3794717532
Short name	T839
Test name
Test status
Simulation time	1931877874 ps
CPU time	5.73 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:55 PM PDT 24
Peak memory	218744 kb
Host	smart-cc9dcee4-7795-4750-95f9-02e0b776e88f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794717532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3794717532
Directory	/workspace/35.spi_device_mailbox/latest

Test location	/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2532502362
Short name	T252
Test name
Test status
Simulation time	160648500 ps
CPU time	4.24 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:46:54 PM PDT 24
Peak memory	233396 kb
Host	smart-75204c09-be51-4095-ad84-0a5d3ea44574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532502362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.2532502362
Directory	/workspace/35.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/35.spi_device_pass_cmd_filtering.2569760393
Short name	T756
Test name
Test status
Simulation time	1254341765 ps
CPU time	5.13 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:46:53 PM PDT 24
Peak memory	233560 kb
Host	smart-5525c90a-d7a8-4a4c-a5d4-365e922029b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569760393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2569760393
Directory	/workspace/35.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/35.spi_device_read_buffer_direct.365464265
Short name	T691
Test name
Test status
Simulation time	1714117569 ps
CPU time	5.67 seconds
Started	May 23 02:46:52 PM PDT 24
Finished	May 23 02:46:59 PM PDT 24
Peak memory	219216 kb
Host	smart-8beb4795-08f5-4a5c-bbed-fe35ab1dcbd6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=365464265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire ct.365464265
Directory	/workspace/35.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/35.spi_device_stress_all.4294864687
Short name	T150
Test name
Test status
Simulation time	5879194155 ps
CPU time	33.91 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:36 PM PDT 24
Peak memory	240896 kb
Host	smart-ea4d42fe-81e5-4d5b-b871-1602808101fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294864687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre ss_all.4294864687
Directory	/workspace/35.spi_device_stress_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_all.2409858774
Short name	T291
Test name
Test status
Simulation time	2909796916 ps
CPU time	22.84 seconds
Started	May 23 02:46:48 PM PDT 24
Finished	May 23 02:47:12 PM PDT 24
Peak memory	216276 kb
Host	smart-1c742613-2cfd-44c3-83fc-8707f6cfb813
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409858774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2409858774
Directory	/workspace/35.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1004816248
Short name	T328
Test name
Test status
Simulation time	9177459414 ps
CPU time	26.75 seconds
Started	May 23 02:46:47 PM PDT 24
Finished	May 23 02:47:14 PM PDT 24
Peak memory	215976 kb
Host	smart-0bbc1b5b-9f97-4c4a-83f2-f8107fb10cfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004816248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1004816248
Directory	/workspace/35.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_rw.3390455191
Short name	T21
Test name
Test status
Simulation time	47824827 ps
CPU time	1.35 seconds
Started	May 23 02:46:49 PM PDT 24
Finished	May 23 02:46:52 PM PDT 24
Peak memory	216088 kb
Host	smart-9695604d-2049-4f61-9891-02725166ba26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390455191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3390455191
Directory	/workspace/35.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_sts_read.2651488864
Short name	T301
Test name
Test status
Simulation time	244179359 ps
CPU time	0.91 seconds
Started	May 23 02:46:51 PM PDT 24
Finished	May 23 02:46:53 PM PDT 24
Peak memory	205712 kb
Host	smart-9292bf90-a883-4879-9189-6f5bc1e25400
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651488864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2651488864
Directory	/workspace/35.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/35.spi_device_upload.1313945837
Short name	T469
Test name
Test status
Simulation time	924253214 ps
CPU time	4.42 seconds
Started	May 23 02:46:50 PM PDT 24
Finished	May 23 02:46:56 PM PDT 24
Peak memory	226728 kb
Host	smart-6f30f297-a645-4136-be0a-1a51916648f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313945837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1313945837
Directory	/workspace/35.spi_device_upload/latest

Test location	/workspace/coverage/default/36.spi_device_alert_test.3477588045
Short name	T379
Test name
Test status
Simulation time	41723245 ps
CPU time	0.72 seconds
Started	May 23 02:47:14 PM PDT 24
Finished	May 23 02:47:16 PM PDT 24
Peak memory	204732 kb
Host	smart-342ed5c2-5b63-4369-aa34-beb2057cb182
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477588045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test. 3477588045
Directory	/workspace/36.spi_device_alert_test/latest

Test location	/workspace/coverage/default/36.spi_device_cfg_cmd.2834583810
Short name	T461
Test name
Test status
Simulation time	1427860938 ps
CPU time	14.96 seconds
Started	May 23 02:47:04 PM PDT 24
Finished	May 23 02:47:20 PM PDT 24
Peak memory	218588 kb
Host	smart-c63c88ce-4125-4109-9629-84a37ecc476e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834583810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2834583810
Directory	/workspace/36.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/36.spi_device_csb_read.2050072024
Short name	T776
Test name
Test status
Simulation time	19483934 ps
CPU time	0.79 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:05 PM PDT 24
Peak memory	205396 kb
Host	smart-0f8b2cf8-3e56-4666-ab91-b142597972a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050072024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2050072024
Directory	/workspace/36.spi_device_csb_read/latest

Test location	/workspace/coverage/default/36.spi_device_flash_all.1360650407
Short name	T727
Test name
Test status
Simulation time	200992983 ps
CPU time	4.13 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:07 PM PDT 24
Peak memory	234252 kb
Host	smart-c2c66ebd-297b-4722-b3bc-14cb5d419c10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360650407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1360650407
Directory	/workspace/36.spi_device_flash_all/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm.2830107139
Short name	T747
Test name
Test status
Simulation time	74860203292 ps
CPU time	326.56 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:52:31 PM PDT 24
Peak memory	250164 kb
Host	smart-a5f27e65-63a3-4bf9-bd59-f2439ebf95f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830107139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2830107139
Directory	/workspace/36.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/36.spi_device_flash_mode.1007448588
Short name	T212
Test name
Test status
Simulation time	10818929462 ps
CPU time	33.85 seconds
Started	May 23 02:47:04 PM PDT 24
Finished	May 23 02:47:39 PM PDT 24
Peak memory	249032 kb
Host	smart-1592d716-abb0-406a-b361-86a1fc2cd557
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007448588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1007448588
Directory	/workspace/36.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/36.spi_device_intercept.4005318710
Short name	T924
Test name
Test status
Simulation time	2432546739 ps
CPU time	7.41 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:10 PM PDT 24
Peak memory	219476 kb
Host	smart-c8607d47-c02a-4620-8180-2e9a18d5cf78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005318710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4005318710
Directory	/workspace/36.spi_device_intercept/latest

Test location	/workspace/coverage/default/36.spi_device_mailbox.1004601891
Short name	T591
Test name
Test status
Simulation time	623487612 ps
CPU time	7.51 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:11 PM PDT 24
Peak memory	218432 kb
Host	smart-dc727ceb-0f3a-4e46-b93b-5b2ab3601257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004601891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1004601891
Directory	/workspace/36.spi_device_mailbox/latest

Test location	/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1965507172
Short name	T643
Test name
Test status
Simulation time	1596110388 ps
CPU time	3.31 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:07 PM PDT 24
Peak memory	218400 kb
Host	smart-f97134b1-1ba8-49aa-af05-7e7e3b88b6ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965507172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa p.1965507172
Directory	/workspace/36.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/36.spi_device_pass_cmd_filtering.2148933940
Short name	T174
Test name
Test status
Simulation time	1314932132 ps
CPU time	5.57 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:09 PM PDT 24
Peak memory	218292 kb
Host	smart-d1e87a01-3fe1-4b66-8a42-c5277f8dea02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148933940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2148933940
Directory	/workspace/36.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/36.spi_device_read_buffer_direct.3572442008
Short name	T320
Test name
Test status
Simulation time	737962415 ps
CPU time	5 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:08 PM PDT 24
Peak memory	222288 kb
Host	smart-a38f4840-5a9d-491a-a4a3-97ae4c5f1254
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3572442008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.3572442008
Directory	/workspace/36.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/36.spi_device_stress_all.391445625
Short name	T217
Test name
Test status
Simulation time	406323767320 ps
CPU time	766.13 seconds
Started	May 23 02:47:17 PM PDT 24
Finished	May 23 03:00:05 PM PDT 24
Peak memory	263528 kb
Host	smart-f70387e8-0bb5-4301-816e-d78df113fa61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391445625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres s_all.391445625
Directory	/workspace/36.spi_device_stress_all/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_all.2926862031
Short name	T851
Test name
Test status
Simulation time	1040638565 ps
CPU time	15.1 seconds
Started	May 23 02:47:03 PM PDT 24
Finished	May 23 02:47:20 PM PDT 24
Peak memory	219780 kb
Host	smart-f855f29c-a66c-4d26-a0dd-72348bf40675
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926862031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2926862031
Directory	/workspace/36.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4252949898
Short name	T353
Test name
Test status
Simulation time	11957607 ps
CPU time	0.79 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:04 PM PDT 24
Peak memory	205556 kb
Host	smart-d86a9e43-d056-4a92-8669-ccf350477269
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252949898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4252949898
Directory	/workspace/36.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_rw.1897737394
Short name	T417
Test name
Test status
Simulation time	29147829 ps
CPU time	1.94 seconds
Started	May 23 02:47:01 PM PDT 24
Finished	May 23 02:47:04 PM PDT 24
Peak memory	216180 kb
Host	smart-fbde2d4e-6c7f-474f-808e-6ceb6c8cec72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897737394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1897737394
Directory	/workspace/36.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_sts_read.1246296187
Short name	T790
Test name
Test status
Simulation time	20170162 ps
CPU time	0.82 seconds
Started	May 23 02:47:00 PM PDT 24
Finished	May 23 02:47:03 PM PDT 24
Peak memory	205764 kb
Host	smart-bb201570-9872-4485-91cc-10b6053ed022
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246296187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1246296187
Directory	/workspace/36.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/36.spi_device_upload.2117997607
Short name	T418
Test name
Test status
Simulation time	235863485 ps
CPU time	5.07 seconds
Started	May 23 02:47:02 PM PDT 24
Finished	May 23 02:47:09 PM PDT 24
Peak memory	234024 kb
Host	smart-3e15c6d4-5844-4ea5-8c9f-fc08b6a3cc89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117997607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2117997607
Directory	/workspace/36.spi_device_upload/latest

Test location	/workspace/coverage/default/37.spi_device_alert_test.3554829550
Short name	T477
Test name
Test status
Simulation time	98965299 ps
CPU time	0.74 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:38 PM PDT 24
Peak memory	205228 kb
Host	smart-36b2a247-80c4-45b2-b871-a97a8ea41241
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554829550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test. 3554829550
Directory	/workspace/37.spi_device_alert_test/latest

Test location	/workspace/coverage/default/37.spi_device_cfg_cmd.1149101486
Short name	T647
Test name
Test status
Simulation time	209786027 ps
CPU time	2.64 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:40 PM PDT 24
Peak memory	235604 kb
Host	smart-71cd0af5-6551-480f-9e91-fca36e13120c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149101486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1149101486
Directory	/workspace/37.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/37.spi_device_csb_read.1488231922
Short name	T568
Test name
Test status
Simulation time	18414850 ps
CPU time	0.77 seconds
Started	May 23 02:47:16 PM PDT 24
Finished	May 23 02:47:18 PM PDT 24
Peak memory	205448 kb
Host	smart-02968303-89aa-4c00-afbf-3ec11a168c26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488231922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1488231922
Directory	/workspace/37.spi_device_csb_read/latest

Test location	/workspace/coverage/default/37.spi_device_flash_all.2743644856
Short name	T880
Test name
Test status
Simulation time	32017662246 ps
CPU time	36.5 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:48:12 PM PDT 24
Peak memory	236564 kb
Host	smart-e26900f3-c58e-428a-8c18-6622345cb699
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743644856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2743644856
Directory	/workspace/37.spi_device_flash_all/latest

Test location	/workspace/coverage/default/37.spi_device_flash_and_tpm.1354204407
Short name	T557
Test name
Test status
Simulation time	29048384169 ps
CPU time	162.88 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:50:20 PM PDT 24
Peak memory	257196 kb
Host	smart-9001a4cd-9f92-4b28-90eb-23a6c01217be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354204407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1354204407
Directory	/workspace/37.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4079212096
Short name	T65
Test name
Test status
Simulation time	11849659884 ps
CPU time	106.96 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:49:25 PM PDT 24
Peak memory	254884 kb
Host	smart-e2e331ab-df41-4e5c-a357-d854d863525a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079212096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl e.4079212096
Directory	/workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/37.spi_device_flash_mode.919864949
Short name	T523
Test name
Test status
Simulation time	340750707 ps
CPU time	10.76 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:47:46 PM PDT 24
Peak memory	248980 kb
Host	smart-a4958aea-6c04-4672-a771-9215135dd439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919864949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.919864949
Directory	/workspace/37.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/37.spi_device_intercept.773011588
Short name	T664
Test name
Test status
Simulation time	1748205255 ps
CPU time	7.79 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:46 PM PDT 24
Peak memory	218460 kb
Host	smart-c0bed332-39ac-4d31-b05b-1f19ecdf1360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773011588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.773011588
Directory	/workspace/37.spi_device_intercept/latest

Test location	/workspace/coverage/default/37.spi_device_mailbox.3091249284
Short name	T801
Test name
Test status
Simulation time	4075545133 ps
CPU time	35.74 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:48:14 PM PDT 24
Peak memory	224376 kb
Host	smart-94941e0f-2bd1-4c54-931e-e42e77d87098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091249284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3091249284
Directory	/workspace/37.spi_device_mailbox/latest

Test location	/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1067593502
Short name	T405
Test name
Test status
Simulation time	1814559145 ps
CPU time	5.92 seconds
Started	May 23 02:47:37 PM PDT 24
Finished	May 23 02:47:44 PM PDT 24
Peak memory	218492 kb
Host	smart-01ec8787-8c5c-483f-a2c0-df4fdd17b075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067593502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa p.1067593502
Directory	/workspace/37.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/37.spi_device_pass_cmd_filtering.647359312
Short name	T947
Test name
Test status
Simulation time	14523649991 ps
CPU time	11.3 seconds
Started	May 23 02:47:38 PM PDT 24
Finished	May 23 02:47:51 PM PDT 24
Peak memory	236080 kb
Host	smart-c61cc7c5-e8de-4656-9ae5-ec04fb607bcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647359312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.647359312
Directory	/workspace/37.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/37.spi_device_read_buffer_direct.3455541379
Short name	T700
Test name
Test status
Simulation time	280726152 ps
CPU time	4.35 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:42 PM PDT 24
Peak memory	220028 kb
Host	smart-276f5a2c-4bcc-4f41-b0e3-478b6f11b823
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3455541379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.3455541379
Directory	/workspace/37.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_all.3083811059
Short name	T607
Test name
Test status
Simulation time	14908943561 ps
CPU time	20.12 seconds
Started	May 23 02:47:17 PM PDT 24
Finished	May 23 02:47:39 PM PDT 24
Peak memory	216228 kb
Host	smart-7e64e6e9-6357-4567-b123-940bb163a411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083811059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3083811059
Directory	/workspace/37.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.101975099
Short name	T298
Test name
Test status
Simulation time	723675272 ps
CPU time	3.55 seconds
Started	May 23 02:47:15 PM PDT 24
Finished	May 23 02:47:20 PM PDT 24
Peak memory	216088 kb
Host	smart-01edd198-5adb-48a5-aea0-4f923b7e1af5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101975099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.101975099
Directory	/workspace/37.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_rw.852281509
Short name	T290
Test name
Test status
Simulation time	97114564 ps
CPU time	1.24 seconds
Started	May 23 02:47:34 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	207972 kb
Host	smart-ef474269-997a-48e6-a936-a81af906ea1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852281509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.852281509
Directory	/workspace/37.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_sts_read.2515920770
Short name	T570
Test name
Test status
Simulation time	280191583 ps
CPU time	0.75 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	205744 kb
Host	smart-a85e31be-ac64-4582-8b48-8ef1fb0ce5b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515920770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2515920770
Directory	/workspace/37.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/37.spi_device_upload.2637476327
Short name	T425
Test name
Test status
Simulation time	7092152633 ps
CPU time	8.53 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:45 PM PDT 24
Peak memory	235908 kb
Host	smart-cc655159-bfe7-4895-a575-9ca856036ce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637476327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2637476327
Directory	/workspace/37.spi_device_upload/latest

Test location	/workspace/coverage/default/38.spi_device_alert_test.1866147961
Short name	T475
Test name
Test status
Simulation time	17270034 ps
CPU time	0.7 seconds
Started	May 23 02:47:50 PM PDT 24
Finished	May 23 02:47:52 PM PDT 24
Peak memory	204768 kb
Host	smart-5d5b9b3d-76cc-4a44-9fb2-cdeb7c38abf8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866147961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test. 1866147961
Directory	/workspace/38.spi_device_alert_test/latest

Test location	/workspace/coverage/default/38.spi_device_cfg_cmd.2904411054
Short name	T904
Test name
Test status
Simulation time	526322419 ps
CPU time	4.29 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:42 PM PDT 24
Peak memory	233556 kb
Host	smart-9c6b8eec-1680-439a-94c5-bb4c4a2a205a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904411054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2904411054
Directory	/workspace/38.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/38.spi_device_csb_read.3625519577
Short name	T310
Test name
Test status
Simulation time	16753716 ps
CPU time	0.84 seconds
Started	May 23 02:47:38 PM PDT 24
Finished	May 23 02:47:40 PM PDT 24
Peak memory	206564 kb
Host	smart-96083608-74fc-4dbe-a5e5-718c1d96f90f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625519577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3625519577
Directory	/workspace/38.spi_device_csb_read/latest

Test location	/workspace/coverage/default/38.spi_device_flash_all.2693041216
Short name	T630
Test name
Test status
Simulation time	20462339029 ps
CPU time	68.14 seconds
Started	May 23 02:47:37 PM PDT 24
Finished	May 23 02:48:47 PM PDT 24
Peak memory	249148 kb
Host	smart-56ae77f1-360f-4968-82ae-860c1a41973e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693041216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2693041216
Directory	/workspace/38.spi_device_flash_all/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm.397007037
Short name	T837
Test name
Test status
Simulation time	2945326315 ps
CPU time	65.42 seconds
Started	May 23 02:47:37 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	252740 kb
Host	smart-bdca137b-1597-4b2d-8712-50243f056a63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397007037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.397007037
Directory	/workspace/38.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/38.spi_device_flash_mode.3974138958
Short name	T211
Test name
Test status
Simulation time	33876928 ps
CPU time	2.32 seconds
Started	May 23 02:47:38 PM PDT 24
Finished	May 23 02:47:42 PM PDT 24
Peak memory	224216 kb
Host	smart-680b6c5e-fa86-476b-aaf1-1ee1bb3fef9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974138958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3974138958
Directory	/workspace/38.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/38.spi_device_intercept.1864661536
Short name	T395
Test name
Test status
Simulation time	3465267521 ps
CPU time	10.68 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:48 PM PDT 24
Peak memory	219600 kb
Host	smart-0384ec3f-254a-4aec-abe8-ac1b51f31b5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864661536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1864661536
Directory	/workspace/38.spi_device_intercept/latest

Test location	/workspace/coverage/default/38.spi_device_mailbox.663836885
Short name	T956
Test name
Test status
Simulation time	6766108723 ps
CPU time	13.14 seconds
Started	May 23 02:47:37 PM PDT 24
Finished	May 23 02:47:52 PM PDT 24
Peak memory	222880 kb
Host	smart-b10de772-bf07-475b-814e-16f6cf4eaeb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663836885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.663836885
Directory	/workspace/38.spi_device_mailbox/latest

Test location	/workspace/coverage/default/38.spi_device_pass_cmd_filtering.657262655
Short name	T846
Test name
Test status
Simulation time	28089684590 ps
CPU time	18.46 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:47:55 PM PDT 24
Peak memory	219636 kb
Host	smart-4c3269b7-d1d4-4ec9-bff5-10d2b5ed2801
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657262655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.657262655
Directory	/workspace/38.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/38.spi_device_read_buffer_direct.1410102385
Short name	T763
Test name
Test status
Simulation time	1534449768 ps
CPU time	4.5 seconds
Started	May 23 02:47:34 PM PDT 24
Finished	May 23 02:47:40 PM PDT 24
Peak memory	222748 kb
Host	smart-20aa11b4-b531-40ba-a58b-72d5a78b3154
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1410102385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir ect.1410102385
Directory	/workspace/38.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/38.spi_device_stress_all.1932970899
Short name	T73
Test name
Test status
Simulation time	6707813624 ps
CPU time	24.66 seconds
Started	May 23 02:47:38 PM PDT 24
Finished	May 23 02:48:04 PM PDT 24
Peak memory	224324 kb
Host	smart-83e32c69-8160-432e-94a1-98e407cf7415
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932970899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre ss_all.1932970899
Directory	/workspace/38.spi_device_stress_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_all.2906161806
Short name	T828
Test name
Test status
Simulation time	7934462256 ps
CPU time	45.95 seconds
Started	May 23 02:47:38 PM PDT 24
Finished	May 23 02:48:26 PM PDT 24
Peak memory	216320 kb
Host	smart-1477c696-0878-4a22-a9a9-d5c41ab48820
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906161806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2906161806
Directory	/workspace/38.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1417869852
Short name	T60
Test name
Test status
Simulation time	404728456 ps
CPU time	1.77 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:47:38 PM PDT 24
Peak memory	207772 kb
Host	smart-5365b29c-4c67-4b32-8bd4-71dc29958d32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417869852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1417869852
Directory	/workspace/38.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_rw.4073162847
Short name	T858
Test name
Test status
Simulation time	74194813 ps
CPU time	1.12 seconds
Started	May 23 02:47:36 PM PDT 24
Finished	May 23 02:47:39 PM PDT 24
Peak memory	207708 kb
Host	smart-9038cf96-0c10-4c83-95d4-beec773a95cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073162847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4073162847
Directory	/workspace/38.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_sts_read.1054685557
Short name	T460
Test name
Test status
Simulation time	37961548 ps
CPU time	0.8 seconds
Started	May 23 02:47:35 PM PDT 24
Finished	May 23 02:47:37 PM PDT 24
Peak memory	205716 kb
Host	smart-f580fe6b-78ae-4ac3-8869-68b8a6bb397c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054685557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1054685557
Directory	/workspace/38.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/38.spi_device_upload.2747745189
Short name	T16
Test name
Test status
Simulation time	2084901751 ps
CPU time	7.53 seconds
Started	May 23 02:47:37 PM PDT 24
Finished	May 23 02:47:46 PM PDT 24
Peak memory	229128 kb
Host	smart-678362b8-eea7-42ea-a57a-2503f0317294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747745189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2747745189
Directory	/workspace/38.spi_device_upload/latest

Test location	/workspace/coverage/default/39.spi_device_alert_test.1428568867
Short name	T463
Test name
Test status
Simulation time	12136058 ps
CPU time	0.68 seconds
Started	May 23 02:47:42 PM PDT 24
Finished	May 23 02:47:44 PM PDT 24
Peak memory	204696 kb
Host	smart-770cb8c5-7b57-48c6-9759-92db34e8e804
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428568867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test. 1428568867
Directory	/workspace/39.spi_device_alert_test/latest

Test location	/workspace/coverage/default/39.spi_device_cfg_cmd.2215055232
Short name	T950
Test name
Test status
Simulation time	84405519 ps
CPU time	2.5 seconds
Started	May 23 02:47:42 PM PDT 24
Finished	May 23 02:47:46 PM PDT 24
Peak memory	235460 kb
Host	smart-7b11794c-5ee2-4260-9396-8c29512cc71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215055232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2215055232
Directory	/workspace/39.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/39.spi_device_csb_read.1590939652
Short name	T371
Test name
Test status
Simulation time	97116016 ps
CPU time	0.75 seconds
Started	May 23 02:47:43 PM PDT 24
Finished	May 23 02:47:45 PM PDT 24
Peak memory	205464 kb
Host	smart-f6ab3616-bd8d-4275-887d-12c40152c0a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590939652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1590939652
Directory	/workspace/39.spi_device_csb_read/latest

Test location	/workspace/coverage/default/39.spi_device_flash_all.1045189313
Short name	T676
Test name
Test status
Simulation time	54049547766 ps
CPU time	97.56 seconds
Started	May 23 02:47:43 PM PDT 24
Finished	May 23 02:49:22 PM PDT 24
Peak memory	249032 kb
Host	smart-c438bcb2-e36e-45f9-ab38-46884221becf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045189313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1045189313
Directory	/workspace/39.spi_device_flash_all/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm.729992807
Short name	T197
Test name
Test status
Simulation time	21592128901 ps
CPU time	92.72 seconds
Started	May 23 02:47:44 PM PDT 24
Finished	May 23 02:49:18 PM PDT 24
Peak memory	253444 kb
Host	smart-1cbf6212-57d2-48d3-816a-eb1cd1783ca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729992807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.729992807
Directory	/workspace/39.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/39.spi_device_flash_mode.234257663
Short name	T377
Test name
Test status
Simulation time	1813037824 ps
CPU time	28.48 seconds
Started	May 23 02:47:43 PM PDT 24
Finished	May 23 02:48:12 PM PDT 24
Peak memory	237612 kb
Host	smart-75eb1aac-bfba-4579-aa82-956ea0bcbe71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234257663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.234257663
Directory	/workspace/39.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/39.spi_device_intercept.1493562802
Short name	T349
Test name
Test status
Simulation time	1216387350 ps
CPU time	17.42 seconds
Started	May 23 02:47:44 PM PDT 24
Finished	May 23 02:48:02 PM PDT 24
Peak memory	218404 kb
Host	smart-262dee6d-e93d-4a5d-a656-db53e4800240
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493562802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1493562802
Directory	/workspace/39.spi_device_intercept/latest

Test location	/workspace/coverage/default/39.spi_device_mailbox.1509321288
Short name	T237
Test name
Test status
Simulation time	297765193 ps
CPU time	3.72 seconds
Started	May 23 02:47:42 PM PDT 24
Finished	May 23 02:47:47 PM PDT 24
Peak memory	234484 kb
Host	smart-e161838b-ba24-4ce7-bccd-63860bd2922a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509321288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1509321288
Directory	/workspace/39.spi_device_mailbox/latest

Test location	/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2313020538
Short name	T576
Test name
Test status
Simulation time	218740267 ps
CPU time	2.3 seconds
Started	May 23 02:47:44 PM PDT 24
Finished	May 23 02:47:47 PM PDT 24
Peak memory	218392 kb
Host	smart-88b35dc1-8143-4536-8c9a-b874eb785309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313020538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa p.2313020538
Directory	/workspace/39.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/39.spi_device_pass_cmd_filtering.3994564109
Short name	T37
Test name
Test status
Simulation time	6467164296 ps
CPU time	15.68 seconds
Started	May 23 02:47:47 PM PDT 24
Finished	May 23 02:48:04 PM PDT 24
Peak memory	240784 kb
Host	smart-3e890610-3c44-4a69-8980-58b8a63cd2e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994564109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3994564109
Directory	/workspace/39.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/39.spi_device_read_buffer_direct.836665872
Short name	T767
Test name
Test status
Simulation time	456055196 ps
CPU time	4.26 seconds
Started	May 23 02:47:49 PM PDT 24
Finished	May 23 02:47:54 PM PDT 24
Peak memory	222096 kb
Host	smart-c235ae66-da3e-4306-a080-09bc8373bcd3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=836665872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire ct.836665872
Directory	/workspace/39.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/39.spi_device_stress_all.548987372
Short name	T273
Test name
Test status
Simulation time	5091030037 ps
CPU time	65.92 seconds
Started	May 23 02:47:47 PM PDT 24
Finished	May 23 02:48:54 PM PDT 24
Peak memory	256976 kb
Host	smart-79e10aa4-6152-4af8-ac6f-8917b05be20f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548987372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres s_all.548987372
Directory	/workspace/39.spi_device_stress_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_all.2712495706
Short name	T814
Test name
Test status
Simulation time	37376667800 ps
CPU time	51.49 seconds
Started	May 23 02:47:43 PM PDT 24
Finished	May 23 02:48:36 PM PDT 24
Peak memory	216308 kb
Host	smart-cc4a4364-1d6d-46f8-8ab4-3c4db80db90c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712495706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2712495706
Directory	/workspace/39.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2874000897
Short name	T130
Test name
Test status
Simulation time	965487977 ps
CPU time	7.44 seconds
Started	May 23 02:47:42 PM PDT 24
Finished	May 23 02:47:50 PM PDT 24
Peak memory	216012 kb
Host	smart-dd233cba-fac2-40a1-b0b8-bfe26401bea0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874000897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2874000897
Directory	/workspace/39.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_rw.1995502158
Short name	T330
Test name
Test status
Simulation time	32687562 ps
CPU time	1.15 seconds
Started	May 23 02:47:42 PM PDT 24
Finished	May 23 02:47:44 PM PDT 24
Peak memory	207860 kb
Host	smart-1c30a3c3-c5e7-41f1-b682-462b36f07715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995502158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1995502158
Directory	/workspace/39.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_sts_read.2032628819
Short name	T496
Test name
Test status
Simulation time	199424672 ps
CPU time	0.86 seconds
Started	May 23 02:47:50 PM PDT 24
Finished	May 23 02:47:53 PM PDT 24
Peak memory	205732 kb
Host	smart-27d611c1-1ebc-435e-90a0-c7ad9516a493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032628819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2032628819
Directory	/workspace/39.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/39.spi_device_upload.2360757065
Short name	T882
Test name
Test status
Simulation time	112529997 ps
CPU time	2.34 seconds
Started	May 23 02:47:51 PM PDT 24
Finished	May 23 02:47:54 PM PDT 24
Peak memory	216260 kb
Host	smart-6c45a191-dd04-45a1-99fd-4ab3d024d090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360757065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2360757065
Directory	/workspace/39.spi_device_upload/latest

Test location	/workspace/coverage/default/4.spi_device_alert_test.3116769317
Short name	T68
Test name
Test status
Simulation time	14751126 ps
CPU time	0.73 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:36 PM PDT 24
Peak memory	205620 kb
Host	smart-e0250335-7af7-448e-8ac3-b22b047dfede
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116769317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3 116769317
Directory	/workspace/4.spi_device_alert_test/latest

Test location	/workspace/coverage/default/4.spi_device_cfg_cmd.4255832156
Short name	T300
Test name
Test status
Simulation time	418599381 ps
CPU time	2.28 seconds
Started	May 23 02:41:25 PM PDT 24
Finished	May 23 02:41:28 PM PDT 24
Peak memory	215984 kb
Host	smart-5f8b834e-7d55-4549-b685-265f26391029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255832156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4255832156
Directory	/workspace/4.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/4.spi_device_csb_read.323592738
Short name	T606
Test name
Test status
Simulation time	15245013 ps
CPU time	0.77 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:41:25 PM PDT 24
Peak memory	206468 kb
Host	smart-1ffe7811-b9c0-4180-83e6-3b622bdfb95d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323592738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.323592738
Directory	/workspace/4.spi_device_csb_read/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm.832633494
Short name	T18
Test name
Test status
Simulation time	2888768522 ps
CPU time	15.4 seconds
Started	May 23 02:41:23 PM PDT 24
Finished	May 23 02:41:39 PM PDT 24
Peak memory	217568 kb
Host	smart-78c77384-7a9d-4951-865b-72208c6e78c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832633494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.832633494
Directory	/workspace/4.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2695895356
Short name	T43
Test name
Test status
Simulation time	3786577923 ps
CPU time	45.63 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:42:11 PM PDT 24
Peak memory	250316 kb
Host	smart-89c85fb8-e82b-4ab4-aae9-67ee4929321d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695895356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle .2695895356
Directory	/workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/4.spi_device_flash_mode.1756331054
Short name	T812
Test name
Test status
Simulation time	1161043638 ps
CPU time	15.6 seconds
Started	May 23 02:41:25 PM PDT 24
Finished	May 23 02:41:41 PM PDT 24
Peak memory	248828 kb
Host	smart-4ab980ad-980f-4bae-a405-640d8ca1cd62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756331054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1756331054
Directory	/workspace/4.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/4.spi_device_intercept.3238830165
Short name	T510
Test name
Test status
Simulation time	292152098 ps
CPU time	4.21 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:41:29 PM PDT 24
Peak memory	218236 kb
Host	smart-3d19da64-1d80-440d-8dd0-17a6fd37e143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238830165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3238830165
Directory	/workspace/4.spi_device_intercept/latest

Test location	/workspace/coverage/default/4.spi_device_mailbox.1753715157
Short name	T352
Test name
Test status
Simulation time	2723735559 ps
CPU time	4.28 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:41:29 PM PDT 24
Peak memory	218560 kb
Host	smart-5c60ae5a-c9de-49bf-a491-6f778cce1e0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753715157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1753715157
Directory	/workspace/4.spi_device_mailbox/latest

Test location	/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2184615952
Short name	T262
Test name
Test status
Simulation time	1537312535 ps
CPU time	6.92 seconds
Started	May 23 02:41:23 PM PDT 24
Finished	May 23 02:41:30 PM PDT 24
Peak memory	240188 kb
Host	smart-c02982a9-d4b1-4c28-a6ab-cb1d6d57c4a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184615952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap .2184615952
Directory	/workspace/4.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/4.spi_device_pass_cmd_filtering.2049764050
Short name	T462
Test name
Test status
Simulation time	744696457 ps
CPU time	6.17 seconds
Started	May 23 02:41:22 PM PDT 24
Finished	May 23 02:41:29 PM PDT 24
Peak memory	233636 kb
Host	smart-7ddb15f7-d203-414f-900c-37653580116c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049764050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2049764050
Directory	/workspace/4.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_read_buffer_direct.2044438431
Short name	T12
Test name
Test status
Simulation time	2828461101 ps
CPU time	18.35 seconds
Started	May 23 02:41:25 PM PDT 24
Finished	May 23 02:41:44 PM PDT 24
Peak memory	222836 kb
Host	smart-a9e87a44-2fc8-49c5-a176-0050cfc242d2
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2044438431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.2044438431
Directory	/workspace/4.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/4.spi_device_stress_all.602842655
Short name	T266
Test name
Test status
Simulation time	212448243996 ps
CPU time	275.8 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:46:01 PM PDT 24
Peak memory	263648 kb
Host	smart-8f478d88-62bc-4841-880e-a1c51cdd0a92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602842655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress _all.602842655
Directory	/workspace/4.spi_device_stress_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_all.3281072835
Short name	T493
Test name
Test status
Simulation time	4861864757 ps
CPU time	27.12 seconds
Started	May 23 02:41:22 PM PDT 24
Finished	May 23 02:41:50 PM PDT 24
Peak memory	219872 kb
Host	smart-087b4b78-d655-43c4-8558-a12237527631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281072835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3281072835
Directory	/workspace/4.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3538087907
Short name	T684
Test name
Test status
Simulation time	1544119247 ps
CPU time	5.05 seconds
Started	May 23 02:41:23 PM PDT 24
Finished	May 23 02:41:29 PM PDT 24
Peak memory	216016 kb
Host	smart-e22179d9-7a4f-457a-b2f6-fb88dac705fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538087907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3538087907
Directory	/workspace/4.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_rw.901911264
Short name	T890
Test name
Test status
Simulation time	169693827 ps
CPU time	2.72 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:41:28 PM PDT 24
Peak memory	216224 kb
Host	smart-b62682af-7307-4a09-91c9-a06642240e4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901911264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.901911264
Directory	/workspace/4.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_sts_read.4121324245
Short name	T434
Test name
Test status
Simulation time	257939857 ps
CPU time	0.96 seconds
Started	May 23 02:41:24 PM PDT 24
Finished	May 23 02:41:26 PM PDT 24
Peak memory	205732 kb
Host	smart-90819f01-80c7-4b4b-af2e-1efdf173cce6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121324245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4121324245
Directory	/workspace/4.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/4.spi_device_upload.3855149396
Short name	T260
Test name
Test status
Simulation time	3409620990 ps
CPU time	15.34 seconds
Started	May 23 02:41:23 PM PDT 24
Finished	May 23 02:41:39 PM PDT 24
Peak memory	233848 kb
Host	smart-2272dfed-5677-4ebd-a4a3-40f8266e4b4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855149396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3855149396
Directory	/workspace/4.spi_device_upload/latest

Test location	/workspace/coverage/default/40.spi_device_alert_test.2719283026
Short name	T920
Test name
Test status
Simulation time	13058104 ps
CPU time	0.71 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	205308 kb
Host	smart-9216b3af-dc01-44b5-9bcc-1dc0ab5a29f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719283026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test. 2719283026
Directory	/workspace/40.spi_device_alert_test/latest

Test location	/workspace/coverage/default/40.spi_device_cfg_cmd.974746504
Short name	T234
Test name
Test status
Simulation time	1329646334 ps
CPU time	11.99 seconds
Started	May 23 02:47:45 PM PDT 24
Finished	May 23 02:48:00 PM PDT 24
Peak memory	219824 kb
Host	smart-d9d6dcdc-60df-41ec-bea4-44ef94f42666
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974746504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.974746504
Directory	/workspace/40.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/40.spi_device_csb_read.689210431
Short name	T484
Test name
Test status
Simulation time	43204018 ps
CPU time	0.77 seconds
Started	May 23 02:47:51 PM PDT 24
Finished	May 23 02:47:53 PM PDT 24
Peak memory	206500 kb
Host	smart-a6190aa5-1d34-4f5f-89d5-8878107375cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689210431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.689210431
Directory	/workspace/40.spi_device_csb_read/latest

Test location	/workspace/coverage/default/40.spi_device_flash_all.3305387491
Short name	T926
Test name
Test status
Simulation time	19032034570 ps
CPU time	113.64 seconds
Started	May 23 02:47:46 PM PDT 24
Finished	May 23 02:49:42 PM PDT 24
Peak memory	254484 kb
Host	smart-b1754aa7-3b8b-4210-906d-86563fcef5a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305387491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3305387491
Directory	/workspace/40.spi_device_flash_all/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3755539785
Short name	T793
Test name
Test status
Simulation time	8169850236 ps
CPU time	118.85 seconds
Started	May 23 02:47:50 PM PDT 24
Finished	May 23 02:49:51 PM PDT 24
Peak memory	249116 kb
Host	smart-0dd684f7-d64f-48c9-8457-dba10b5d8a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755539785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl e.3755539785
Directory	/workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/40.spi_device_flash_mode.696470761
Short name	T511
Test name
Test status
Simulation time	1998809681 ps
CPU time	9.89 seconds
Started	May 23 02:47:46 PM PDT 24
Finished	May 23 02:47:58 PM PDT 24
Peak memory	224404 kb
Host	smart-53836449-8753-407f-90cf-8673c14b64d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696470761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.696470761
Directory	/workspace/40.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/40.spi_device_intercept.1924693519
Short name	T609
Test name
Test status
Simulation time	628467263 ps
CPU time	2.59 seconds
Started	May 23 02:47:47 PM PDT 24
Finished	May 23 02:47:51 PM PDT 24
Peak memory	233628 kb
Host	smart-4622c14a-f696-4a12-83a8-291d244cb324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924693519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1924693519
Directory	/workspace/40.spi_device_intercept/latest

Test location	/workspace/coverage/default/40.spi_device_mailbox.2614301499
Short name	T605
Test name
Test status
Simulation time	10257734638 ps
CPU time	20.11 seconds
Started	May 23 02:47:45 PM PDT 24
Finished	May 23 02:48:08 PM PDT 24
Peak memory	239780 kb
Host	smart-3cc18440-5a41-4557-8511-e6a38db2f0bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614301499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2614301499
Directory	/workspace/40.spi_device_mailbox/latest

Test location	/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.932638980
Short name	T198
Test name
Test status
Simulation time	133540970 ps
CPU time	3.64 seconds
Started	May 23 02:47:44 PM PDT 24
Finished	May 23 02:47:48 PM PDT 24
Peak memory	234552 kb
Host	smart-36c014b1-6b57-4375-8605-302834fed7d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932638980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap .932638980
Directory	/workspace/40.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1948294451
Short name	T860
Test name
Test status
Simulation time	26085165864 ps
CPU time	8.21 seconds
Started	May 23 02:47:43 PM PDT 24
Finished	May 23 02:47:52 PM PDT 24
Peak memory	233284 kb
Host	smart-64f5eebe-d621-4a3d-9f72-dedf8800fa1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948294451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1948294451
Directory	/workspace/40.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/40.spi_device_read_buffer_direct.1709246903
Short name	T367
Test name
Test status
Simulation time	2743556253 ps
CPU time	8.02 seconds
Started	May 23 02:47:41 PM PDT 24
Finished	May 23 02:47:50 PM PDT 24
Peak memory	218676 kb
Host	smart-21c9629f-a083-4e8d-ada8-0235f830d3b6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1709246903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir ect.1709246903
Directory	/workspace/40.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/40.spi_device_stress_all.1881868116
Short name	T875
Test name
Test status
Simulation time	125777122 ps
CPU time	1.21 seconds
Started	May 23 02:47:46 PM PDT 24
Finished	May 23 02:47:49 PM PDT 24
Peak memory	206964 kb
Host	smart-1d8d8ca2-a6dc-4ed5-a72c-f562a3f7d1a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881868116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre ss_all.1881868116
Directory	/workspace/40.spi_device_stress_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_all.3293924983
Short name	T356
Test name
Test status
Simulation time	23095632126 ps
CPU time	25.95 seconds
Started	May 23 02:47:50 PM PDT 24
Finished	May 23 02:48:18 PM PDT 24
Peak memory	216316 kb
Host	smart-e160c567-1b84-4e1c-b0b1-f1a34ffced0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293924983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3293924983
Directory	/workspace/40.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2769970291
Short name	T447
Test name
Test status
Simulation time	28771663960 ps
CPU time	12.94 seconds
Started	May 23 02:47:45 PM PDT 24
Finished	May 23 02:48:00 PM PDT 24
Peak memory	217420 kb
Host	smart-4ca88339-9c89-447f-bd5e-b38ac750ad5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769970291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2769970291
Directory	/workspace/40.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_rw.2314677086
Short name	T347
Test name
Test status
Simulation time	258021797 ps
CPU time	8.73 seconds
Started	May 23 02:47:44 PM PDT 24
Finished	May 23 02:47:55 PM PDT 24
Peak memory	216216 kb
Host	smart-a826b338-3725-443c-8503-bf2190ca972e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314677086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2314677086
Directory	/workspace/40.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_sts_read.595687812
Short name	T8
Test name
Test status
Simulation time	66105657 ps
CPU time	0.79 seconds
Started	May 23 02:47:49 PM PDT 24
Finished	May 23 02:47:51 PM PDT 24
Peak memory	205740 kb
Host	smart-7321cbbc-1136-48b6-84e8-78e882964d78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595687812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.595687812
Directory	/workspace/40.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/40.spi_device_upload.3390959586
Short name	T184
Test name
Test status
Simulation time	6242489090 ps
CPU time	13.32 seconds
Started	May 23 02:47:50 PM PDT 24
Finished	May 23 02:48:05 PM PDT 24
Peak memory	249012 kb
Host	smart-1c019ac3-9d48-4cfd-beae-27ea6c3526ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390959586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3390959586
Directory	/workspace/40.spi_device_upload/latest

Test location	/workspace/coverage/default/41.spi_device_alert_test.3425594312
Short name	T685
Test name
Test status
Simulation time	14368858 ps
CPU time	0.7 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:43 PM PDT 24
Peak memory	205280 kb
Host	smart-abca2d2a-933c-4d03-b2bd-f116bdb3f27e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425594312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test. 3425594312
Directory	/workspace/41.spi_device_alert_test/latest

Test location	/workspace/coverage/default/41.spi_device_cfg_cmd.538158918
Short name	T859
Test name
Test status
Simulation time	110446216 ps
CPU time	2.78 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	233180 kb
Host	smart-5756f32c-8add-4e92-b783-70f69f4549a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=538158918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.538158918
Directory	/workspace/41.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/41.spi_device_csb_read.1591313439
Short name	T542
Test name
Test status
Simulation time	37764480 ps
CPU time	0.8 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	205768 kb
Host	smart-c052b758-c134-4af4-846d-5e551c1fdb43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591313439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1591313439
Directory	/workspace/41.spi_device_csb_read/latest

Test location	/workspace/coverage/default/41.spi_device_flash_all.3186603284
Short name	T822
Test name
Test status
Simulation time	34374555739 ps
CPU time	52.63 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:49:39 PM PDT 24
Peak memory	256864 kb
Host	smart-f9ca9e9c-6cfd-4c05-bd1b-030fc7b0b5d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186603284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3186603284
Directory	/workspace/41.spi_device_flash_all/latest

Test location	/workspace/coverage/default/41.spi_device_flash_and_tpm.1263074063
Short name	T274
Test name
Test status
Simulation time	27682037948 ps
CPU time	293.86 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:53:40 PM PDT 24
Peak memory	250132 kb
Host	smart-b5183487-1c53-4030-b5a4-7ebc534664c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263074063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1263074063
Directory	/workspace/41.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1944476486
Short name	T927
Test name
Test status
Simulation time	5624414523 ps
CPU time	79.49 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:50:02 PM PDT 24
Peak memory	250392 kb
Host	smart-4e7fb49a-82db-4563-bfbe-2d61519bd859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944476486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl e.1944476486
Directory	/workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/41.spi_device_flash_mode.4170178528
Short name	T332
Test name
Test status
Simulation time	361019937 ps
CPU time	4.7 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:49 PM PDT 24
Peak memory	224348 kb
Host	smart-967aa718-99ae-4007-8423-6019e8a5944b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170178528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4170178528
Directory	/workspace/41.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/41.spi_device_intercept.695372279
Short name	T791
Test name
Test status
Simulation time	388303165 ps
CPU time	4.39 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:48:50 PM PDT 24
Peak memory	218432 kb
Host	smart-70d825ab-a5cd-4dcf-965f-73c1c8a84426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695372279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.695372279
Directory	/workspace/41.spi_device_intercept/latest

Test location	/workspace/coverage/default/41.spi_device_mailbox.81462261
Short name	T773
Test name
Test status
Simulation time	48861014874 ps
CPU time	57.06 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:49:40 PM PDT 24
Peak memory	231808 kb
Host	smart-841d4228-761d-49b1-9d2f-36a00b8095ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81462261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.81462261
Directory	/workspace/41.spi_device_mailbox/latest

Test location	/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.147849813
Short name	T387
Test name
Test status
Simulation time	416368293 ps
CPU time	2.33 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:47 PM PDT 24
Peak memory	216060 kb
Host	smart-6c90c05d-edc4-40ae-88eb-90bbcbd90a4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147849813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap .147849813
Directory	/workspace/41.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/41.spi_device_pass_cmd_filtering.2735756084
Short name	T246
Test name
Test status
Simulation time	7667141873 ps
CPU time	13.1 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:48:59 PM PDT 24
Peak memory	246764 kb
Host	smart-f44ce387-bf39-4235-91e4-73d4ed98301d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735756084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2735756084
Directory	/workspace/41.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/41.spi_device_read_buffer_direct.4079825510
Short name	T660
Test name
Test status
Simulation time	640635446 ps
CPU time	7.58 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:51 PM PDT 24
Peak memory	222740 kb
Host	smart-4aace98c-80a2-42f7-8af6-906b6c087132
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4079825510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir ect.4079825510
Directory	/workspace/41.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/41.spi_device_stress_all.480477847
Short name	T613
Test name
Test status
Simulation time	40429086 ps
CPU time	0.96 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:44 PM PDT 24
Peak memory	205588 kb
Host	smart-f7f0cdbe-f25d-4afb-bc68-867f1caa9f6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480477847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres s_all.480477847
Directory	/workspace/41.spi_device_stress_all/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_all.2857816826
Short name	T588
Test name
Test status
Simulation time	2195125301 ps
CPU time	30.81 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:49:17 PM PDT 24
Peak memory	216240 kb
Host	smart-1881459d-ac57-493f-b267-43906b2f4c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857816826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2857816826
Directory	/workspace/41.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2882511552
Short name	T656
Test name
Test status
Simulation time	36716963789 ps
CPU time	20.93 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:49:02 PM PDT 24
Peak memory	216168 kb
Host	smart-6a9fd2dc-15cd-4de5-b648-7143a44cbe26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882511552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2882511552
Directory	/workspace/41.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_rw.51919363
Short name	T292
Test name
Test status
Simulation time	281644499 ps
CPU time	1.57 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:45 PM PDT 24
Peak memory	216156 kb
Host	smart-036e9342-782e-474c-89d9-d6d8789d420b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51919363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.51919363
Directory	/workspace/41.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_sts_read.2034233217
Short name	T450
Test name
Test status
Simulation time	97368717 ps
CPU time	1.01 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:45 PM PDT 24
Peak memory	206264 kb
Host	smart-991e6e5e-f9d9-4b68-9788-58246579aa45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034233217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2034233217
Directory	/workspace/41.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/41.spi_device_upload.3183297547
Short name	T213
Test name
Test status
Simulation time	12522445132 ps
CPU time	21.95 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:49:03 PM PDT 24
Peak memory	240808 kb
Host	smart-d072072d-f095-4a26-9f23-d9564908c1b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183297547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3183297547
Directory	/workspace/41.spi_device_upload/latest

Test location	/workspace/coverage/default/42.spi_device_alert_test.4181782413
Short name	T357
Test name
Test status
Simulation time	11803640 ps
CPU time	0.72 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:48:41 PM PDT 24
Peak memory	204796 kb
Host	smart-27e40a7d-dcfc-4fcb-85b3-730ea9ab0e68
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181782413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test. 4181782413
Directory	/workspace/42.spi_device_alert_test/latest

Test location	/workspace/coverage/default/42.spi_device_cfg_cmd.1833531723
Short name	T488
Test name
Test status
Simulation time	82874346 ps
CPU time	3.45 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:46 PM PDT 24
Peak memory	233676 kb
Host	smart-884c702b-aa6f-4e88-9992-e9c52b135725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833531723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1833531723
Directory	/workspace/42.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/42.spi_device_csb_read.3166174067
Short name	T719
Test name
Test status
Simulation time	51311594 ps
CPU time	0.78 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:42 PM PDT 24
Peak memory	205512 kb
Host	smart-ede336b7-19e6-4c40-8508-b4eb4054f927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166174067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3166174067
Directory	/workspace/42.spi_device_csb_read/latest

Test location	/workspace/coverage/default/42.spi_device_flash_and_tpm.375093175
Short name	T726
Test name
Test status
Simulation time	2794403551 ps
CPU time	71.63 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:49:52 PM PDT 24
Peak memory	249176 kb
Host	smart-ec2dd832-41bd-4c97-8d19-d3d57c6bb17b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375093175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.375093175
Directory	/workspace/42.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3883400681
Short name	T559
Test name
Test status
Simulation time	2380518331 ps
CPU time	49.33 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:49:33 PM PDT 24
Peak memory	255192 kb
Host	smart-bd21f204-145c-4160-8df5-de169b46b0e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883400681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl e.3883400681
Directory	/workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/42.spi_device_intercept.3237683643
Short name	T762
Test name
Test status
Simulation time	315824611 ps
CPU time	4.06 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:48 PM PDT 24
Peak memory	233196 kb
Host	smart-c69f49a2-0199-4e87-b471-c337c2369dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237683643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3237683643
Directory	/workspace/42.spi_device_intercept/latest

Test location	/workspace/coverage/default/42.spi_device_mailbox.1579436817
Short name	T451
Test name
Test status
Simulation time	7085153062 ps
CPU time	71.36 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:49:53 PM PDT 24
Peak memory	247156 kb
Host	smart-79c975d6-ff21-4d9c-adee-751eae926fe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579436817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1579436817
Directory	/workspace/42.spi_device_mailbox/latest

Test location	/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2728870649
Short name	T734
Test name
Test status
Simulation time	702656976 ps
CPU time	5.64 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:49 PM PDT 24
Peak memory	218492 kb
Host	smart-a98ce226-bd90-4e05-a4d9-6cad700d5d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728870649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa p.2728870649
Directory	/workspace/42.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/42.spi_device_pass_cmd_filtering.1485248187
Short name	T617
Test name
Test status
Simulation time	2121077436 ps
CPU time	6.24 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:48 PM PDT 24
Peak memory	218684 kb
Host	smart-3a4d12ef-35da-491a-8fb8-71e1d6da3c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485248187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1485248187
Directory	/workspace/42.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/42.spi_device_read_buffer_direct.3260263387
Short name	T504
Test name
Test status
Simulation time	797228844 ps
CPU time	5.5 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:50 PM PDT 24
Peak memory	222780 kb
Host	smart-5e9232d8-9cd3-4a04-b4a7-1bfef00e22c6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3260263387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.3260263387
Directory	/workspace/42.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/42.spi_device_stress_all.2146285879
Short name	T772
Test name
Test status
Simulation time	268266791 ps
CPU time	1.08 seconds
Started	May 23 02:48:43 PM PDT 24
Finished	May 23 02:48:47 PM PDT 24
Peak memory	206868 kb
Host	smart-a28ceccc-5d1a-4bac-99ed-c8f375775aec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146285879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre ss_all.2146285879
Directory	/workspace/42.spi_device_stress_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_all.1031602521
Short name	T520
Test name
Test status
Simulation time	9999678666 ps
CPU time	26.3 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:49:10 PM PDT 24
Peak memory	216516 kb
Host	smart-46585b9b-57fd-4be2-afe7-e7ffaeaa2edf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031602521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1031602521
Directory	/workspace/42.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3969807009
Short name	T458
Test name
Test status
Simulation time	1522327320 ps
CPU time	7.67 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:50 PM PDT 24
Peak memory	216072 kb
Host	smart-05d9f562-ff33-497a-a670-53898056d8b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969807009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3969807009
Directory	/workspace/42.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_rw.3487314237
Short name	T802
Test name
Test status
Simulation time	80625835 ps
CPU time	1.06 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:48:42 PM PDT 24
Peak memory	207760 kb
Host	smart-84c3ca21-43d5-4c8d-a63f-ef988d980ffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487314237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3487314237
Directory	/workspace/42.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_sts_read.1323842402
Short name	T381
Test name
Test status
Simulation time	34749792 ps
CPU time	0.86 seconds
Started	May 23 02:48:40 PM PDT 24
Finished	May 23 02:48:43 PM PDT 24
Peak memory	205652 kb
Host	smart-a0f9980b-85c7-4e3d-ba40-5717b3800b51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323842402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1323842402
Directory	/workspace/42.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/42.spi_device_upload.294482012
Short name	T693
Test name
Test status
Simulation time	9226003529 ps
CPU time	9.61 seconds
Started	May 23 02:48:39 PM PDT 24
Finished	May 23 02:48:50 PM PDT 24
Peak memory	234320 kb
Host	smart-6c5c92bf-7e95-4891-9488-3c971e3eb3fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294482012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.294482012
Directory	/workspace/42.spi_device_upload/latest

Test location	/workspace/coverage/default/43.spi_device_alert_test.3654076720
Short name	T299
Test name
Test status
Simulation time	62024175 ps
CPU time	0.72 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:07 PM PDT 24
Peak memory	205260 kb
Host	smart-2f438640-f597-4e08-a9e1-f1da22c17254
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654076720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test. 3654076720
Directory	/workspace/43.spi_device_alert_test/latest

Test location	/workspace/coverage/default/43.spi_device_cfg_cmd.1909668251
Short name	T87
Test name
Test status
Simulation time	935555969 ps
CPU time	3.57 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:09 PM PDT 24
Peak memory	218552 kb
Host	smart-85b47a4a-8ae0-4fed-8b7e-8a0d1832b426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909668251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1909668251
Directory	/workspace/43.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/43.spi_device_csb_read.4039881642
Short name	T806
Test name
Test status
Simulation time	13288569 ps
CPU time	0.79 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:45 PM PDT 24
Peak memory	206828 kb
Host	smart-95e022cc-48d1-4bd8-84a0-31b67ff24356
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039881642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4039881642
Directory	/workspace/43.spi_device_csb_read/latest

Test location	/workspace/coverage/default/43.spi_device_flash_all.480937658
Short name	T521
Test name
Test status
Simulation time	131913970095 ps
CPU time	165.98 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:51:50 PM PDT 24
Peak memory	254964 kb
Host	smart-80e4864d-a46d-43c7-b3d6-01a17e18d972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480937658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.480937658
Directory	/workspace/43.spi_device_flash_all/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm.3227472793
Short name	T639
Test name
Test status
Simulation time	9929843072 ps
CPU time	52.68 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:49:49 PM PDT 24
Peak memory	217648 kb
Host	smart-7a38c2e0-cfda-4b1f-8f08-43dbd3a8d2ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227472793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3227472793
Directory	/workspace/43.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1649378816
Short name	T179
Test name
Test status
Simulation time	304093156187 ps
CPU time	481.72 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:57:07 PM PDT 24
Peak memory	249960 kb
Host	smart-e31ed139-eeaa-416b-8b83-edf96a5e9fef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649378816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl e.1649378816
Directory	/workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/43.spi_device_flash_mode.4139152979
Short name	T468
Test name
Test status
Simulation time	513552917 ps
CPU time	10.04 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:12 PM PDT 24
Peak memory	248084 kb
Host	smart-70e81d6b-d6d6-412d-b3df-3803c2c5ccad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139152979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4139152979
Directory	/workspace/43.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/43.spi_device_intercept.2494233887
Short name	T706
Test name
Test status
Simulation time	511936061 ps
CPU time	2.44 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:05 PM PDT 24
Peak memory	218332 kb
Host	smart-a987c4e3-b0f4-4041-b105-c628378331d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494233887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2494233887
Directory	/workspace/43.spi_device_intercept/latest

Test location	/workspace/coverage/default/43.spi_device_mailbox.435405358
Short name	T525
Test name
Test status
Simulation time	2299847050 ps
CPU time	25.65 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:49:23 PM PDT 24
Peak memory	240204 kb
Host	smart-add0ed41-73b8-4fdb-8f02-5b93c3392eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435405358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.435405358
Directory	/workspace/43.spi_device_mailbox/latest

Test location	/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3854026234
Short name	T268
Test name
Test status
Simulation time	11626176648 ps
CPU time	17.29 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:23 PM PDT 24
Peak memory	218900 kb
Host	smart-e947a618-e4d8-4060-97ac-403673c8af82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854026234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa p.3854026234
Directory	/workspace/43.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/43.spi_device_pass_cmd_filtering.2578420494
Short name	T419
Test name
Test status
Simulation time	700805251 ps
CPU time	2.79 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:09 PM PDT 24
Peak memory	218396 kb
Host	smart-3580fb07-5a53-4bf0-96dd-533869bbf2e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578420494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2578420494
Directory	/workspace/43.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/43.spi_device_read_buffer_direct.2664655023
Short name	T142
Test name
Test status
Simulation time	232392177 ps
CPU time	3.85 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:08 PM PDT 24
Peak memory	219080 kb
Host	smart-60de0eb9-cbbb-4c5c-9f5e-4ff0246447ad
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2664655023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir ect.2664655023
Directory	/workspace/43.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/43.spi_device_stress_all.340138322
Short name	T183
Test name
Test status
Simulation time	154500868580 ps
CPU time	433.85 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:56:10 PM PDT 24
Peak memory	269096 kb
Host	smart-d7c7223c-1cb4-4764-ad50-81330c753528
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340138322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres s_all.340138322
Directory	/workspace/43.spi_device_stress_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_all.2360661740
Short name	T718
Test name
Test status
Simulation time	2608682057 ps
CPU time	13.23 seconds
Started	May 23 02:48:42 PM PDT 24
Finished	May 23 02:48:58 PM PDT 24
Peak memory	216224 kb
Host	smart-ef16ca6d-d014-41ed-a518-5cd438232096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360661740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2360661740
Directory	/workspace/43.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2522953072
Short name	T308
Test name
Test status
Simulation time	153767817 ps
CPU time	1.84 seconds
Started	May 23 02:48:41 PM PDT 24
Finished	May 23 02:48:45 PM PDT 24
Peak memory	207728 kb
Host	smart-2d2fc233-e3a3-4510-ad06-54e40de676e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522953072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2522953072
Directory	/workspace/43.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_rw.183775291
Short name	T358
Test name
Test status
Simulation time	37402861 ps
CPU time	1.3 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:48:57 PM PDT 24
Peak memory	207964 kb
Host	smart-668358b7-d198-4974-9fae-449edba8a80f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183775291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.183775291
Directory	/workspace/43.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_sts_read.3978965520
Short name	T678
Test name
Test status
Simulation time	91812267 ps
CPU time	0.81 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:06 PM PDT 24
Peak memory	205736 kb
Host	smart-1d4a9c10-0167-4fbe-838d-fed7ca7f0d35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978965520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3978965520
Directory	/workspace/43.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/43.spi_device_upload.933790141
Short name	T930
Test name
Test status
Simulation time	528121653 ps
CPU time	4.07 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:11 PM PDT 24
Peak memory	236088 kb
Host	smart-f8e73f95-2cbf-4f35-a0d6-1c9aae22b102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933790141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.933790141
Directory	/workspace/43.spi_device_upload/latest

Test location	/workspace/coverage/default/44.spi_device_alert_test.1954670360
Short name	T902
Test name
Test status
Simulation time	13391249 ps
CPU time	0.73 seconds
Started	May 23 02:48:55 PM PDT 24
Finished	May 23 02:48:58 PM PDT 24
Peak memory	204732 kb
Host	smart-89e71751-0b2c-4589-a3a2-27b5fa43dc16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954670360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 1954670360
Directory	/workspace/44.spi_device_alert_test/latest

Test location	/workspace/coverage/default/44.spi_device_cfg_cmd.2034933022
Short name	T856
Test name
Test status
Simulation time	607134227 ps
CPU time	6.56 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:11 PM PDT 24
Peak memory	234152 kb
Host	smart-ba4154d9-10b8-4a8f-a55b-5cf9c9fbf3dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034933022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2034933022
Directory	/workspace/44.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/44.spi_device_csb_read.884159923
Short name	T446
Test name
Test status
Simulation time	23742255 ps
CPU time	0.75 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:49:01 PM PDT 24
Peak memory	205800 kb
Host	smart-f8412eca-e2e6-4b31-91d5-84de6c956b0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884159923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.884159923
Directory	/workspace/44.spi_device_csb_read/latest

Test location	/workspace/coverage/default/44.spi_device_flash_all.2439194817
Short name	T592
Test name
Test status
Simulation time	31352962016 ps
CPU time	231.43 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:52:51 PM PDT 24
Peak memory	250372 kb
Host	smart-7cad2572-e0dd-44d2-ab32-1b3be02de62e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439194817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2439194817
Directory	/workspace/44.spi_device_flash_all/latest

Test location	/workspace/coverage/default/44.spi_device_flash_and_tpm.321676820
Short name	T411
Test name
Test status
Simulation time	1490099427 ps
CPU time	20.48 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:26 PM PDT 24
Peak memory	224432 kb
Host	smart-985fddfc-13e3-44da-92d2-4d41e6f90d3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321676820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.321676820
Directory	/workspace/44.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.671196079
Short name	T188
Test name
Test status
Simulation time	20961121876 ps
CPU time	110.2 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:50:56 PM PDT 24
Peak memory	251224 kb
Host	smart-677c51fd-0240-41bc-867e-5ba837505746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671196079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle .671196079
Directory	/workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/44.spi_device_flash_mode.3338862884
Short name	T811
Test name
Test status
Simulation time	499139032 ps
CPU time	12.81 seconds
Started	May 23 02:48:55 PM PDT 24
Finished	May 23 02:49:11 PM PDT 24
Peak memory	248620 kb
Host	smart-54845e34-19a0-40df-86d1-a9701bf73db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338862884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3338862884
Directory	/workspace/44.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/44.spi_device_intercept.1419513244
Short name	T848
Test name
Test status
Simulation time	3375223761 ps
CPU time	12.13 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:14 PM PDT 24
Peak memory	233996 kb
Host	smart-43918fca-7021-49b5-bf2c-72320cc17630
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419513244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1419513244
Directory	/workspace/44.spi_device_intercept/latest

Test location	/workspace/coverage/default/44.spi_device_mailbox.4010934110
Short name	T224
Test name
Test status
Simulation time	7409036801 ps
CPU time	37.66 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:49:37 PM PDT 24
Peak memory	238468 kb
Host	smart-954fb38b-0470-4c36-bf50-b1e2110d3fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010934110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4010934110
Directory	/workspace/44.spi_device_mailbox/latest

Test location	/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3526246060
Short name	T929
Test name
Test status
Simulation time	131638289 ps
CPU time	2.67 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:04 PM PDT 24
Peak memory	216588 kb
Host	smart-5ed0ff3f-e099-4453-a347-4493929e4513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526246060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa p.3526246060
Directory	/workspace/44.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/44.spi_device_pass_cmd_filtering.2451006106
Short name	T190
Test name
Test status
Simulation time	12078234789 ps
CPU time	22.66 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:29 PM PDT 24
Peak memory	229676 kb
Host	smart-00a125c1-fff2-4fc7-a15d-9f0869d74ee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451006106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2451006106
Directory	/workspace/44.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/44.spi_device_read_buffer_direct.1873432650
Short name	T363
Test name
Test status
Simulation time	2031868721 ps
CPU time	9.3 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:15 PM PDT 24
Peak memory	222744 kb
Host	smart-90804b12-b222-488e-b5c5-259aa6fc17fa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1873432650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir ect.1873432650
Directory	/workspace/44.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/44.spi_device_stress_all.330356832
Short name	T278
Test name
Test status
Simulation time	10148344646 ps
CPU time	116.83 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:51:03 PM PDT 24
Peak memory	256920 kb
Host	smart-79c89860-fcfb-4311-8aaf-39e1217ae8da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330356832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres s_all.330356832
Directory	/workspace/44.spi_device_stress_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_all.194315235
Short name	T534
Test name
Test status
Simulation time	27266457419 ps
CPU time	31.97 seconds
Started	May 23 02:48:52 PM PDT 24
Finished	May 23 02:49:26 PM PDT 24
Peak memory	216448 kb
Host	smart-2a241cbd-2289-46b1-bdb6-2c155997b4a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194315235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.194315235
Directory	/workspace/44.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.525959976
Short name	T479
Test name
Test status
Simulation time	336213639 ps
CPU time	2.06 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:48:58 PM PDT 24
Peak memory	207608 kb
Host	smart-0fd4359e-4267-4cfc-b257-1ad315226eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525959976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.525959976
Directory	/workspace/44.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_rw.914853855
Short name	T20
Test name
Test status
Simulation time	921138438 ps
CPU time	9.39 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:11 PM PDT 24
Peak memory	216184 kb
Host	smart-c6abac40-74df-4f95-8092-26c8634411b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914853855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.914853855
Directory	/workspace/44.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_sts_read.4233185358
Short name	T807
Test name
Test status
Simulation time	251280503 ps
CPU time	0.93 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:48:56 PM PDT 24
Peak memory	205744 kb
Host	smart-f58cafb2-0256-4649-bf1e-cf70100414e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233185358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4233185358
Directory	/workspace/44.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/44.spi_device_upload.3534068081
Short name	T864
Test name
Test status
Simulation time	689950005 ps
CPU time	6.93 seconds
Started	May 23 02:49:01 PM PDT 24
Finished	May 23 02:49:13 PM PDT 24
Peak memory	218328 kb
Host	smart-031131ce-b7bb-41cc-961e-6b1b6e399edd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534068081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3534068081
Directory	/workspace/44.spi_device_upload/latest

Test location	/workspace/coverage/default/45.spi_device_alert_test.2141900879
Short name	T910
Test name
Test status
Simulation time	14347316 ps
CPU time	0.74 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:03 PM PDT 24
Peak memory	205300 kb
Host	smart-86412f68-69b1-4efb-ba11-69a61b0f5e23
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141900879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 2141900879
Directory	/workspace/45.spi_device_alert_test/latest

Test location	/workspace/coverage/default/45.spi_device_cfg_cmd.338619278
Short name	T723
Test name
Test status
Simulation time	157869548 ps
CPU time	3.25 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:49:03 PM PDT 24
Peak memory	218432 kb
Host	smart-f551e8fe-4717-49b7-8fe9-d4d82d52d143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338619278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.338619278
Directory	/workspace/45.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/45.spi_device_csb_read.1826125505
Short name	T364
Test name
Test status
Simulation time	47501513 ps
CPU time	0.8 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:49:07 PM PDT 24
Peak memory	206488 kb
Host	smart-3dc26c48-76be-4630-b481-884fed5ecc3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826125505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1826125505
Directory	/workspace/45.spi_device_csb_read/latest

Test location	/workspace/coverage/default/45.spi_device_flash_all.1629988173
Short name	T80
Test name
Test status
Simulation time	80602029546 ps
CPU time	172.23 seconds
Started	May 23 02:49:00 PM PDT 24
Finished	May 23 02:51:58 PM PDT 24
Peak memory	252472 kb
Host	smart-152d1106-accd-44e2-8916-574e2fcd5eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629988173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1629988173
Directory	/workspace/45.spi_device_flash_all/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm.52380309
Short name	T23
Test name
Test status
Simulation time	4379000556 ps
CPU time	68.83 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:50:09 PM PDT 24
Peak memory	249120 kb
Host	smart-58451391-d389-45dd-babc-a03885c17c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52380309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.52380309
Directory	/workspace/45.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3450030185
Short name	T731
Test name
Test status
Simulation time	39994522120 ps
CPU time	378.06 seconds
Started	May 23 02:48:55 PM PDT 24
Finished	May 23 02:55:16 PM PDT 24
Peak memory	263528 kb
Host	smart-285e5e46-fe67-41c8-a638-53bf505c4169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450030185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl e.3450030185
Directory	/workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/45.spi_device_flash_mode.2763768479
Short name	T283
Test name
Test status
Simulation time	6850216277 ps
CPU time	31.07 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:34 PM PDT 24
Peak memory	235772 kb
Host	smart-5c7ac49e-7b29-443a-a739-767d87603377
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763768479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2763768479
Directory	/workspace/45.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/45.spi_device_intercept.4058535431
Short name	T254
Test name
Test status
Simulation time	127307294 ps
CPU time	2.75 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:49:03 PM PDT 24
Peak memory	224396 kb
Host	smart-11cfec0a-40eb-47a5-bfed-fb57ace782a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058535431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4058535431
Directory	/workspace/45.spi_device_intercept/latest

Test location	/workspace/coverage/default/45.spi_device_mailbox.3536402049
Short name	T799
Test name
Test status
Simulation time	9374850369 ps
CPU time	11.62 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:16 PM PDT 24
Peak memory	219696 kb
Host	smart-0018a182-3686-48c1-92b2-f17271b1b0af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536402049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3536402049
Directory	/workspace/45.spi_device_mailbox/latest

Test location	/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.926947275
Short name	T4
Test name
Test status
Simulation time	10918303048 ps
CPU time	28.59 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:33 PM PDT 24
Peak memory	223288 kb
Host	smart-4936eb9d-730d-466e-8179-a0a123206b88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926947275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap .926947275
Directory	/workspace/45.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/45.spi_device_pass_cmd_filtering.2772023746
Short name	T697
Test name
Test status
Simulation time	1584627906 ps
CPU time	4.8 seconds
Started	May 23 02:48:55 PM PDT 24
Finished	May 23 02:49:02 PM PDT 24
Peak memory	233076 kb
Host	smart-46e0c525-bb4e-4edc-939a-c4380b0ba8e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772023746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2772023746
Directory	/workspace/45.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/45.spi_device_read_buffer_direct.3495937001
Short name	T386
Test name
Test status
Simulation time	6763507461 ps
CPU time	10.71 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:12 PM PDT 24
Peak memory	222960 kb
Host	smart-4a9a63ec-4c94-4ef5-802b-e17dcf13086b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3495937001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir ect.3495937001
Directory	/workspace/45.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/45.spi_device_stress_all.1244826722
Short name	T620
Test name
Test status
Simulation time	40997274643 ps
CPU time	372.05 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:55:12 PM PDT 24
Peak memory	265496 kb
Host	smart-a9a5923c-b57f-4006-8afb-164629422d78
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244826722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre ss_all.1244826722
Directory	/workspace/45.spi_device_stress_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_all.2365405450
Short name	T538
Test name
Test status
Simulation time	241559032 ps
CPU time	2.81 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:49:00 PM PDT 24
Peak memory	217644 kb
Host	smart-fb700661-41d3-4014-a5c8-0b47927b9eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365405450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2365405450
Directory	/workspace/45.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2545591410
Short name	T758
Test name
Test status
Simulation time	13732738 ps
CPU time	0.81 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:02 PM PDT 24
Peak memory	205568 kb
Host	smart-8aca6bb8-e610-4c33-b49b-55b404e8b581
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545591410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2545591410
Directory	/workspace/45.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_rw.1033461534
Short name	T360
Test name
Test status
Simulation time	2800229364 ps
CPU time	9.3 seconds
Started	May 23 02:48:57 PM PDT 24
Finished	May 23 02:49:10 PM PDT 24
Peak memory	216212 kb
Host	smart-3bbabbb2-9b91-4103-9fef-9954a56c0521
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033461534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1033461534
Directory	/workspace/45.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_sts_read.4019246230
Short name	T936
Test name
Test status
Simulation time	144770028 ps
CPU time	0.91 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:06 PM PDT 24
Peak memory	206012 kb
Host	smart-47c8ffc5-4641-49e0-9ea7-98643970d99f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019246230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4019246230
Directory	/workspace/45.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/45.spi_device_upload.1704610255
Short name	T953
Test name
Test status
Simulation time	18048455565 ps
CPU time	18.23 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:49:15 PM PDT 24
Peak memory	234660 kb
Host	smart-81e8bc38-b7d5-458a-98e8-07afec26861c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704610255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1704610255
Directory	/workspace/45.spi_device_upload/latest

Test location	/workspace/coverage/default/46.spi_device_alert_test.2554779087
Short name	T805
Test name
Test status
Simulation time	13017651 ps
CPU time	0.73 seconds
Started	May 23 02:49:06 PM PDT 24
Finished	May 23 02:49:11 PM PDT 24
Peak memory	205304 kb
Host	smart-1882fd44-ff2c-4425-8556-464a1f656a23
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554779087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 2554779087
Directory	/workspace/46.spi_device_alert_test/latest

Test location	/workspace/coverage/default/46.spi_device_cfg_cmd.1932147208
Short name	T777
Test name
Test status
Simulation time	441961227 ps
CPU time	3.34 seconds
Started	May 23 02:49:07 PM PDT 24
Finished	May 23 02:49:15 PM PDT 24
Peak memory	218328 kb
Host	smart-2f6eae75-5a7b-4329-b789-92532526cd0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932147208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1932147208
Directory	/workspace/46.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/46.spi_device_csb_read.2839267841
Short name	T818
Test name
Test status
Simulation time	72678360 ps
CPU time	0.77 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:05 PM PDT 24
Peak memory	206776 kb
Host	smart-933ee66e-2332-45e2-a0d8-574304533e80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839267841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2839267841
Directory	/workspace/46.spi_device_csb_read/latest

Test location	/workspace/coverage/default/46.spi_device_flash_all.2011864922
Short name	T515
Test name
Test status
Simulation time	3082069097 ps
CPU time	15.46 seconds
Started	May 23 02:49:12 PM PDT 24
Finished	May 23 02:49:31 PM PDT 24
Peak memory	232676 kb
Host	smart-f5bc74ee-0fce-4914-a970-b0761ba79786
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011864922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2011864922
Directory	/workspace/46.spi_device_flash_all/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm.2879979281
Short name	T852
Test name
Test status
Simulation time	53188758767 ps
CPU time	160.8 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:51:54 PM PDT 24
Peak memory	250800 kb
Host	smart-cb33b03a-077d-496d-b941-c7e2e32cdc7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879979281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2879979281
Directory	/workspace/46.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1250648120
Short name	T567
Test name
Test status
Simulation time	4179645588 ps
CPU time	24.73 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:49:37 PM PDT 24
Peak memory	236692 kb
Host	smart-79f4d4c5-f355-4ffb-b2ce-786d27e6852c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250648120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl e.1250648120
Directory	/workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/46.spi_device_flash_mode.896133295
Short name	T471
Test name
Test status
Simulation time	2141481098 ps
CPU time	7.3 seconds
Started	May 23 02:49:07 PM PDT 24
Finished	May 23 02:49:19 PM PDT 24
Peak memory	232624 kb
Host	smart-331504a3-0644-4f28-a684-97663f810939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896133295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.896133295
Directory	/workspace/46.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/46.spi_device_intercept.4052646110
Short name	T231
Test name
Test status
Simulation time	618992842 ps
CPU time	8.5 seconds
Started	May 23 02:49:09 PM PDT 24
Finished	May 23 02:49:22 PM PDT 24
Peak memory	218480 kb
Host	smart-e0a38c2b-ba87-4638-9c6c-5604fa9b9964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052646110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4052646110
Directory	/workspace/46.spi_device_intercept/latest

Test location	/workspace/coverage/default/46.spi_device_mailbox.4194109568
Short name	T466
Test name
Test status
Simulation time	11244487129 ps
CPU time	21.41 seconds
Started	May 23 02:49:07 PM PDT 24
Finished	May 23 02:49:33 PM PDT 24
Peak memory	234596 kb
Host	smart-6d419128-a7d2-44f1-9c36-4c52e7d66415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194109568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4194109568
Directory	/workspace/46.spi_device_mailbox/latest

Test location	/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3538232756
Short name	T594
Test name
Test status
Simulation time	75682186 ps
CPU time	2.58 seconds
Started	May 23 02:49:13 PM PDT 24
Finished	May 23 02:49:18 PM PDT 24
Peak memory	218748 kb
Host	smart-cfc701ff-4ae6-48bb-9c3f-387a331f9ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538232756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa p.3538232756
Directory	/workspace/46.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/46.spi_device_pass_cmd_filtering.4037167339
Short name	T339
Test name
Test status
Simulation time	637509940 ps
CPU time	2.26 seconds
Started	May 23 02:48:56 PM PDT 24
Finished	May 23 02:49:02 PM PDT 24
Peak memory	216012 kb
Host	smart-94ca63f8-fb78-4c9e-9c6a-1f149abce526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037167339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4037167339
Directory	/workspace/46.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/46.spi_device_read_buffer_direct.2270390502
Short name	T540
Test name
Test status
Simulation time	802037841 ps
CPU time	6.2 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:49:18 PM PDT 24
Peak memory	218788 kb
Host	smart-4e455002-c474-41f2-950f-9b53d64a73e5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2270390502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir ect.2270390502
Directory	/workspace/46.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/46.spi_device_stress_all.1898180363
Short name	T825
Test name
Test status
Simulation time	5094331902 ps
CPU time	24.74 seconds
Started	May 23 02:49:09 PM PDT 24
Finished	May 23 02:49:38 PM PDT 24
Peak memory	236388 kb
Host	smart-7edeaeac-67b0-49f4-bb7c-0aac90e65a75
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898180363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre ss_all.1898180363
Directory	/workspace/46.spi_device_stress_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_all.3586797537
Short name	T740
Test name
Test status
Simulation time	4610108093 ps
CPU time	36.36 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:40 PM PDT 24
Peak memory	216324 kb
Host	smart-abdb288f-8254-4373-a183-271562825c94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586797537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3586797537
Directory	/workspace/46.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2896515745
Short name	T507
Test name
Test status
Simulation time	12901252354 ps
CPU time	19.55 seconds
Started	May 23 02:48:54 PM PDT 24
Finished	May 23 02:49:16 PM PDT 24
Peak memory	216188 kb
Host	smart-b72828e1-9047-4d00-a1bd-0e24252b9ad3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896515745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2896515745
Directory	/workspace/46.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_rw.4080754163
Short name	T876
Test name
Test status
Simulation time	128674231 ps
CPU time	3.09 seconds
Started	May 23 02:48:58 PM PDT 24
Finished	May 23 02:49:07 PM PDT 24
Peak memory	216192 kb
Host	smart-9ad7e450-49de-438e-a762-a03fdd0099d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080754163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4080754163
Directory	/workspace/46.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_sts_read.863884398
Short name	T389
Test name
Test status
Simulation time	42682517 ps
CPU time	0.82 seconds
Started	May 23 02:48:59 PM PDT 24
Finished	May 23 02:49:05 PM PDT 24
Peak memory	205700 kb
Host	smart-5f50e8fe-5676-4714-bde0-d684dd24cec8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863884398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.863884398
Directory	/workspace/46.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/46.spi_device_upload.2285819962
Short name	T738
Test name
Test status
Simulation time	6672124102 ps
CPU time	26.92 seconds
Started	May 23 02:49:09 PM PDT 24
Finished	May 23 02:49:40 PM PDT 24
Peak memory	237756 kb
Host	smart-030df390-e54b-4657-8c2d-77fab07d8348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285819962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2285819962
Directory	/workspace/46.spi_device_upload/latest

Test location	/workspace/coverage/default/47.spi_device_alert_test.1482078454
Short name	T424
Test name
Test status
Simulation time	36344018 ps
CPU time	0.74 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:41 PM PDT 24
Peak memory	205432 kb
Host	smart-a22ca349-5161-4222-af04-9f4a0c8fccfc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482078454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test. 1482078454
Directory	/workspace/47.spi_device_alert_test/latest

Test location	/workspace/coverage/default/47.spi_device_cfg_cmd.2243522054
Short name	T432
Test name
Test status
Simulation time	158137556 ps
CPU time	4.02 seconds
Started	May 23 02:49:21 PM PDT 24
Finished	May 23 02:49:26 PM PDT 24
Peak memory	233704 kb
Host	smart-4d06e248-b1a2-40ea-af67-6a7eb0418122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243522054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2243522054
Directory	/workspace/47.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/47.spi_device_csb_read.2033356113
Short name	T472
Test name
Test status
Simulation time	50297588 ps
CPU time	0.8 seconds
Started	May 23 02:49:09 PM PDT 24
Finished	May 23 02:49:14 PM PDT 24
Peak memory	206796 kb
Host	smart-a4fae712-d586-4e21-bf99-4064cbd0734b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033356113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2033356113
Directory	/workspace/47.spi_device_csb_read/latest

Test location	/workspace/coverage/default/47.spi_device_flash_all.4194636145
Short name	T681
Test name
Test status
Simulation time	25500387 ps
CPU time	0.8 seconds
Started	May 23 02:49:20 PM PDT 24
Finished	May 23 02:49:22 PM PDT 24
Peak memory	215900 kb
Host	smart-ce75fccb-e056-460d-ba05-e67fc12afd4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194636145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4194636145
Directory	/workspace/47.spi_device_flash_all/latest

Test location	/workspace/coverage/default/47.spi_device_flash_and_tpm.3450312082
Short name	T247
Test name
Test status
Simulation time	10338637083 ps
CPU time	156.5 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:52:17 PM PDT 24
Peak memory	251920 kb
Host	smart-ce49a292-4d07-407e-bebe-2edfdb480016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450312082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3450312082
Directory	/workspace/47.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3162727129
Short name	T63
Test name
Test status
Simulation time	10152278877 ps
CPU time	122.4 seconds
Started	May 23 02:49:35 PM PDT 24
Finished	May 23 02:51:38 PM PDT 24
Peak memory	248924 kb
Host	smart-fc5f413b-2e8e-446a-9e74-6195d7a11379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162727129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl e.3162727129
Directory	/workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/47.spi_device_flash_mode.3979546098
Short name	T141
Test name
Test status
Simulation time	1180780714 ps
CPU time	20.89 seconds
Started	May 23 02:49:21 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	237192 kb
Host	smart-b3542b9d-8ab3-4f77-b6d5-5dcb9e06930f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979546098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3979546098
Directory	/workspace/47.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/47.spi_device_intercept.725388125
Short name	T544
Test name
Test status
Simulation time	5709516292 ps
CPU time	19.42 seconds
Started	May 23 02:49:23 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	220036 kb
Host	smart-cf186f51-ebf5-4fd2-9218-dac66fd8b387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725388125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.725388125
Directory	/workspace/47.spi_device_intercept/latest

Test location	/workspace/coverage/default/47.spi_device_mailbox.2125124971
Short name	T202
Test name
Test status
Simulation time	315782445 ps
CPU time	5.33 seconds
Started	May 23 02:49:22 PM PDT 24
Finished	May 23 02:49:29 PM PDT 24
Peak memory	233948 kb
Host	smart-860d19c2-617e-4bbd-9434-5dc579a57e06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125124971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2125124971
Directory	/workspace/47.spi_device_mailbox/latest

Test location	/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3430844344
Short name	T177
Test name
Test status
Simulation time	1982937475 ps
CPU time	9.9 seconds
Started	May 23 02:49:15 PM PDT 24
Finished	May 23 02:49:27 PM PDT 24
Peak memory	237156 kb
Host	smart-eca3361d-3f2b-4a75-9635-984b8b713fa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430844344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa p.3430844344
Directory	/workspace/47.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/47.spi_device_pass_cmd_filtering.2900580862
Short name	T214
Test name
Test status
Simulation time	15522755794 ps
CPU time	12.87 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:49:26 PM PDT 24
Peak memory	218816 kb
Host	smart-538f3ec4-8c22-4673-8a86-a0c96c96962c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900580862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2900580862
Directory	/workspace/47.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/47.spi_device_read_buffer_direct.994671584
Short name	T52
Test name
Test status
Simulation time	379370959 ps
CPU time	4.52 seconds
Started	May 23 02:49:23 PM PDT 24
Finished	May 23 02:49:28 PM PDT 24
Peak memory	219136 kb
Host	smart-ab9adb17-2871-478f-bda3-09d1d717c65b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=994671584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire ct.994671584
Directory	/workspace/47.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/47.spi_device_stress_all.3876069900
Short name	T725
Test name
Test status
Simulation time	9078573531 ps
CPU time	58.75 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:50:37 PM PDT 24
Peak memory	255404 kb
Host	smart-c162658b-1edf-4655-bc3b-1f2db2a8198e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876069900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre ss_all.3876069900
Directory	/workspace/47.spi_device_stress_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_all.2885698215
Short name	T294
Test name
Test status
Simulation time	370711275 ps
CPU time	6.23 seconds
Started	May 23 02:49:09 PM PDT 24
Finished	May 23 02:49:20 PM PDT 24
Peak memory	216252 kb
Host	smart-c742d4e5-a371-4080-b7f3-a0eb24167809
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885698215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2885698215
Directory	/workspace/47.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3580017661
Short name	T390
Test name
Test status
Simulation time	5200762410 ps
CPU time	5.34 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:49:17 PM PDT 24
Peak memory	216240 kb
Host	smart-b0011bb2-c236-46cf-ba9e-4977cc622f36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580017661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3580017661
Directory	/workspace/47.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_rw.1663429422
Short name	T843
Test name
Test status
Simulation time	111319782 ps
CPU time	1.42 seconds
Started	May 23 02:49:12 PM PDT 24
Finished	May 23 02:49:16 PM PDT 24
Peak memory	216256 kb
Host	smart-d7afaa16-06c6-4e32-832c-cc6db774adf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663429422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1663429422
Directory	/workspace/47.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_sts_read.521887027
Short name	T325
Test name
Test status
Simulation time	73511903 ps
CPU time	1 seconds
Started	May 23 02:49:08 PM PDT 24
Finished	May 23 02:49:13 PM PDT 24
Peak memory	206704 kb
Host	smart-ccbcc0a0-91ea-4d3b-9da2-e8f0be577e4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521887027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.521887027
Directory	/workspace/47.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/47.spi_device_upload.1536154098
Short name	T558
Test name
Test status
Simulation time	6459032849 ps
CPU time	7.34 seconds
Started	May 23 02:49:22 PM PDT 24
Finished	May 23 02:49:30 PM PDT 24
Peak memory	218380 kb
Host	smart-cd624633-73e0-403a-9888-f619bff157e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536154098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1536154098
Directory	/workspace/47.spi_device_upload/latest

Test location	/workspace/coverage/default/48.spi_device_alert_test.2875328711
Short name	T808
Test name
Test status
Simulation time	11852119 ps
CPU time	0.72 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:38 PM PDT 24
Peak memory	204692 kb
Host	smart-b040f0be-a22e-4fd9-9a65-9eebe621cad5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875328711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test. 2875328711
Directory	/workspace/48.spi_device_alert_test/latest

Test location	/workspace/coverage/default/48.spi_device_cfg_cmd.1259111895
Short name	T704
Test name
Test status
Simulation time	641546678 ps
CPU time	4.58 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:42 PM PDT 24
Peak memory	218864 kb
Host	smart-1204ac48-399b-449a-af66-d3fa372261bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259111895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1259111895
Directory	/workspace/48.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/48.spi_device_csb_read.1136511880
Short name	T887
Test name
Test status
Simulation time	37936317 ps
CPU time	0.76 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:41 PM PDT 24
Peak memory	206428 kb
Host	smart-e71e2e0c-7fcb-4971-bf8c-f0defe67d089
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136511880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1136511880
Directory	/workspace/48.spi_device_csb_read/latest

Test location	/workspace/coverage/default/48.spi_device_flash_all.3258541458
Short name	T206
Test name
Test status
Simulation time	23331398371 ps
CPU time	184.8 seconds
Started	May 23 02:49:40 PM PDT 24
Finished	May 23 02:52:46 PM PDT 24
Peak memory	253300 kb
Host	smart-c6bab4e6-5fab-43e3-b5fb-b088d2ec1255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258541458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3258541458
Directory	/workspace/48.spi_device_flash_all/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm.1780354542
Short name	T661
Test name
Test status
Simulation time	4857641173 ps
CPU time	38.23 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:50:18 PM PDT 24
Peak memory	240456 kb
Host	smart-42f58909-5da2-4a47-a83e-09cb44c33431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780354542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1780354542
Directory	/workspace/48.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1057817841
Short name	T220
Test name
Test status
Simulation time	2208826043 ps
CPU time	20.76 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:50:00 PM PDT 24
Peak memory	235172 kb
Host	smart-7e83d4e3-3869-45e6-9a32-e98c8bb0e601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057817841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl e.1057817841
Directory	/workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/48.spi_device_flash_mode.2327663643
Short name	T281
Test name
Test status
Simulation time	4507158886 ps
CPU time	48.69 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:50:26 PM PDT 24
Peak memory	240048 kb
Host	smart-3715916e-b3db-4b05-a60d-7031fac8cd8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327663643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2327663643
Directory	/workspace/48.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/48.spi_device_intercept.1129360965
Short name	T444
Test name
Test status
Simulation time	232943691 ps
CPU time	3.27 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:49:41 PM PDT 24
Peak memory	216492 kb
Host	smart-ad737725-fc52-4a94-af4e-93e00e26f27d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129360965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1129360965
Directory	/workspace/48.spi_device_intercept/latest

Test location	/workspace/coverage/default/48.spi_device_mailbox.42010964
Short name	T743
Test name
Test status
Simulation time	1321990895 ps
CPU time	24.07 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:50:03 PM PDT 24
Peak memory	228996 kb
Host	smart-62cb6fde-d668-4999-aea0-731f7e190abf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42010964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.42010964
Directory	/workspace/48.spi_device_mailbox/latest

Test location	/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1778196804
Short name	T877
Test name
Test status
Simulation time	53419798 ps
CPU time	2.11 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:40 PM PDT 24
Peak memory	215948 kb
Host	smart-d3ac0cca-e526-4633-8d95-8e28d2ccd367
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778196804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa p.1778196804
Directory	/workspace/48.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/48.spi_device_pass_cmd_filtering.2481457531
Short name	T186
Test name
Test status
Simulation time	2566498741 ps
CPU time	4.4 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:44 PM PDT 24
Peak memory	217828 kb
Host	smart-2cda68d4-db8d-471d-92a3-6837337a968d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481457531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2481457531
Directory	/workspace/48.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/48.spi_device_read_buffer_direct.1069177954
Short name	T746
Test name
Test status
Simulation time	110063929 ps
CPU time	4.29 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:44 PM PDT 24
Peak memory	222244 kb
Host	smart-ee69f485-62a7-4f64-888f-9b02593602d0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1069177954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir ect.1069177954
Directory	/workspace/48.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/48.spi_device_stress_all.3437146318
Short name	T897
Test name
Test status
Simulation time	41260781 ps
CPU time	0.98 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:39 PM PDT 24
Peak memory	206540 kb
Host	smart-4a975ca2-0bc6-4f18-8e52-ee48b3ffeffa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437146318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre ss_all.3437146318
Directory	/workspace/48.spi_device_stress_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_all.368619231
Short name	T287
Test name
Test status
Simulation time	6582091320 ps
CPU time	12.19 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:49:50 PM PDT 24
Peak memory	216560 kb
Host	smart-599f8915-c0bf-4c1a-99ca-8af4031f3297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368619231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.368619231
Directory	/workspace/48.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.818519697
Short name	T473
Test name
Test status
Simulation time	5278597310 ps
CPU time	5.22 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	216176 kb
Host	smart-c728669d-33b1-4c87-a688-6b64e104581c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818519697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.818519697
Directory	/workspace/48.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_rw.2891575059
Short name	T949
Test name
Test status
Simulation time	84229367 ps
CPU time	1.03 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:49:39 PM PDT 24
Peak memory	207272 kb
Host	smart-32fdd2c0-1263-44cf-989b-e58026a60263
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891575059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2891575059
Directory	/workspace/48.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_sts_read.2267571417
Short name	T531
Test name
Test status
Simulation time	217345695 ps
CPU time	0.84 seconds
Started	May 23 02:49:41 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	205712 kb
Host	smart-15957b3e-3646-4c2d-ada9-ede183938709
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267571417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2267571417
Directory	/workspace/48.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/48.spi_device_upload.3060995635
Short name	T553
Test name
Test status
Simulation time	2134354660 ps
CPU time	10.24 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:49:48 PM PDT 24
Peak memory	226912 kb
Host	smart-19f83c9a-8f68-407c-a188-f965b3429879
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060995635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3060995635
Directory	/workspace/48.spi_device_upload/latest

Test location	/workspace/coverage/default/49.spi_device_alert_test.226886433
Short name	T457
Test name
Test status
Simulation time	12186428 ps
CPU time	0.75 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:41 PM PDT 24
Peak memory	205340 kb
Host	smart-52faf6c7-75fc-48b5-9588-f1126bd064a3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226886433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.226886433
Directory	/workspace/49.spi_device_alert_test/latest

Test location	/workspace/coverage/default/49.spi_device_cfg_cmd.95720126
Short name	T582
Test name
Test status
Simulation time	128209769 ps
CPU time	2.76 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:49:44 PM PDT 24
Peak memory	218520 kb
Host	smart-453970ff-df56-4e13-9b18-cdcbb3a57e55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95720126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.95720126
Directory	/workspace/49.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/49.spi_device_csb_read.274097722
Short name	T454
Test name
Test status
Simulation time	101459058 ps
CPU time	0.76 seconds
Started	May 23 02:49:41 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	205468 kb
Host	smart-16ff851b-c4f8-4b0f-8d02-4e6ecbcd53d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274097722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.274097722
Directory	/workspace/49.spi_device_csb_read/latest

Test location	/workspace/coverage/default/49.spi_device_flash_all.69859693
Short name	T683
Test name
Test status
Simulation time	1253607630 ps
CPU time	8.86 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:49 PM PDT 24
Peak memory	238772 kb
Host	smart-9f62e7a0-d045-440c-9ebe-1a4cba227cc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69859693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.69859693
Directory	/workspace/49.spi_device_flash_all/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm.3969161887
Short name	T56
Test name
Test status
Simulation time	52900272967 ps
CPU time	484.53 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:57:45 PM PDT 24
Peak memory	265060 kb
Host	smart-08bf49e5-9b3c-443f-82ac-412e439f6d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969161887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3969161887
Directory	/workspace/49.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3525824806
Short name	T136
Test name
Test status
Simulation time	2688055332 ps
CPU time	49.25 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:50:28 PM PDT 24
Peak memory	240908 kb
Host	smart-c861d7b4-377e-4a03-97de-b0d8a1ea1c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525824806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl e.3525824806
Directory	/workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/49.spi_device_flash_mode.3308267296
Short name	T889
Test name
Test status
Simulation time	1677683521 ps
CPU time	24.07 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:50:03 PM PDT 24
Peak memory	233900 kb
Host	smart-1497e4a1-f12b-4a69-ba2e-d6fcc4508acf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308267296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3308267296
Directory	/workspace/49.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/49.spi_device_intercept.1126979631
Short name	T730
Test name
Test status
Simulation time	367529285 ps
CPU time	3.9 seconds
Started	May 23 02:49:37 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	218356 kb
Host	smart-1e5a8985-1100-4e40-878c-43129635d11a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126979631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1126979631
Directory	/workspace/49.spi_device_intercept/latest

Test location	/workspace/coverage/default/49.spi_device_mailbox.2436425835
Short name	T728
Test name
Test status
Simulation time	337977755 ps
CPU time	5.99 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:49:45 PM PDT 24
Peak memory	233412 kb
Host	smart-ef603669-9f8a-4bcf-86b3-49e83e073965
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436425835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2436425835
Directory	/workspace/49.spi_device_mailbox/latest

Test location	/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3046009139
Short name	T797
Test name
Test status
Simulation time	9145878777 ps
CPU time	21.45 seconds
Started	May 23 02:49:41 PM PDT 24
Finished	May 23 02:50:04 PM PDT 24
Peak memory	232660 kb
Host	smart-ff36ba37-74d0-4d07-b99b-7eca9b627f84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046009139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa p.3046009139
Directory	/workspace/49.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/49.spi_device_pass_cmd_filtering.751775891
Short name	T665
Test name
Test status
Simulation time	165881998 ps
CPU time	4.24 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:49:45 PM PDT 24
Peak memory	233568 kb
Host	smart-78237d40-073d-4ce8-b393-831b4920a783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751775891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.751775891
Directory	/workspace/49.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/49.spi_device_read_buffer_direct.2378450551
Short name	T392
Test name
Test status
Simulation time	1648913583 ps
CPU time	5.2 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:49:46 PM PDT 24
Peak memory	222968 kb
Host	smart-bb95de79-b0a8-443e-bc9c-086e5b144ba1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2378450551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir ect.2378450551
Directory	/workspace/49.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/49.spi_device_stress_all.2975435799
Short name	T431
Test name
Test status
Simulation time	7847754078 ps
CPU time	109.98 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:51:26 PM PDT 24
Peak memory	249116 kb
Host	smart-7f0d5d53-1779-4dd5-8b6c-d006f6e83fae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975435799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre ss_all.2975435799
Directory	/workspace/49.spi_device_stress_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_all.2352714603
Short name	T625
Test name
Test status
Simulation time	16093855209 ps
CPU time	19.99 seconds
Started	May 23 02:49:38 PM PDT 24
Finished	May 23 02:50:00 PM PDT 24
Peak memory	216236 kb
Host	smart-6f8d36ab-d0df-4f3f-92ea-cb9361be1b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352714603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2352714603
Directory	/workspace/49.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1220065266
Short name	T319
Test name
Test status
Simulation time	39400013917 ps
CPU time	17.2 seconds
Started	May 23 02:49:35 PM PDT 24
Finished	May 23 02:49:53 PM PDT 24
Peak memory	216168 kb
Host	smart-d6b1c0fe-df35-43a5-8ac1-21c7f4f0dedb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220065266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1220065266
Directory	/workspace/49.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_rw.4084309258
Short name	T894
Test name
Test status
Simulation time	393313834 ps
CPU time	2.51 seconds
Started	May 23 02:49:39 PM PDT 24
Finished	May 23 02:49:43 PM PDT 24
Peak memory	216208 kb
Host	smart-58e7c94b-f1e2-4230-9029-e93f16e944a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084309258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4084309258
Directory	/workspace/49.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_sts_read.2978515969
Short name	T421
Test name
Test status
Simulation time	33637672 ps
CPU time	0.75 seconds
Started	May 23 02:49:42 PM PDT 24
Finished	May 23 02:49:44 PM PDT 24
Peak memory	205712 kb
Host	smart-e41f7965-0c5b-46cd-95dc-c31014e6d43d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978515969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2978515969
Directory	/workspace/49.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/49.spi_device_upload.3808417111
Short name	T336
Test name
Test status
Simulation time	11014686761 ps
CPU time	14.95 seconds
Started	May 23 02:49:36 PM PDT 24
Finished	May 23 02:49:52 PM PDT 24
Peak memory	239192 kb
Host	smart-69d6f688-ff56-49f2-b162-f85263e010ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808417111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3808417111
Directory	/workspace/49.spi_device_upload/latest

Test location	/workspace/coverage/default/5.spi_device_alert_test.2274768520
Short name	T621
Test name
Test status
Simulation time	42136184 ps
CPU time	0.72 seconds
Started	May 23 02:41:54 PM PDT 24
Finished	May 23 02:41:56 PM PDT 24
Peak memory	205344 kb
Host	smart-77af8c15-4f28-4629-9cc4-2bf2685affe7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274768520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2 274768520
Directory	/workspace/5.spi_device_alert_test/latest

Test location	/workspace/coverage/default/5.spi_device_cfg_cmd.2889681703
Short name	T708
Test name
Test status
Simulation time	71291152 ps
CPU time	2.04 seconds
Started	May 23 02:41:34 PM PDT 24
Finished	May 23 02:41:37 PM PDT 24
Peak memory	216056 kb
Host	smart-57d6d54c-4969-4e75-b672-2ff1fa7c8744
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889681703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2889681703
Directory	/workspace/5.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/5.spi_device_csb_read.508898354
Short name	T455
Test name
Test status
Simulation time	142526106 ps
CPU time	0.8 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:36 PM PDT 24
Peak memory	206504 kb
Host	smart-21871f8a-39bd-4cfc-828b-e62dff3c0203
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508898354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.508898354
Directory	/workspace/5.spi_device_csb_read/latest

Test location	/workspace/coverage/default/5.spi_device_flash_all.3166245194
Short name	T834
Test name
Test status
Simulation time	32146327584 ps
CPU time	75.45 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:42:51 PM PDT 24
Peak memory	249004 kb
Host	smart-14a54088-b43e-4e60-ae4d-6c960383f3d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166245194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3166245194
Directory	/workspace/5.spi_device_flash_all/latest

Test location	/workspace/coverage/default/5.spi_device_flash_and_tpm.377926689
Short name	T249
Test name
Test status
Simulation time	9875381252 ps
CPU time	49.66 seconds
Started	May 23 02:41:50 PM PDT 24
Finished	May 23 02:42:40 PM PDT 24
Peak memory	254020 kb
Host	smart-ac3b208c-e894-4df2-b129-ecc71b2061fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377926689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.377926689
Directory	/workspace/5.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/5.spi_device_flash_mode.3884170508
Short name	T64
Test name
Test status
Simulation time	3666118168 ps
CPU time	15.55 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:52 PM PDT 24
Peak memory	250132 kb
Host	smart-8567ab74-2f9e-45b9-a6f5-0c11fda982c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884170508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3884170508
Directory	/workspace/5.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/5.spi_device_intercept.210257775
Short name	T185
Test name
Test status
Simulation time	587164814 ps
CPU time	4.44 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:41 PM PDT 24
Peak memory	233772 kb
Host	smart-cd4bbfd3-6a81-45e9-b5de-955626fdd64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210257775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.210257775
Directory	/workspace/5.spi_device_intercept/latest

Test location	/workspace/coverage/default/5.spi_device_mailbox.3559218833
Short name	T657
Test name
Test status
Simulation time	4502512503 ps
CPU time	53.42 seconds
Started	May 23 02:41:36 PM PDT 24
Finished	May 23 02:42:30 PM PDT 24
Peak memory	238164 kb
Host	smart-6391a3f3-01b9-45a5-b4f3-3aac9e0ed0c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559218833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3559218833
Directory	/workspace/5.spi_device_mailbox/latest

Test location	/workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1151439722
Short name	T603
Test name
Test status
Simulation time	264678615 ps
CPU time	2 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:38 PM PDT 24
Peak memory	216000 kb
Host	smart-8c4d477b-c96f-4cb7-be0e-475f4ee3f52a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151439722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap .1151439722
Directory	/workspace/5.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/5.spi_device_pass_cmd_filtering.1937165888
Short name	T795
Test name
Test status
Simulation time	13574285223 ps
CPU time	16.09 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:52 PM PDT 24
Peak memory	237896 kb
Host	smart-24e541f9-8601-4a6a-b29a-7f3a5bede03d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937165888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1937165888
Directory	/workspace/5.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/5.spi_device_read_buffer_direct.3457984409
Short name	T369
Test name
Test status
Simulation time	243400531 ps
CPU time	4.66 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:41 PM PDT 24
Peak memory	218756 kb
Host	smart-18832ffa-c97b-44cc-a8f3-90a33ae9007e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3457984409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire ct.3457984409
Directory	/workspace/5.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_all.852922192
Short name	T707
Test name
Test status
Simulation time	1365528582 ps
CPU time	6.02 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:41 PM PDT 24
Peak memory	216532 kb
Host	smart-3f0a5bcc-5018-48d2-8556-fede94cd1758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852922192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.852922192
Directory	/workspace/5.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.595574762
Short name	T648
Test name
Test status
Simulation time	12393333 ps
CPU time	0.72 seconds
Started	May 23 02:41:36 PM PDT 24
Finished	May 23 02:41:37 PM PDT 24
Peak memory	205552 kb
Host	smart-f66c709c-b72f-4e82-9b49-0e1a4c45771e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595574762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.595574762
Directory	/workspace/5.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_rw.883122494
Short name	T560
Test name
Test status
Simulation time	103179626 ps
CPU time	1.75 seconds
Started	May 23 02:41:35 PM PDT 24
Finished	May 23 02:41:37 PM PDT 24
Peak memory	216176 kb
Host	smart-84bdbc5a-7af8-45d7-8438-b69cca0afef0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883122494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.883122494
Directory	/workspace/5.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_sts_read.931040931
Short name	T532
Test name
Test status
Simulation time	39228346 ps
CPU time	0.71 seconds
Started	May 23 02:41:36 PM PDT 24
Finished	May 23 02:41:37 PM PDT 24
Peak memory	205552 kb
Host	smart-0ce8fb83-72d6-449c-93de-dc2da034ed8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931040931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.931040931
Directory	/workspace/5.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/5.spi_device_upload.627266658
Short name	T526
Test name
Test status
Simulation time	973689532 ps
CPU time	2.09 seconds
Started	May 23 02:41:36 PM PDT 24
Finished	May 23 02:41:39 PM PDT 24
Peak memory	207756 kb
Host	smart-cbd548b0-f5c4-47ef-a8a1-6bbd8132377c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627266658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.627266658
Directory	/workspace/5.spi_device_upload/latest

Test location	/workspace/coverage/default/6.spi_device_alert_test.608541808
Short name	T341
Test name
Test status
Simulation time	19369211 ps
CPU time	0.75 seconds
Started	May 23 02:42:04 PM PDT 24
Finished	May 23 02:42:05 PM PDT 24
Peak memory	205316 kb
Host	smart-80a31231-64bd-4083-b079-b57c5810b27e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608541808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.608541808
Directory	/workspace/6.spi_device_alert_test/latest

Test location	/workspace/coverage/default/6.spi_device_cfg_cmd.2962039980
Short name	T494
Test name
Test status
Simulation time	268854160 ps
CPU time	2.32 seconds
Started	May 23 02:41:56 PM PDT 24
Finished	May 23 02:41:59 PM PDT 24
Peak memory	218564 kb
Host	smart-dd132cc2-6939-4cb2-b643-a0cbdb18c049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962039980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2962039980
Directory	/workspace/6.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/6.spi_device_csb_read.458894946
Short name	T485
Test name
Test status
Simulation time	72730147 ps
CPU time	0.83 seconds
Started	May 23 02:41:54 PM PDT 24
Finished	May 23 02:41:56 PM PDT 24
Peak memory	206488 kb
Host	smart-40895834-fd39-4d15-85a1-c5ca1c923266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458894946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.458894946
Directory	/workspace/6.spi_device_csb_read/latest

Test location	/workspace/coverage/default/6.spi_device_flash_all.3778401477
Short name	T226
Test name
Test status
Simulation time	21035742797 ps
CPU time	79.58 seconds
Started	May 23 02:41:52 PM PDT 24
Finished	May 23 02:43:12 PM PDT 24
Peak memory	240808 kb
Host	smart-7b7c27fb-77e5-479c-9566-e9811677ae9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778401477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3778401477
Directory	/workspace/6.spi_device_flash_all/latest

Test location	/workspace/coverage/default/6.spi_device_flash_and_tpm.2162180987
Short name	T717
Test name
Test status
Simulation time	9205726448 ps
CPU time	81.58 seconds
Started	May 23 02:41:57 PM PDT 24
Finished	May 23 02:43:20 PM PDT 24
Peak memory	236632 kb
Host	smart-c20e55d7-d431-4630-a799-da0670380e35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162180987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2162180987
Directory	/workspace/6.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3867046408
Short name	T847
Test name
Test status
Simulation time	20462079350 ps
CPU time	131.17 seconds
Started	May 23 02:41:55 PM PDT 24
Finished	May 23 02:44:07 PM PDT 24
Peak memory	257852 kb
Host	smart-94be91bf-67bc-43f6-a620-aa89841bb01f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867046408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle .3867046408
Directory	/workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/6.spi_device_flash_mode.2284483839
Short name	T376
Test name
Test status
Simulation time	659345902 ps
CPU time	9.03 seconds
Started	May 23 02:41:55 PM PDT 24
Finished	May 23 02:42:04 PM PDT 24
Peak memory	232596 kb
Host	smart-7cc71240-e77e-4128-8305-459bed140ced
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284483839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2284483839
Directory	/workspace/6.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/6.spi_device_intercept.397014227
Short name	T530
Test name
Test status
Simulation time	1078650049 ps
CPU time	5.8 seconds
Started	May 23 02:41:51 PM PDT 24
Finished	May 23 02:41:57 PM PDT 24
Peak memory	232604 kb
Host	smart-0a4b55a0-f6b6-43e2-9282-8051360d88f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397014227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.397014227
Directory	/workspace/6.spi_device_intercept/latest

Test location	/workspace/coverage/default/6.spi_device_mailbox.2704504489
Short name	T459
Test name
Test status
Simulation time	39284122805 ps
CPU time	66.34 seconds
Started	May 23 02:41:51 PM PDT 24
Finished	May 23 02:42:58 PM PDT 24
Peak memory	234512 kb
Host	smart-dfd97416-74a9-478a-af1e-3a8c21d43569
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704504489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2704504489
Directory	/workspace/6.spi_device_mailbox/latest

Test location	/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2713170201
Short name	T48
Test name
Test status
Simulation time	39238805 ps
CPU time	2.8 seconds
Started	May 23 02:41:52 PM PDT 24
Finished	May 23 02:41:56 PM PDT 24
Peak memory	233640 kb
Host	smart-6d293ac3-8a66-49b8-a91e-2868e408ec37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713170201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .2713170201
Directory	/workspace/6.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_pass_cmd_filtering.2789301679
Short name	T940
Test name
Test status
Simulation time	108831031 ps
CPU time	2.21 seconds
Started	May 23 02:41:50 PM PDT 24
Finished	May 23 02:41:53 PM PDT 24
Peak memory	216020 kb
Host	smart-10058b15-1384-4a51-af1d-31fb1cf5e0d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789301679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2789301679
Directory	/workspace/6.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/6.spi_device_read_buffer_direct.151305426
Short name	T810
Test name
Test status
Simulation time	1413920532 ps
CPU time	13.91 seconds
Started	May 23 02:41:55 PM PDT 24
Finished	May 23 02:42:10 PM PDT 24
Peak memory	222728 kb
Host	smart-ac57e0fc-7603-46a9-befa-c88576538df5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=151305426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc t.151305426
Directory	/workspace/6.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/6.spi_device_stress_all.3474671837
Short name	T157
Test name
Test status
Simulation time	48085140 ps
CPU time	1.05 seconds
Started	May 23 02:42:03 PM PDT 24
Finished	May 23 02:42:04 PM PDT 24
Peak memory	206992 kb
Host	smart-cba2ec54-297a-45de-b767-2e153ff1e4fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474671837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres s_all.3474671837
Directory	/workspace/6.spi_device_stress_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_all.397380920
Short name	T931
Test name
Test status
Simulation time	25223297735 ps
CPU time	51.29 seconds
Started	May 23 02:41:50 PM PDT 24
Finished	May 23 02:42:42 PM PDT 24
Peak memory	216248 kb
Host	smart-41a77f35-f837-4f7c-b575-b1aa41e92733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397380920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.397380920
Directory	/workspace/6.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3607334675
Short name	T88
Test name
Test status
Simulation time	7052687271 ps
CPU time	21.91 seconds
Started	May 23 02:41:50 PM PDT 24
Finished	May 23 02:42:13 PM PDT 24
Peak memory	216160 kb
Host	smart-cbf37852-22c8-4b71-836d-01bd3668413d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607334675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3607334675
Directory	/workspace/6.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_rw.471457371
Short name	T317
Test name
Test status
Simulation time	89822419 ps
CPU time	1.05 seconds
Started	May 23 02:41:52 PM PDT 24
Finished	May 23 02:41:53 PM PDT 24
Peak memory	206836 kb
Host	smart-3a8fdf17-2998-4510-b120-cd3570954f2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471457371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.471457371
Directory	/workspace/6.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_sts_read.695489864
Short name	T315
Test name
Test status
Simulation time	45911209 ps
CPU time	0.69 seconds
Started	May 23 02:41:55 PM PDT 24
Finished	May 23 02:41:56 PM PDT 24
Peak memory	205528 kb
Host	smart-938711dd-adb3-424c-affc-d74752a805da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695489864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.695489864
Directory	/workspace/6.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/6.spi_device_upload.519821371
Short name	T223
Test name
Test status
Simulation time	585737837 ps
CPU time	7.09 seconds
Started	May 23 02:41:55 PM PDT 24
Finished	May 23 02:42:02 PM PDT 24
Peak memory	227092 kb
Host	smart-00841967-20bb-4a28-a47a-42cdb9c3b86e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519821371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.519821371
Directory	/workspace/6.spi_device_upload/latest

Test location	/workspace/coverage/default/7.spi_device_alert_test.1800105323
Short name	T775
Test name
Test status
Simulation time	33305091 ps
CPU time	0.74 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:42:22 PM PDT 24
Peak memory	205304 kb
Host	smart-1682ed26-d466-4d36-bb14-d9e783389bb7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800105323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1 800105323
Directory	/workspace/7.spi_device_alert_test/latest

Test location	/workspace/coverage/default/7.spi_device_cfg_cmd.2147230359
Short name	T873
Test name
Test status
Simulation time	189604262 ps
CPU time	4.93 seconds
Started	May 23 02:42:04 PM PDT 24
Finished	May 23 02:42:09 PM PDT 24
Peak memory	218760 kb
Host	smart-ce4b42a8-dc28-4146-bc22-da240fb8a4c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147230359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2147230359
Directory	/workspace/7.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/7.spi_device_csb_read.2997400208
Short name	T803
Test name
Test status
Simulation time	52187197 ps
CPU time	0.79 seconds
Started	May 23 02:42:02 PM PDT 24
Finished	May 23 02:42:03 PM PDT 24
Peak memory	206280 kb
Host	smart-71b4bc35-f8ab-4c04-8f20-bbfc5971b111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997400208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2997400208
Directory	/workspace/7.spi_device_csb_read/latest

Test location	/workspace/coverage/default/7.spi_device_flash_all.530044352
Short name	T102
Test name
Test status
Simulation time	12432949541 ps
CPU time	112.95 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:44:14 PM PDT 24
Peak memory	253748 kb
Host	smart-f49b2ab1-d02a-49e1-af42-be9bac4879fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530044352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.530044352
Directory	/workspace/7.spi_device_flash_all/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm.3003505866
Short name	T258
Test name
Test status
Simulation time	335897503207 ps
CPU time	168.86 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:45:10 PM PDT 24
Peak memory	238864 kb
Host	smart-40751a6b-cb23-424d-9428-e9f495fb23db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003505866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3003505866
Directory	/workspace/7.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/7.spi_device_flash_mode.1017690858
Short name	T314
Test name
Test status
Simulation time	5623866793 ps
CPU time	14.29 seconds
Started	May 23 02:42:04 PM PDT 24
Finished	May 23 02:42:19 PM PDT 24
Peak memory	238912 kb
Host	smart-9a388ea3-7845-4bd0-b355-b829426b98a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017690858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1017690858
Directory	/workspace/7.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/7.spi_device_intercept.2846773160
Short name	T331
Test name
Test status
Simulation time	470176080 ps
CPU time	5.17 seconds
Started	May 23 02:42:03 PM PDT 24
Finished	May 23 02:42:09 PM PDT 24
Peak memory	218660 kb
Host	smart-b6a79535-bb76-4659-b0ad-62d25614e277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846773160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2846773160
Directory	/workspace/7.spi_device_intercept/latest

Test location	/workspace/coverage/default/7.spi_device_mailbox.2721725556
Short name	T99
Test name
Test status
Simulation time	399847494 ps
CPU time	8.79 seconds
Started	May 23 02:42:02 PM PDT 24
Finished	May 23 02:42:11 PM PDT 24
Peak memory	228516 kb
Host	smart-edd57905-9dad-4db6-a68c-2215a49a025c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721725556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2721725556
Directory	/workspace/7.spi_device_mailbox/latest

Test location	/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3098125229
Short name	T796
Test name
Test status
Simulation time	2437576347 ps
CPU time	10.18 seconds
Started	May 23 02:42:01 PM PDT 24
Finished	May 23 02:42:12 PM PDT 24
Peak memory	237564 kb
Host	smart-5d95574b-b752-4e25-a8a9-21a75d790f12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098125229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap .3098125229
Directory	/workspace/7.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/7.spi_device_pass_cmd_filtering.1212010951
Short name	T869
Test name
Test status
Simulation time	1289235967 ps
CPU time	7.22 seconds
Started	May 23 02:42:02 PM PDT 24
Finished	May 23 02:42:10 PM PDT 24
Peak memory	236272 kb
Host	smart-e0157ad8-9c63-4a36-a049-0bf269b03428
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212010951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1212010951
Directory	/workspace/7.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/7.spi_device_read_buffer_direct.86386812
Short name	T769
Test name
Test status
Simulation time	9634985776 ps
CPU time	7.81 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:27 PM PDT 24
Peak memory	222364 kb
Host	smart-8ae7b0f3-a187-413a-a706-1eafff7acc1c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=86386812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct .86386812
Directory	/workspace/7.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/7.spi_device_stress_all.2407009273
Short name	T69
Test name
Test status
Simulation time	43593721 ps
CPU time	0.98 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:21 PM PDT 24
Peak memory	205684 kb
Host	smart-2b8cd03e-8104-40e7-93bf-08365c12e7a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407009273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres s_all.2407009273
Directory	/workspace/7.spi_device_stress_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_all.2735158990
Short name	T394
Test name
Test status
Simulation time	2009969382 ps
CPU time	16.61 seconds
Started	May 23 02:42:03 PM PDT 24
Finished	May 23 02:42:20 PM PDT 24
Peak memory	216092 kb
Host	smart-f4641c8b-3d05-423e-a849-12c204ba1c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735158990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2735158990
Directory	/workspace/7.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3750865486
Short name	T324
Test name
Test status
Simulation time	10484841094 ps
CPU time	7.46 seconds
Started	May 23 02:42:03 PM PDT 24
Finished	May 23 02:42:11 PM PDT 24
Peak memory	216144 kb
Host	smart-e3591416-9da0-48b8-8b3c-af7242c75b4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750865486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3750865486
Directory	/workspace/7.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_rw.4240426235
Short name	T402
Test name
Test status
Simulation time	357488494 ps
CPU time	4.68 seconds
Started	May 23 02:42:02 PM PDT 24
Finished	May 23 02:42:07 PM PDT 24
Peak memory	216276 kb
Host	smart-7504dfe8-3596-4e8b-887b-ddf08fca111f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240426235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4240426235
Directory	/workspace/7.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_sts_read.4150662438
Short name	T680
Test name
Test status
Simulation time	49236154 ps
CPU time	0.8 seconds
Started	May 23 02:42:04 PM PDT 24
Finished	May 23 02:42:05 PM PDT 24
Peak memory	205712 kb
Host	smart-67f4c86d-d99b-443a-afaa-047ac9ca32ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150662438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4150662438
Directory	/workspace/7.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/7.spi_device_upload.710382301
Short name	T752
Test name
Test status
Simulation time	15024453936 ps
CPU time	16.57 seconds
Started	May 23 02:42:03 PM PDT 24
Finished	May 23 02:42:21 PM PDT 24
Peak memory	239336 kb
Host	smart-69f11b7d-62e0-4c50-9f7f-d622dc63141a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710382301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.710382301
Directory	/workspace/7.spi_device_upload/latest

Test location	/workspace/coverage/default/8.spi_device_alert_test.954832644
Short name	T385
Test name
Test status
Simulation time	37530470 ps
CPU time	0.77 seconds
Started	May 23 02:42:31 PM PDT 24
Finished	May 23 02:42:33 PM PDT 24
Peak memory	205624 kb
Host	smart-341dbcca-02ef-4cda-9885-ce716e00890a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954832644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.954832644
Directory	/workspace/8.spi_device_alert_test/latest

Test location	/workspace/coverage/default/8.spi_device_cfg_cmd.2007343180
Short name	T733
Test name
Test status
Simulation time	1895993444 ps
CPU time	6.49 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:27 PM PDT 24
Peak memory	233348 kb
Host	smart-44aee72b-a793-4837-be21-09d7d1f913d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007343180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2007343180
Directory	/workspace/8.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/8.spi_device_csb_read.2441833402
Short name	T699
Test name
Test status
Simulation time	16111912 ps
CPU time	0.79 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:42:22 PM PDT 24
Peak memory	205488 kb
Host	smart-4b0fc2a7-98bd-4c50-9118-03c8d4996946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441833402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2441833402
Directory	/workspace/8.spi_device_csb_read/latest

Test location	/workspace/coverage/default/8.spi_device_flash_all.258623202
Short name	T230
Test name
Test status
Simulation time	3795189477 ps
CPU time	29.1 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:43:02 PM PDT 24
Peak memory	240844 kb
Host	smart-963f4e0e-d530-436a-b6a8-ba6a1374bb4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258623202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.258623202
Directory	/workspace/8.spi_device_flash_all/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm.565565561
Short name	T850
Test name
Test status
Simulation time	2015391382 ps
CPU time	20.61 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:42:54 PM PDT 24
Peak memory	217204 kb
Host	smart-de924aa1-13f4-4184-9487-4d2b2fe7e44e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=565565561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.565565561
Directory	/workspace/8.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.139846011
Short name	T815
Test name
Test status
Simulation time	6984895531 ps
CPU time	61.59 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:43:36 PM PDT 24
Peak memory	224532 kb
Host	smart-df44b0df-2ecd-4c22-b0b6-c5458e0106a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139846011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle. 139846011
Directory	/workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/8.spi_device_flash_mode.3071822132
Short name	T562
Test name
Test status
Simulation time	798504484 ps
CPU time	12.99 seconds
Started	May 23 02:42:34 PM PDT 24
Finished	May 23 02:42:48 PM PDT 24
Peak memory	248788 kb
Host	smart-40266b3e-0de9-4159-b170-d6976ff35fbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071822132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3071822132
Directory	/workspace/8.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/8.spi_device_intercept.2759876511
Short name	T821
Test name
Test status
Simulation time	1256889078 ps
CPU time	14.63 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:34 PM PDT 24
Peak memory	220356 kb
Host	smart-beb1f565-59ed-4a07-a1ac-4ca848a663fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759876511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2759876511
Directory	/workspace/8.spi_device_intercept/latest

Test location	/workspace/coverage/default/8.spi_device_mailbox.2025906780
Short name	T355
Test name
Test status
Simulation time	4056046734 ps
CPU time	53.35 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:43:15 PM PDT 24
Peak memory	234712 kb
Host	smart-8c05625c-5a16-4db5-bc55-133ad066d611
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025906780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2025906780
Directory	/workspace/8.spi_device_mailbox/latest

Test location	/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1208102996
Short name	T101
Test name
Test status
Simulation time	881846822 ps
CPU time	5.91 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:25 PM PDT 24
Peak memory	233836 kb
Host	smart-55ccf100-a1ee-431f-97b4-c29fb5d2e244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208102996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap .1208102996
Directory	/workspace/8.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/8.spi_device_pass_cmd_filtering.1002269290
Short name	T599
Test name
Test status
Simulation time	29895888 ps
CPU time	2.6 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:23 PM PDT 24
Peak memory	221372 kb
Host	smart-ea7bc315-e6ff-4dc8-a318-bec2442e5759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002269290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1002269290
Directory	/workspace/8.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/8.spi_device_read_buffer_direct.396644798
Short name	T547
Test name
Test status
Simulation time	1457181733 ps
CPU time	5.48 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:42:40 PM PDT 24
Peak memory	219120 kb
Host	smart-bad01848-209f-4442-87d2-37d0992fbfad
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396644798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc t.396644798
Directory	/workspace/8.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_all.1253363867
Short name	T833
Test name
Test status
Simulation time	16922676665 ps
CPU time	43.44 seconds
Started	May 23 02:42:21 PM PDT 24
Finished	May 23 02:43:05 PM PDT 24
Peak memory	216304 kb
Host	smart-c3109345-6c11-499e-93c4-f9d8633f3d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253363867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1253363867
Directory	/workspace/8.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1070433088
Short name	T410
Test name
Test status
Simulation time	9002614897 ps
CPU time	21.63 seconds
Started	May 23 02:42:20 PM PDT 24
Finished	May 23 02:42:43 PM PDT 24
Peak memory	216156 kb
Host	smart-6f0b6287-7a31-4c9b-9e89-540926955409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070433088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1070433088
Directory	/workspace/8.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_rw.185599754
Short name	T655
Test name
Test status
Simulation time	632567610 ps
CPU time	2.42 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:22 PM PDT 24
Peak memory	216184 kb
Host	smart-47531b4e-fb91-452b-8909-f6787e9d8ae5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185599754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.185599754
Directory	/workspace/8.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_sts_read.3920910243
Short name	T896
Test name
Test status
Simulation time	254141264 ps
CPU time	0.86 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:20 PM PDT 24
Peak memory	205732 kb
Host	smart-29952252-098c-4873-8937-ffb65b568bb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920910243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3920910243
Directory	/workspace/8.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/8.spi_device_upload.2483843467
Short name	T824
Test name
Test status
Simulation time	10740092995 ps
CPU time	21.15 seconds
Started	May 23 02:42:19 PM PDT 24
Finished	May 23 02:42:41 PM PDT 24
Peak memory	233672 kb
Host	smart-dc0d69ef-7bc8-4d36-91e5-7f199974cc99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483843467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2483843467
Directory	/workspace/8.spi_device_upload/latest

Test location	/workspace/coverage/default/9.spi_device_alert_test.906368217
Short name	T878
Test name
Test status
Simulation time	21227820 ps
CPU time	0.7 seconds
Started	May 23 02:42:37 PM PDT 24
Finished	May 23 02:42:38 PM PDT 24
Peak memory	205308 kb
Host	smart-088bda4a-afaa-4902-8378-19185758c945
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906368217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.906368217
Directory	/workspace/9.spi_device_alert_test/latest

Test location	/workspace/coverage/default/9.spi_device_cfg_cmd.2423112153
Short name	T596
Test name
Test status
Simulation time	2554133846 ps
CPU time	6.41 seconds
Started	May 23 02:42:34 PM PDT 24
Finished	May 23 02:42:41 PM PDT 24
Peak memory	233448 kb
Host	smart-57b4a372-4ab6-4149-b47d-d3c29d8c4475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423112153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2423112153
Directory	/workspace/9.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/9.spi_device_csb_read.3910570682
Short name	T302
Test name
Test status
Simulation time	17600022 ps
CPU time	0.83 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:42:34 PM PDT 24
Peak memory	206520 kb
Host	smart-5bb93bba-f2f2-4b7a-8337-b528f424f8e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910570682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3910570682
Directory	/workspace/9.spi_device_csb_read/latest

Test location	/workspace/coverage/default/9.spi_device_flash_all.3428142428
Short name	T863
Test name
Test status
Simulation time	25774195871 ps
CPU time	103.56 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:44:17 PM PDT 24
Peak memory	249040 kb
Host	smart-da32f978-6099-46ba-8939-8a71311ffecb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428142428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3428142428
Directory	/workspace/9.spi_device_flash_all/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm.850357493
Short name	T195
Test name
Test status
Simulation time	48949648350 ps
CPU time	353.82 seconds
Started	May 23 02:42:34 PM PDT 24
Finished	May 23 02:48:29 PM PDT 24
Peak memory	257220 kb
Host	smart-fa6aac77-0239-4406-b5a2-fb96612f7461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850357493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.850357493
Directory	/workspace/9.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1784338542
Short name	T216
Test name
Test status
Simulation time	85182918995 ps
CPU time	156.89 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:45:11 PM PDT 24
Peak memory	262808 kb
Host	smart-d623dc76-5b80-4052-9042-b3f1e42f830e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784338542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle .1784338542
Directory	/workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/9.spi_device_flash_mode.240119776
Short name	T722
Test name
Test status
Simulation time	9757069770 ps
CPU time	24.46 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:42:59 PM PDT 24
Peak memory	240828 kb
Host	smart-502d5871-9762-4b57-9af5-2eb270c3c94f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240119776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.240119776
Directory	/workspace/9.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/9.spi_device_intercept.1902209785
Short name	T128
Test name
Test status
Simulation time	943964518 ps
CPU time	10.25 seconds
Started	May 23 02:42:35 PM PDT 24
Finished	May 23 02:42:46 PM PDT 24
Peak memory	221380 kb
Host	smart-d9060ebb-e75c-450a-b575-00fce9799eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902209785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1902209785
Directory	/workspace/9.spi_device_intercept/latest

Test location	/workspace/coverage/default/9.spi_device_mailbox.392590774
Short name	T760
Test name
Test status
Simulation time	3400261786 ps
CPU time	40.67 seconds
Started	May 23 02:42:34 PM PDT 24
Finished	May 23 02:43:16 PM PDT 24
Peak memory	236144 kb
Host	smart-6c95559f-8b23-4072-8149-7d520ad17ad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392590774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.392590774
Directory	/workspace/9.spi_device_mailbox/latest

Test location	/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3160621025
Short name	T866
Test name
Test status
Simulation time	4460977947 ps
CPU time	11.23 seconds
Started	May 23 02:42:34 PM PDT 24
Finished	May 23 02:42:46 PM PDT 24
Peak memory	217856 kb
Host	smart-6490f7dc-6b1f-4c2f-8085-6ad79a2f40e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160621025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap .3160621025
Directory	/workspace/9.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/9.spi_device_pass_cmd_filtering.4269323510
Short name	T611
Test name
Test status
Simulation time	88923764 ps
CPU time	2.21 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:42:35 PM PDT 24
Peak memory	216028 kb
Host	smart-194531e3-c73b-4112-a606-849430a260c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269323510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4269323510
Directory	/workspace/9.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/9.spi_device_read_buffer_direct.2264175375
Short name	T662
Test name
Test status
Simulation time	848561196 ps
CPU time	11.13 seconds
Started	May 23 02:42:36 PM PDT 24
Finished	May 23 02:42:48 PM PDT 24
Peak memory	218468 kb
Host	smart-0bf77975-eb8a-4087-b077-ec775fe65f2a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2264175375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.2264175375
Directory	/workspace/9.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/9.spi_device_stress_all.2576557107
Short name	T886
Test name
Test status
Simulation time	119027751855 ps
CPU time	252.33 seconds
Started	May 23 02:42:37 PM PDT 24
Finished	May 23 02:46:50 PM PDT 24
Peak memory	257288 kb
Host	smart-92d72a4d-0983-4cbd-b810-89974535165e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576557107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres s_all.2576557107
Directory	/workspace/9.spi_device_stress_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_all.826532244
Short name	T757
Test name
Test status
Simulation time	2279382647 ps
CPU time	27.51 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:43:01 PM PDT 24
Peak memory	216128 kb
Host	smart-5153b0f0-52d3-49b3-8a47-8abc4418c641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826532244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.826532244
Directory	/workspace/9.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2729321234
Short name	T739
Test name
Test status
Simulation time	2299279495 ps
CPU time	6.54 seconds
Started	May 23 02:42:32 PM PDT 24
Finished	May 23 02:42:39 PM PDT 24
Peak memory	216232 kb
Host	smart-cd4250c6-14dc-4e0c-8276-01af27a839d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729321234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2729321234
Directory	/workspace/9.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_rw.2192988429
Short name	T624
Test name
Test status
Simulation time	169140057 ps
CPU time	1.06 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:42:34 PM PDT 24
Peak memory	207416 kb
Host	smart-67fb9b99-ddd4-4a0b-9b1a-f48baf129936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192988429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2192988429
Directory	/workspace/9.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_sts_read.3308217693
Short name	T944
Test name
Test status
Simulation time	22175605 ps
CPU time	0.79 seconds
Started	May 23 02:42:33 PM PDT 24
Finished	May 23 02:42:34 PM PDT 24
Peak memory	205548 kb
Host	smart-ded2924b-8cbe-4383-8138-60a6db527e62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308217693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3308217693
Directory	/workspace/9.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/9.spi_device_upload.4286792274
Short name	T225
Test name
Test status
Simulation time	2254962620 ps
CPU time	11.96 seconds
Started	May 23 02:42:35 PM PDT 24
Finished	May 23 02:42:47 PM PDT 24
Peak memory	225928 kb
Host	smart-eeced9d9-56ce-4aa1-8f85-fd5ae09a6da9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286792274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4286792274
Directory	/workspace/9.spi_device_upload/latest