Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3436892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3735505

1

T1

2653

T2

945

T3

1023

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4029321	1			T1	4748		T2	146		T3	244
values[0x0]	1570309	1			T1	1325		T2	443		T3	427
values[0x1]	1572767	1			T1	1274		T2	439		T3	466

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2431446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4740951

1

T1

4124

T2

972

T3

1045

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27965	1			T1	14		T2	1		T3	8
valid_sources[0x01]	26337	1			T1	40		T2	3		T3	3
valid_sources[0x02]	27618	1			T1	28		T2	3		T3	6
valid_sources[0x03]	28416	1			T1	30		T2	10		T3	8
valid_sources[0x04]	27275	1			T1	32		T3	3		T6	7
valid_sources[0x05]	29233	1			T1	30		T3	5		T6	2
valid_sources[0x06]	25523	1			T1	29		T2	3		T3	8
valid_sources[0x07]	29685	1			T1	41		T2	1		T3	7
valid_sources[0x08]	26626	1			T1	10		T2	2		T3	9
valid_sources[0x09]	27105	1			T1	33		T3	1		T6	18
valid_sources[0x0a]	27587	1			T1	20		T2	2		T3	8
valid_sources[0x0b]	27549	1			T1	32		T2	1		T3	4
valid_sources[0x0c]	25886	1			T1	29		T2	7		T3	2
valid_sources[0x0d]	27747	1			T1	20		T2	2		T3	7
valid_sources[0x0e]	27689	1			T1	33		T2	3		T3	5
valid_sources[0x0f]	31830	1			T1	19		T2	5		T3	6
valid_sources[0x10]	26502	1			T1	14		T2	3		T3	4
valid_sources[0x11]	28505	1			T1	21		T2	5		T3	3
valid_sources[0x12]	25944	1			T1	25		T2	5		T6	4
valid_sources[0x13]	25954	1			T1	16		T2	4		T3	9
valid_sources[0x14]	28415	1			T1	24		T3	1		T6	3
valid_sources[0x15]	27934	1			T1	25		T2	6		T3	11
valid_sources[0x16]	26662	1			T1	36		T2	4		T3	2
valid_sources[0x17]	31641	1			T1	14		T2	4		T3	3
valid_sources[0x18]	27761	1			T1	47		T2	9		T3	3
valid_sources[0x19]	27281	1			T1	15		T2	4		T3	6
valid_sources[0x1a]	26848	1			T1	26		T2	12		T3	2
valid_sources[0x1b]	27823	1			T1	23		T2	4		T3	3
valid_sources[0x1c]	32971	1			T1	27		T2	5		T3	7
valid_sources[0x1d]	28412	1			T1	46		T2	9		T3	3
valid_sources[0x1e]	28282	1			T1	27		T2	3		T3	6
valid_sources[0x1f]	28539	1			T1	19		T2	6		T3	6
valid_sources[0x20]	24955	1			T1	20		T2	5		T3	3
valid_sources[0x21]	26592	1			T1	26		T3	1		T5	2
valid_sources[0x22]	28529	1			T1	45		T2	8		T3	5
valid_sources[0x23]	28095	1			T1	42		T2	2		T3	4
valid_sources[0x24]	26854	1			T1	22		T2	1		T3	3
valid_sources[0x25]	28527	1			T1	22		T2	1		T3	5
valid_sources[0x26]	25127	1			T1	38		T2	8		T3	3
valid_sources[0x27]	27333	1			T1	29		T2	6		T3	6
valid_sources[0x28]	27613	1			T1	16		T2	1		T3	11
valid_sources[0x29]	28759	1			T1	23		T3	6		T6	9
valid_sources[0x2a]	26467	1			T1	30		T2	2		T3	2
valid_sources[0x2b]	26387	1			T1	34		T2	7		T3	5
valid_sources[0x2c]	27039	1			T1	45		T2	4		T3	6
valid_sources[0x2d]	26252	1			T1	44		T2	4		T3	5
valid_sources[0x2e]	26260	1			T1	20		T2	5		T3	6
valid_sources[0x2f]	28547	1			T1	25		T2	4		T3	4
valid_sources[0x30]	28261	1			T1	17		T2	3		T3	8
valid_sources[0x31]	28265	1			T1	27		T2	4		T3	3
valid_sources[0x32]	28189	1			T1	27		T2	2		T3	2
valid_sources[0x33]	27600	1			T1	19		T2	5		T3	2
valid_sources[0x34]	28956	1			T1	14		T2	8		T3	6
valid_sources[0x35]	26682	1			T1	22		T2	6		T3	7
valid_sources[0x36]	28256	1			T1	30		T2	5		T3	4
valid_sources[0x37]	27673	1			T1	25		T2	3		T3	4
valid_sources[0x38]	28412	1			T1	33		T2	7		T3	9
valid_sources[0x39]	30654	1			T1	31		T2	5		T3	5
valid_sources[0x3a]	31513	1			T1	18		T2	2		T3	3
valid_sources[0x3b]	27604	1			T1	34		T2	3		T3	3
valid_sources[0x3c]	27923	1			T1	19		T3	7		T6	5
valid_sources[0x3d]	26857	1			T1	32		T2	2		T3	10
valid_sources[0x3e]	27757	1			T1	21		T2	5		T3	7
valid_sources[0x3f]	25722	1			T1	21		T2	3		T3	2
valid_sources[0x40]	26726	1			T1	49		T2	6		T3	4
valid_sources[0x41]	26549	1			T1	30		T2	1		T3	2
valid_sources[0x42]	27994	1			T1	45		T2	2		T3	2
valid_sources[0x43]	26526	1			T1	28		T2	4		T3	7
valid_sources[0x44]	26082	1			T1	29		T2	5		T3	1
valid_sources[0x45]	27798	1			T1	27		T2	4		T3	1
valid_sources[0x46]	26704	1			T1	26		T2	4		T3	4
valid_sources[0x47]	26306	1			T1	35		T2	13		T3	3
valid_sources[0x48]	30561	1			T1	30		T2	2		T3	4
valid_sources[0x49]	24908	1			T1	17		T2	6		T3	3
valid_sources[0x4a]	28414	1			T1	35		T2	7		T3	1
valid_sources[0x4b]	27853	1			T1	22		T2	8		T3	4
valid_sources[0x4c]	26796	1			T1	32		T2	6		T3	4
valid_sources[0x4d]	26657	1			T1	27		T2	4		T3	3
valid_sources[0x4e]	31926	1			T1	39		T2	6		T3	2
valid_sources[0x4f]	26884	1			T1	21		T2	3		T3	4
valid_sources[0x50]	27119	1			T1	29		T2	7		T3	9
valid_sources[0x51]	27374	1			T1	34		T2	2		T3	2
valid_sources[0x52]	30777	1			T1	38		T2	1		T3	2
valid_sources[0x53]	27775	1			T1	27		T2	1		T3	7
valid_sources[0x54]	26611	1			T1	28		T2	1		T6	2
valid_sources[0x55]	28095	1			T1	34		T2	1		T3	6
valid_sources[0x56]	26326	1			T1	42		T2	3		T3	5
valid_sources[0x57]	30346	1			T1	36		T2	4		T3	2
valid_sources[0x58]	28006	1			T1	25		T3	1		T5	1
valid_sources[0x59]	27319	1			T1	24		T2	13		T3	7
valid_sources[0x5a]	25420	1			T1	35		T2	2		T3	5
valid_sources[0x5b]	29854	1			T1	44		T2	8		T3	7
valid_sources[0x5c]	25133	1			T1	58		T2	6		T3	4
valid_sources[0x5d]	25642	1			T1	23		T2	1		T3	4
valid_sources[0x5e]	29496	1			T1	28		T2	2		T3	2
valid_sources[0x5f]	27262	1			T1	21		T2	3		T3	5
valid_sources[0x60]	31716	1			T1	19		T2	4		T3	5
valid_sources[0x61]	28162	1			T1	33		T3	12		T7	4
valid_sources[0x62]	29368	1			T1	38		T3	2		T5	1
valid_sources[0x63]	26872	1			T1	31		T2	1		T3	5
valid_sources[0x64]	27070	1			T1	28		T2	4		T3	3
valid_sources[0x65]	27499	1			T1	21		T2	3		T3	4
valid_sources[0x66]	26592	1			T1	34		T2	1		T3	3
valid_sources[0x67]	30561	1			T1	24		T2	4		T3	3
valid_sources[0x68]	26411	1			T1	37		T2	4		T3	5
valid_sources[0x69]	26915	1			T1	30		T2	3		T3	3
valid_sources[0x6a]	27668	1			T1	27		T2	4		T3	4
valid_sources[0x6b]	27542	1			T1	22		T2	2		T3	4
valid_sources[0x6c]	27623	1			T1	39		T2	1		T3	10
valid_sources[0x6d]	51349	1			T1	37		T2	8		T3	5
valid_sources[0x6e]	25186	1			T1	24		T2	11		T3	5
valid_sources[0x6f]	26696	1			T1	33		T2	1		T3	4
valid_sources[0x70]	28894	1			T1	31		T2	12		T3	5
valid_sources[0x71]	25204	1			T1	22		T2	1		T3	1
valid_sources[0x72]	27452	1			T1	25		T2	2		T3	4
valid_sources[0x73]	30438	1			T1	17		T2	6		T3	11
valid_sources[0x74]	29954	1			T1	23		T2	3		T3	1
valid_sources[0x75]	28485	1			T1	36		T2	3		T3	6
valid_sources[0x76]	25525	1			T1	46		T2	2		T3	3
valid_sources[0x77]	26997	1			T1	13		T2	5		T3	4
valid_sources[0x78]	36469	1			T1	30		T3	3		T6	3
valid_sources[0x79]	26994	1			T1	30		T2	2		T3	6
valid_sources[0x7a]	25829	1			T1	27		T2	7		T3	5
valid_sources[0x7b]	28343	1			T1	29		T2	5		T3	5
valid_sources[0x7c]	29495	1			T1	20		T2	5		T5	1
valid_sources[0x7d]	25780	1			T1	33		T2	4		T3	2
valid_sources[0x7e]	28536	1			T1	23		T2	7		T3	6
valid_sources[0x7f]	27780	1			T1	49		T3	5		T7	3
valid_sources[0x80]	27080	1			T1	24		T2	11		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

916872

1

T1

723

T2

68

T3

135

values[0x0]

all_enables

biggest_size

1419773

1

T1

1000

T2

443

T3

426

values[0x1]

all_enables

biggest_size

1398860

1

T1

930

T2

434

T3

462