Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3458752

1

T1

4694

T2

83

T3

114

full_word

3736769

1

T1

2653

T2

945

T3

1023

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7195161	1			T1	7347		T2	1028		T3	1137
auto[TlIntgErrCmd]	116	1			T63	4		T94	4		T95	5
auto[TlIntgErrData]	119	1			T63	5		T94	3		T95	9
auto[TlIntgErrBoth]	125	1			T63	1		T94	3		T95	16

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4032784

1

T1

4748

T2

146

T3

244

auto[1]

3162737

1

T1

2599

T2

882

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3115494	1			T1	4025		T2	78		T3	109
auto[TlIntgErrNone]	partial	auto[1]	342940	1			T1	669		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	917135	1			T1	723		T2	68		T3	135
auto[TlIntgErrNone]	full_word	auto[1]	2819592	1			T1	1930		T2	877		T3	888
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T63	3		T94	2		T95	2
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T63	1		T94	2		T95	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T270	1		T273	1		T274	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T108	1		T275	1		T270	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T63	2		T94	1		T95	5
auto[TlIntgErrData]	partial	auto[1]	48	1			T94	1		T95	2		T108	2
auto[TlIntgErrData]	full_word	auto[0]	16	1			T63	3		T94	1		T95	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T95	1		T108	1		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T95	5		T106	3		T275	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T63	1		T94	3		T95	11
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T146	1		T276	1		T277	3
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T146	2		T273	1		T271	1