Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	498031459	2615787	0	0
gen_wmask[1].MaskCheckPortA_A	498031459	2615787	0	0
gen_wmask[2].MaskCheckPortA_A	498031459	2615787	0	0
gen_wmask[3].MaskCheckPortA_A	498031459	2615787	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498031459	2615787	0	0
T1	437056	3279	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	520011	12232	0	0
T10	3114	0	0	0
T11	12548	832	0	0
T12	642827	10404	0	0
T13	0	832	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498031459	2615787	0	0
T1	437056	3279	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	520011	12232	0	0
T10	3114	0	0	0
T11	12548	832	0	0
T12	642827	10404	0	0
T13	0	832	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498031459	2615787	0	0
T1	437056	3279	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	520011	12232	0	0
T10	3114	0	0	0
T11	12548	832	0	0
T12	642827	10404	0	0
T13	0	832	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498031459	2615787	0	0
T1	437056	3279	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	520011	12232	0	0
T10	3114	0	0	0
T11	12548	832	0	0
T12	642827	10404	0	0
T13	0	832	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	372648194	1750262	0	0
gen_wmask[1].MaskCheckPortA_A	372648194	1750262	0	0
gen_wmask[2].MaskCheckPortA_A	372648194	1750262	0	0
gen_wmask[3].MaskCheckPortA_A	372648194	1750262	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1750262	0	0
T1	354519	1032	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	7197	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	6332	0	0
T13	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1750262	0	0
T1	354519	1032	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	7197	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	6332	0	0
T13	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1750262	0	0
T1	354519	1032	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	7197	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	6332	0	0
T13	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1750262	0	0
T1	354519	1032	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	7197	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	6332	0	0
T13	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	125383265	865525	0	0
gen_wmask[1].MaskCheckPortA_A	125383265	865525	0	0
gen_wmask[2].MaskCheckPortA_A	125383265	865525	0	0
gen_wmask[3].MaskCheckPortA_A	125383265	865525	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	865525	0	0
T1	82537	2247	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5035	0	0
T11	12548	0	0	0
T12	642827	4072	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	865525	0	0
T1	82537	2247	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5035	0	0
T11	12548	0	0	0
T12	642827	4072	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	865525	0	0
T1	82537	2247	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5035	0	0
T11	12548	0	0	0
T12	642827	4072	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	865525	0	0
T1	82537	2247	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5035	0	0
T11	12548	0	0	0
T12	642827	4072	0	0
T14	0	75	0	0
T15	0	95	0	0
T16	0	20	0	0
T17	0	5430	0	0
T18	0	131	0	0
T22	0	336	0	0
T23	0	4180	0	0