Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T9,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Unreachable
1	1	Covered	T1,T9,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T12,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T12,T17
1	0	Covered	T9,T12,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T9,T12,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	623414724	496710228	0	0
CheckNGreaterZero_A	2715	2715	0	0
GntImpliesReady_A	623414724	2976698	0	0
GntImpliesValid_A	623414724	2976698	0	0
GrantKnown_A	623414724	496710228	0	0
IdxKnown_A	623414724	496710228	0	0
IndexIsCorrect_A	623414724	2976698	0	0
LockArbDecision_A	623414724	0	0	0
NoReadyValidNoGrant_A	623414724	0	0	0
ReadyAndValidImplyGrant_A	623414724	2976698	0	0
ReqAndReadyImplyGrant_A	623414724	2976698	0	0
ReqImpliesValid_A	623414724	2976698	0	0
ReqStaysHighUntilGranted0_M	623414724	0	0	0
RoundRobin_A	623414724	3	0	905
ValidKnown_A	623414724	496710228	0	0
gen_data_port_assertion.DataFlow_A	623414724	2976698	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	496710228	0	0
T1	437056	433893	0	0
T2	50949	35067	0	0
T3	57582	33268	0	0
T4	8578	8332	0	0
T5	1261	1174	0	0
T6	31789	22204	0	0
T7	139890	85139	0	0
T8	5591	4930	0	0
T9	866493	513750	0	0
T10	3114	3021	0	0
T11	25096	12548	0	0
T12	1285654	636249	0	0
T13	260465	259584	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T19	0	39392	0	0
T22	0	55960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2715	2715	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	496710228	0	0
T1	437056	433893	0	0
T2	50949	35067	0	0
T3	57582	33268	0	0
T4	8578	8332	0	0
T5	1261	1174	0	0
T6	31789	22204	0	0
T7	139890	85139	0	0
T8	5591	4930	0	0
T9	866493	513750	0	0
T10	3114	3021	0	0
T11	25096	12548	0	0
T12	1285654	636249	0	0
T13	260465	259584	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T19	0	39392	0	0
T22	0	55960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	496710228	0	0
T1	437056	433893	0	0
T2	50949	35067	0	0
T3	57582	33268	0	0
T4	8578	8332	0	0
T5	1261	1174	0	0
T6	31789	22204	0	0
T7	139890	85139	0	0
T8	5591	4930	0	0
T9	866493	513750	0	0
T10	3114	3021	0	0
T11	25096	12548	0	0
T12	1285654	636249	0	0
T13	260465	259584	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T19	0	39392	0	0
T22	0	55960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	3	0	905
T44	282383	1	0	1
T45	575761	1	0	1
T46	0	1	0	0
T47	54154	0	0	1
T48	127725	0	0	1
T49	179668	0	0	1
T50	71977	0	0	1
T51	2858	0	0	1
T52	361236	0	0	1
T53	229779	0	0	1
T54	213345	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	496710228	0	0
T1	437056	433893	0	0
T2	50949	35067	0	0
T3	57582	33268	0	0
T4	8578	8332	0	0
T5	1261	1174	0	0
T6	31789	22204	0	0
T7	139890	85139	0	0
T8	5591	4930	0	0
T9	866493	513750	0	0
T10	3114	3021	0	0
T11	25096	12548	0	0
T12	1285654	636249	0	0
T13	260465	259584	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T19	0	39392	0	0
T22	0	55960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623414724	2976698	0	0
T1	437056	4990	0	0
T2	35155	832	0	0
T3	33517	832	0	0
T4	8402	832	0	0
T5	1261	0	0	0
T6	22281	832	0	0
T7	85374	832	0	0
T8	5015	0	0	0
T9	866493	14987	0	0
T10	3114	0	0	0
T11	25096	832	0	0
T12	1285654	12538	0	0
T13	260465	832	0	0
T14	1376	93	0	0
T15	2056	126	0	0
T16	2504	58	0	0
T17	276970	7291	0	0
T18	1848	145	0	0
T19	39392	0	0	0
T22	0	641	0	0
T23	0	4989	0	0
T24	0	2952	0	0
T27	0	130	0	0
T40	0	802	0	0
T43	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T9,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Unreachable
1	1	Covered	T1,T9,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T9,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125383265	29178333	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	125383265	639203	0	0
GntImpliesValid_A	125383265	639203	0	0
GrantKnown_A	125383265	29178333	0	0
IdxKnown_A	125383265	29178333	0	0
IndexIsCorrect_A	125383265	639203	0	0
LockArbDecision_A	125383265	0	0	0
NoReadyValidNoGrant_A	125383265	0	0	0
ReadyAndValidImplyGrant_A	125383265	639203	0	0
ReqAndReadyImplyGrant_A	125383265	639203	0	0
ReqImpliesValid_A	125383265	639203	0	0
ReqStaysHighUntilGranted0_M	125383265	0	0	0
RoundRobin_A	125383265	0	0	0
ValidKnown_A	125383265	29178333	0	0
gen_data_port_assertion.DataFlow_A	125383265	639203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	29178333	0	0
T1	82537	79440	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	576	0	0
T9	346482	138568	0	0
T11	12548	0	0	0
T12	642827	180088	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T22	0	55960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	29178333	0	0
T1	82537	79440	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	576	0	0
T9	346482	138568	0	0
T11	12548	0	0	0
T12	642827	180088	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T22	0	55960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	29178333	0	0
T1	82537	79440	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	576	0	0
T9	346482	138568	0	0
T11	12548	0	0	0
T12	642827	180088	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T22	0	55960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	29178333	0	0
T1	82537	79440	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	576	0	0
T9	346482	138568	0	0
T11	12548	0	0	0
T12	642827	180088	0	0
T14	0	1376	0	0
T15	0	2056	0	0
T16	0	2504	0	0
T17	0	147136	0	0
T18	0	1848	0	0
T22	0	55960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	639203	0	0
T1	82537	3370	0	0
T2	15794	0	0	0
T3	24065	0	0	0
T4	176	0	0	0
T6	9508	0	0	0
T7	54516	0	0	0
T8	576	0	0	0
T9	346482	5608	0	0
T11	12548	0	0	0
T12	642827	3758	0	0
T14	0	93	0	0
T15	0	126	0	0
T16	0	58	0	0
T17	0	4842	0	0
T18	0	145	0	0
T22	0	641	0	0
T23	0	1911	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T12,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T12,T17
1	0	Covered	T9,T12,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T9,T12,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T12,T17
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125383265	94966372	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	125383265	437446	0	0
GntImpliesValid_A	125383265	437446	0	0
GrantKnown_A	125383265	94966372	0	0
IdxKnown_A	125383265	94966372	0	0
IndexIsCorrect_A	125383265	437446	0	0
LockArbDecision_A	125383265	0	0	0
NoReadyValidNoGrant_A	125383265	0	0	0
ReadyAndValidImplyGrant_A	125383265	437446	0	0
ReqAndReadyImplyGrant_A	125383265	437446	0	0
ReqImpliesValid_A	125383265	437446	0	0
ReqStaysHighUntilGranted0_M	125383265	0	0	0
RoundRobin_A	125383265	0	0	0
ValidKnown_A	125383265	94966372	0	0
gen_data_port_assertion.DataFlow_A	125383265	437446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	94966372	0	0
T2	15794	15794	0	0
T3	24065	23904	0	0
T4	176	176	0	0
T6	9508	9508	0	0
T7	54516	54360	0	0
T8	576	0	0	0
T9	346482	201658	0	0
T11	12548	12548	0	0
T12	642827	456161	0	0
T13	260465	259584	0	0
T19	0	39392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	94966372	0	0
T2	15794	15794	0	0
T3	24065	23904	0	0
T4	176	176	0	0
T6	9508	9508	0	0
T7	54516	54360	0	0
T8	576	0	0	0
T9	346482	201658	0	0
T11	12548	12548	0	0
T12	642827	456161	0	0
T13	260465	259584	0	0
T19	0	39392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	94966372	0	0
T2	15794	15794	0	0
T3	24065	23904	0	0
T4	176	176	0	0
T6	9508	9508	0	0
T7	54516	54360	0	0
T8	576	0	0	0
T9	346482	201658	0	0
T11	12548	12548	0	0
T12	642827	456161	0	0
T13	260465	259584	0	0
T19	0	39392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	94966372	0	0
T2	15794	15794	0	0
T3	24065	23904	0	0
T4	176	176	0	0
T6	9508	9508	0	0
T7	54516	54360	0	0
T8	576	0	0	0
T9	346482	201658	0	0
T11	12548	12548	0	0
T12	642827	456161	0	0
T13	260465	259584	0	0
T19	0	39392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125383265	437446	0	0
T9	346482	942	0	0
T11	12548	0	0	0
T12	642827	1768	0	0
T13	260465	0	0	0
T14	1376	0	0	0
T15	2056	0	0	0
T16	2504	0	0	0
T17	276970	2449	0	0
T18	1848	0	0	0
T19	39392	0	0	0
T23	0	3078	0	0
T24	0	2952	0	0
T25	0	2785	0	0
T27	0	130	0	0
T40	0	802	0	0
T41	0	4517	0	0
T43	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372648194	372565523	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	372648194	1900049	0	0
GntImpliesValid_A	372648194	1900049	0	0
GrantKnown_A	372648194	372565523	0	0
IdxKnown_A	372648194	372565523	0	0
IndexIsCorrect_A	372648194	1900049	0	0
LockArbDecision_A	372648194	0	0	0
NoReadyValidNoGrant_A	372648194	0	0	0
ReadyAndValidImplyGrant_A	372648194	1900049	0	0
ReqAndReadyImplyGrant_A	372648194	1900049	0	0
ReqImpliesValid_A	372648194	1900049	0	0
ReqStaysHighUntilGranted0_M	372648194	0	0	0
RoundRobin_A	372648194	3	0	905
ValidKnown_A	372648194	372565523	0	0
gen_data_port_assertion.DataFlow_A	372648194	1900049	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	372565523	0	0
T1	354519	354453	0	0
T2	19361	19273	0	0
T3	9452	9364	0	0
T4	8226	8156	0	0
T5	1261	1174	0	0
T6	12773	12696	0	0
T7	30858	30779	0	0
T8	4439	4354	0	0
T9	173529	173524	0	0
T10	3114	3021	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	372565523	0	0
T1	354519	354453	0	0
T2	19361	19273	0	0
T3	9452	9364	0	0
T4	8226	8156	0	0
T5	1261	1174	0	0
T6	12773	12696	0	0
T7	30858	30779	0	0
T8	4439	4354	0	0
T9	173529	173524	0	0
T10	3114	3021	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	372565523	0	0
T1	354519	354453	0	0
T2	19361	19273	0	0
T3	9452	9364	0	0
T4	8226	8156	0	0
T5	1261	1174	0	0
T6	12773	12696	0	0
T7	30858	30779	0	0
T8	4439	4354	0	0
T9	173529	173524	0	0
T10	3114	3021	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	3	0	905
T44	282383	1	0	1
T45	575761	1	0	1
T46	0	1	0	0
T47	54154	0	0	1
T48	127725	0	0	1
T49	179668	0	0	1
T50	71977	0	0	1
T51	2858	0	0	1
T52	361236	0	0	1
T53	229779	0	0	1
T54	213345	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	372565523	0	0
T1	354519	354453	0	0
T2	19361	19273	0	0
T3	9452	9364	0	0
T4	8226	8156	0	0
T5	1261	1174	0	0
T6	12773	12696	0	0
T7	30858	30779	0	0
T8	4439	4354	0	0
T9	173529	173524	0	0
T10	3114	3021	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372648194	1900049	0	0
T1	354519	1620	0	0
T2	19361	832	0	0
T3	9452	832	0	0
T4	8226	832	0	0
T5	1261	0	0	0
T6	12773	832	0	0
T7	30858	832	0	0
T8	4439	0	0	0
T9	173529	8437	0	0
T10	3114	0	0	0
T11	0	832	0	0
T12	0	7012	0	0
T13	0	832	0	0