Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	374978110	4154	0	0
addr_swap_data_rd_A	374978110	3435	0	0
addr_swap_mask_rd_A	374978110	3546	0	0
cfg_rd_A	374978110	3685	0	0
cmd_filter_0_rd_A	374978110	7600	0	0
cmd_filter_1_rd_A	374978110	8518	0	0
cmd_filter_2_rd_A	374978110	7108	0	0
cmd_filter_3_rd_A	374978110	8601	0	0
cmd_filter_4_rd_A	374978110	8202	0	0
cmd_filter_5_rd_A	374978110	8156	0	0
cmd_filter_6_rd_A	374978110	7074	0	0
cmd_filter_7_rd_A	374978110	7643	0	0
cmd_info_0_rd_A	374978110	4730	0	0
cmd_info_10_rd_A	374978110	5205	0	0
cmd_info_11_rd_A	374978110	4685	0	0
cmd_info_12_rd_A	374978110	5155	0	0
cmd_info_13_rd_A	374978110	5204	0	0
cmd_info_14_rd_A	374978110	5410	0	0
cmd_info_15_rd_A	374978110	5398	0	0
cmd_info_16_rd_A	374978110	5210	0	0
cmd_info_17_rd_A	374978110	5062	0	0
cmd_info_18_rd_A	374978110	4946	0	0
cmd_info_19_rd_A	374978110	5201	0	0
cmd_info_1_rd_A	374978110	5302	0	0
cmd_info_20_rd_A	374978110	4870	0	0
cmd_info_21_rd_A	374978110	5064	0	0
cmd_info_22_rd_A	374978110	5248	0	0
cmd_info_23_rd_A	374978110	5143	0	0
cmd_info_2_rd_A	374978110	5254	0	0
cmd_info_3_rd_A	374978110	5002	0	0
cmd_info_4_rd_A	374978110	5074	0	0
cmd_info_5_rd_A	374978110	5236	0	0
cmd_info_6_rd_A	374978110	4764	0	0
cmd_info_7_rd_A	374978110	5219	0	0
cmd_info_8_rd_A	374978110	5023	0	0
cmd_info_9_rd_A	374978110	5067	0	0
cmd_info_en4b_rd_A	374978110	3487	0	0
cmd_info_ex4b_rd_A	374978110	3520	0	0
cmd_info_wrdi_rd_A	374978110	3564	0	0
cmd_info_wren_rd_A	374978110	3474	0	0
intercept_en_rd_A	374978110	3850	0	0
intr_enable_rd_A	374978110	4973	0	0
jedec_cc_rd_A	374978110	3384	0	0
jedec_id_rd_A	374978110	3537	0	0
mailbox_addr_rd_A	374978110	3450	0	0
payload_swap_data_rd_A	374978110	3258	0	0
payload_swap_mask_rd_A	374978110	3296	0	0
read_threshold_rd_A	374978110	3316	0	0
tpm_access_0_rd_A	374978110	3686	0	0
tpm_access_1_rd_A	374978110	3490	0	0
tpm_cfg_rd_A	374978110	3824	0	0
tpm_did_vid_rd_A	374978110	3353	0	0
tpm_int_enable_rd_A	374978110	3401	0	0
tpm_int_status_rd_A	374978110	3317	0	0
tpm_int_vector_rd_A	374978110	3300	0	0
tpm_intf_capability_rd_A	374978110	3406	0	0
tpm_rid_rd_A	374978110	3485	0	0
tpm_sts_rd_A	374978110	3280	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4154	0	0
T62	9763	167	0	0
T63	28979	1	0	0
T93	3762	1	0	0
T94	10114	1	0	0
T95	28889	3	0	0
T96	4894	193	0	0
T97	4895	178	0	0
T100	4534	189	0	0
T106	20426	5	0	0
T108	22098	3	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3435	0	0
T61	5388	11	0	0
T112	4698	3	0	0
T114	7264	5	0	0
T116	8748	6	0	0
T135	14911	18	0	0
T138	11630	21	0	0
T145	77111	501	0	0
T146	94137	59	0	0
T147	6605	16	0	0
T148	14533	33	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3546	0	0
T61	5388	2	0	0
T107	5537	11	0	0
T110	4551	7	0	0
T113	3619	1	0	0
T135	14911	60	0	0
T138	11630	17	0	0
T145	77111	554	0	0
T146	94137	76	0	0
T147	6605	35	0	0
T148	14533	25	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3685	0	0
T61	5388	4	0	0
T107	5537	13	0	0
T110	4551	10	0	0
T113	3619	5	0	0
T135	14911	30	0	0
T138	11630	20	0	0
T145	77111	501	0	0
T146	94137	117	0	0
T147	6605	5	0	0
T148	14533	46	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	7600	0	0
T61	5388	9	0	0
T107	5537	137	0	0
T110	4551	1	0	0
T112	4698	116	0	0
T113	3619	4	0	0
T135	14911	18	0	0
T138	11630	5	0	0
T145	77111	516	0	0
T146	94137	490	0	0
T147	6605	35	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	8518	0	0
T61	5388	2	0	0
T107	5537	138	0	0
T112	4698	107	0	0
T113	3619	70	0	0
T135	14911	47	0	0
T138	11630	9	0	0
T145	77111	552	0	0
T146	94137	737	0	0
T147	6605	14	0	0
T148	14533	232	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	7108	0	0
T61	5388	8	0	0
T107	5537	12	0	0
T110	4551	103	0	0
T112	4698	7	0	0
T135	14911	56	0	0
T138	11630	11	0	0
T145	77111	555	0	0
T146	94137	821	0	0
T147	6605	30	0	0
T148	14533	125	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	8601	0	0
T61	5388	6	0	0
T110	4551	99	0	0
T112	4698	3	0	0
T113	3619	65	0	0
T135	14911	42	0	0
T138	11630	13	0	0
T145	77111	520	0	0
T146	94137	1147	0	0
T147	6605	26	0	0
T148	14533	395	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	8202	0	0
T61	5388	88	0	0
T107	5537	10	0	0
T110	4551	102	0	0
T112	4698	124	0	0
T135	14911	24	0	0
T138	11630	19	0	0
T145	77111	528	0	0
T146	94137	1052	0	0
T147	6605	4	0	0
T148	14533	138	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	8156	0	0
T61	5388	85	0	0
T107	5537	116	0	0
T112	4698	4	0	0
T113	3619	61	0	0
T135	14911	77	0	0
T138	11630	17	0	0
T145	77111	541	0	0
T146	94137	1188	0	0
T147	6605	25	0	0
T148	14533	127	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	7074	0	0
T61	5388	6	0	0
T107	5537	129	0	0
T110	4551	2	0	0
T112	4698	120	0	0
T113	3619	66	0	0
T135	14911	35	0	0
T138	11630	34	0	0
T145	77111	555	0	0
T146	94137	1037	0	0
T147	6605	60	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	7643	0	0
T61	5388	5	0	0
T107	5537	5	0	0
T110	4551	120	0	0
T112	4698	8	0	0
T113	3619	49	0	0
T135	14911	65	0	0
T138	11630	36	0	0
T145	77111	619	0	0
T146	94137	1077	0	0
T147	6605	22	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4730	0	0
T61	5388	54	0	0
T107	5537	13	0	0
T110	4551	38	0	0
T112	4698	46	0	0
T135	14911	64	0	0
T138	11630	19	0	0
T145	77111	480	0	0
T146	94137	423	0	0
T147	6605	35	0	0
T148	14533	14	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5205	0	0
T61	5388	7	0	0
T107	5537	49	0	0
T110	4551	35	0	0
T112	4698	9	0	0
T113	3619	8	0	0
T135	14911	30	0	0
T138	11630	11	0	0
T145	77111	527	0	0
T146	94137	461	0	0
T147	6605	2	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4685	0	0
T61	5388	3	0	0
T107	5537	61	0	0
T110	4551	2	0	0
T112	4698	42	0	0
T135	14911	44	0	0
T138	11630	6	0	0
T145	77111	541	0	0
T146	94137	444	0	0
T147	6605	30	0	0
T148	14533	20	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5155	0	0
T61	5388	6	0	0
T107	5537	42	0	0
T112	4698	52	0	0
T113	3619	38	0	0
T135	14911	47	0	0
T138	11630	26	0	0
T145	77111	547	0	0
T146	94137	556	0	0
T147	6605	8	0	0
T148	14533	27	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5204	0	0
T61	5388	49	0	0
T107	5537	3	0	0
T110	4551	45	0	0
T112	4698	7	0	0
T113	3619	1	0	0
T135	14911	53	0	0
T138	11630	20	0	0
T145	77111	547	0	0
T146	94137	611	0	0
T147	6605	37	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5410	0	0
T61	5388	58	0	0
T107	5537	6	0	0
T110	4551	54	0	0
T112	4698	44	0	0
T113	3619	32	0	0
T135	14911	24	0	0
T138	11630	19	0	0
T145	77111	516	0	0
T146	94137	340	0	0
T147	6605	4	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5398	0	0
T61	5388	12	0	0
T107	5537	61	0	0
T110	4551	9	0	0
T112	4698	36	0	0
T113	3619	17	0	0
T135	14911	83	0	0
T138	11630	25	0	0
T145	77111	554	0	0
T146	94137	427	0	0
T147	6605	10	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5210	0	0
T61	5388	7	0	0
T107	5537	54	0	0
T110	4551	50	0	0
T112	4698	48	0	0
T113	3619	33	0	0
T135	14911	84	0	0
T138	11630	23	0	0
T145	77111	571	0	0
T146	94137	371	0	0
T147	6605	5	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5062	0	0
T61	5388	37	0	0
T107	5537	6	0	0
T110	4551	43	0	0
T112	4698	66	0	0
T135	14911	39	0	0
T138	11630	39	0	0
T145	77111	614	0	0
T146	94137	478	0	0
T147	6605	9	0	0
T148	14533	110	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4946	0	0
T61	5388	55	0	0
T107	5537	3	0	0
T110	4551	3	0	0
T112	4698	8	0	0
T113	3619	4	0	0
T135	14911	28	0	0
T138	11630	22	0	0
T145	77111	500	0	0
T146	94137	464	0	0
T147	6605	26	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5201	0	0
T61	5388	63	0	0
T107	5537	8	0	0
T110	4551	2	0	0
T112	4698	63	0	0
T135	14911	52	0	0
T138	11630	20	0	0
T145	77111	583	0	0
T146	94137	480	0	0
T147	6605	7	0	0
T148	14533	53	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5302	0	0
T61	5388	7	0	0
T107	5537	13	0	0
T110	4551	38	0	0
T112	4698	39	0	0
T114	7264	53	0	0
T135	14911	45	0	0
T138	11630	41	0	0
T145	77111	546	0	0
T146	94137	448	0	0
T148	14533	117	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4870	0	0
T61	5388	12	0	0
T107	5537	14	0	0
T110	4551	47	0	0
T112	4698	41	0	0
T113	3619	6	0	0
T135	14911	58	0	0
T138	11630	1	0	0
T145	77111	558	0	0
T146	94137	379	0	0
T147	6605	1	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5064	0	0
T61	5388	76	0	0
T101	22272	5	0	0
T107	5537	14	0	0
T110	4551	3	0	0
T112	4698	5	0	0
T113	3619	3	0	0
T135	14911	18	0	0
T138	11630	17	0	0
T145	77111	531	0	0
T146	94137	502	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5248	0	0
T61	5388	67	0	0
T107	5537	14	0	0
T110	4551	6	0	0
T112	4698	53	0	0
T113	3619	33	0	0
T135	14911	11	0	0
T138	11630	25	0	0
T145	77111	530	0	0
T146	94137	436	0	0
T147	6605	11	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5143	0	0
T61	5388	41	0	0
T107	5537	57	0	0
T110	4551	33	0	0
T112	4698	54	0	0
T113	3619	8	0	0
T135	14911	22	0	0
T138	11630	14	0	0
T145	77111	493	0	0
T146	94137	416	0	0
T147	6605	17	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5254	0	0
T61	5388	52	0	0
T110	4551	49	0	0
T112	4698	2	0	0
T113	3619	25	0	0
T135	14911	38	0	0
T138	11630	12	0	0
T145	77111	541	0	0
T146	94137	498	0	0
T147	6605	13	0	0
T148	14533	108	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5002	0	0
T61	5388	42	0	0
T107	5537	15	0	0
T110	4551	52	0	0
T112	4698	69	0	0
T135	14911	34	0	0
T138	11630	19	0	0
T145	77111	525	0	0
T146	94137	455	0	0
T147	6605	29	0	0
T148	14533	78	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5074	0	0
T61	5388	7	0	0
T107	5537	6	0	0
T110	4551	35	0	0
T112	4698	54	0	0
T113	3619	28	0	0
T135	14911	66	0	0
T138	11630	18	0	0
T145	77111	533	0	0
T146	94137	368	0	0
T147	6605	7	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5236	0	0
T61	5388	12	0	0
T107	5537	2	0	0
T110	4551	30	0	0
T112	4698	2	0	0
T113	3619	17	0	0
T135	14911	20	0	0
T138	11630	9	0	0
T145	77111	501	0	0
T146	94137	346	0	0
T147	6605	31	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4764	0	0
T61	5388	46	0	0
T107	5537	9	0	0
T110	4551	2	0	0
T112	4698	49	0	0
T114	7264	26	0	0
T135	14911	53	0	0
T138	11630	22	0	0
T145	77111	543	0	0
T146	94137	365	0	0
T148	14533	27	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5219	0	0
T61	5388	1	0	0
T101	22272	4	0	0
T107	5537	7	0	0
T110	4551	31	0	0
T112	4698	48	0	0
T113	3619	18	0	0
T135	14911	36	0	0
T138	11630	25	0	0
T145	77111	534	0	0
T146	94137	525	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5023	0	0
T61	5388	61	0	0
T107	5537	3	0	0
T110	4551	1	0	0
T113	3619	6	0	0
T135	14911	20	0	0
T138	11630	5	0	0
T145	77111	585	0	0
T146	94137	451	0	0
T147	6605	32	0	0
T148	14533	22	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	5067	0	0
T61	5388	5	0	0
T107	5537	8	0	0
T110	4551	3	0	0
T112	4698	4	0	0
T113	3619	5	0	0
T135	14911	31	0	0
T138	11630	19	0	0
T145	77111	603	0	0
T146	94137	385	0	0
T147	6605	11	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3487	0	0
T61	5388	11	0	0
T107	5537	6	0	0
T110	4551	3	0	0
T112	4698	13	0	0
T135	14911	13	0	0
T138	11630	7	0	0
T145	77111	638	0	0
T146	94137	53	0	0
T147	6605	25	0	0
T148	14533	32	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3520	0	0
T61	5388	3	0	0
T107	5537	2	0	0
T110	4551	10	0	0
T113	3619	4	0	0
T135	14911	49	0	0
T138	11630	36	0	0
T145	77111	588	0	0
T146	94137	90	0	0
T147	6605	36	0	0
T148	14533	17	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3564	0	0
T61	5388	14	0	0
T107	5537	14	0	0
T110	4551	4	0	0
T112	4698	7	0	0
T113	3619	2	0	0
T135	14911	63	0	0
T138	11630	26	0	0
T145	77111	527	0	0
T146	94137	85	0	0
T147	6605	37	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3474	0	0
T61	5388	8	0	0
T107	5537	9	0	0
T110	4551	9	0	0
T112	4698	9	0	0
T135	14911	73	0	0
T138	11630	4	0	0
T145	77111	576	0	0
T146	94137	110	0	0
T147	6605	2	0	0
T148	14533	21	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3850	0	0
T61	5388	10	0	0
T107	5537	29	0	0
T110	4551	12	0	0
T112	4698	19	0	0
T113	3619	2	0	0
T135	14911	25	0	0
T138	11630	15	0	0
T145	77111	561	0	0
T146	94137	214	0	0
T147	6605	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	4973	0	0
T17	568036	9	0	0
T18	2847	0	0	0
T22	22188	0	0	0
T23	778457	0	0	0
T34	1372	0	0	0
T42	29377	0	0	0
T44	0	13	0	0
T45	0	33	0	0
T55	1636	0	0	0
T77	0	15	0	0
T82	43088	0	0	0
T92	24736	0	0	0
T98	83445	0	0	0
T149	0	33	0	0
T150	0	24	0	0
T151	0	9	0	0
T152	0	19	0	0
T153	0	26	0	0
T154	0	44	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3384	0	0
T61	5388	3	0	0
T107	5537	4	0	0
T110	4551	1	0	0
T112	4698	3	0	0
T135	14911	27	0	0
T138	11630	12	0	0
T145	77111	455	0	0
T146	94137	107	0	0
T147	6605	6	0	0
T148	14533	38	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3537	0	0
T61	5388	10	0	0
T107	5537	5	0	0
T110	4551	14	0	0
T112	4698	9	0	0
T113	3619	4	0	0
T135	14911	74	0	0
T138	11630	10	0	0
T145	77111	519	0	0
T146	94137	94	0	0
T147	6605	24	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3450	0	0
T107	5537	4	0	0
T110	4551	6	0	0
T112	4698	7	0	0
T114	7264	3	0	0
T135	14911	60	0	0
T138	11630	16	0	0
T145	77111	569	0	0
T146	94137	60	0	0
T147	6605	13	0	0
T148	14533	33	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3258	0	0
T61	5388	6	0	0
T107	5537	9	0	0
T110	4551	3	0	0
T112	4698	4	0	0
T113	3619	6	0	0
T135	14911	33	0	0
T138	11630	7	0	0
T145	77111	548	0	0
T146	94137	70	0	0
T147	6605	13	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3296	0	0
T61	5388	4	0	0
T107	5537	9	0	0
T110	4551	8	0	0
T112	4698	1	0	0
T113	3619	4	0	0
T135	14911	57	0	0
T138	11630	19	0	0
T145	77111	521	0	0
T146	94137	46	0	0
T147	6605	5	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3316	0	0
T61	5388	17	0	0
T107	5537	6	0	0
T110	4551	5	0	0
T112	4698	5	0	0
T113	3619	4	0	0
T135	14911	37	0	0
T138	11630	18	0	0
T145	77111	553	0	0
T146	94137	51	0	0
T147	6605	12	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3686	0	0
T61	5388	21	0	0
T107	5537	17	0	0
T110	4551	7	0	0
T112	4698	17	0	0
T113	3619	3	0	0
T135	14911	36	0	0
T138	11630	5	0	0
T145	77111	522	0	0
T146	94137	111	0	0
T147	6605	14	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3490	0	0
T61	5388	1	0	0
T107	5537	11	0	0
T110	4551	3	0	0
T113	3619	5	0	0
T135	14911	72	0	0
T138	11630	14	0	0
T145	77111	529	0	0
T146	94137	47	0	0
T147	6605	42	0	0
T148	14533	23	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3824	0	0
T61	5388	31	0	0
T107	5537	16	0	0
T110	4551	19	0	0
T113	3619	6	0	0
T135	14911	39	0	0
T138	11630	12	0	0
T145	77111	545	0	0
T146	94137	115	0	0
T147	6605	39	0	0
T148	14533	63	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3353	0	0
T61	5388	4	0	0
T107	5537	3	0	0
T110	4551	2	0	0
T112	4698	10	0	0
T135	14911	27	0	0
T138	11630	6	0	0
T145	77111	524	0	0
T146	94137	77	0	0
T147	6605	39	0	0
T148	14533	32	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3401	0	0
T61	5388	7	0	0
T107	5537	15	0	0
T110	4551	2	0	0
T112	4698	2	0	0
T135	14911	31	0	0
T138	11630	29	0	0
T145	77111	574	0	0
T146	94137	65	0	0
T147	6605	12	0	0
T148	14533	11	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3317	0	0
T61	5388	4	0	0
T107	5537	4	0	0
T110	4551	7	0	0
T112	4698	8	0	0
T113	3619	2	0	0
T135	14911	10	0	0
T138	11630	54	0	0
T145	77111	584	0	0
T146	94137	52	0	0
T147	6605	24	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3300	0	0
T61	5388	11	0	0
T107	5537	7	0	0
T112	4698	2	0	0
T113	3619	3	0	0
T135	14911	53	0	0
T138	11630	14	0	0
T145	77111	520	0	0
T146	94137	43	0	0
T147	6605	14	0	0
T148	14533	14	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3406	0	0
T61	5388	7	0	0
T107	5537	6	0	0
T110	4551	2	0	0
T112	4698	9	0	0
T135	14911	53	0	0
T138	11630	19	0	0
T145	77111	581	0	0
T146	94137	42	0	0
T147	6605	1	0	0
T148	14533	21	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3485	0	0
T61	5388	8	0	0
T107	5537	4	0	0
T112	4698	2	0	0
T113	3619	1	0	0
T135	14911	48	0	0
T138	11630	14	0	0
T145	77111	546	0	0
T146	94137	31	0	0
T147	6605	36	0	0
T148	14533	19	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374978110	3280	0	0
T107	5537	4	0	0
T110	4551	8	0	0
T113	3619	5	0	0
T114	7264	4	0	0
T135	14911	37	0	0
T138	11630	15	0	0
T145	77111	500	0	0
T146	94137	62	0	0
T147	6605	16	0	0
T148	14533	14	0	0