| T813 |
/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.104801051 |
|
|
May 26 12:52:08 PM PDT 24 |
May 26 12:52:16 PM PDT 24 |
2139946854 ps |
| T814 |
/workspace/coverage/default/34.spi_device_alert_test.3085997832 |
|
|
May 26 12:55:23 PM PDT 24 |
May 26 12:55:28 PM PDT 24 |
43087996 ps |
| T815 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.468172706 |
|
|
May 26 12:53:28 PM PDT 24 |
May 26 12:53:33 PM PDT 24 |
113805857 ps |
| T816 |
/workspace/coverage/default/41.spi_device_alert_test.2632976643 |
|
|
May 26 12:56:08 PM PDT 24 |
May 26 12:56:10 PM PDT 24 |
21174014 ps |
| T817 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.4129877638 |
|
|
May 26 12:54:02 PM PDT 24 |
May 26 12:54:09 PM PDT 24 |
1507660835 ps |
| T818 |
/workspace/coverage/default/42.spi_device_tpm_all.3302155578 |
|
|
May 26 12:56:09 PM PDT 24 |
May 26 12:56:51 PM PDT 24 |
16125280750 ps |
| T819 |
/workspace/coverage/default/41.spi_device_mailbox.388801974 |
|
|
May 26 12:56:10 PM PDT 24 |
May 26 12:56:15 PM PDT 24 |
310107450 ps |
| T820 |
/workspace/coverage/default/23.spi_device_mailbox.3094433772 |
|
|
May 26 12:54:24 PM PDT 24 |
May 26 12:54:39 PM PDT 24 |
1451399253 ps |
| T821 |
/workspace/coverage/default/37.spi_device_pass_cmd_filtering.168300860 |
|
|
May 26 12:55:35 PM PDT 24 |
May 26 12:55:44 PM PDT 24 |
3615762938 ps |
| T822 |
/workspace/coverage/default/27.spi_device_csb_read.3389458554 |
|
|
May 26 12:54:45 PM PDT 24 |
May 26 12:54:47 PM PDT 24 |
135574793 ps |
| T823 |
/workspace/coverage/default/49.spi_device_tpm_sts_read.547988671 |
|
|
May 26 12:56:47 PM PDT 24 |
May 26 12:56:48 PM PDT 24 |
15135819 ps |
| T824 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.2258778892 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:24 PM PDT 24 |
395356424 ps |
| T825 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.1838555604 |
|
|
May 26 12:51:49 PM PDT 24 |
May 26 12:51:51 PM PDT 24 |
54163287 ps |
| T826 |
/workspace/coverage/default/25.spi_device_cfg_cmd.2877715548 |
|
|
May 26 12:54:36 PM PDT 24 |
May 26 12:54:40 PM PDT 24 |
215984890 ps |
| T827 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1289100442 |
|
|
May 26 12:51:49 PM PDT 24 |
May 26 12:51:52 PM PDT 24 |
974287508 ps |
| T828 |
/workspace/coverage/default/3.spi_device_csb_read.2289274070 |
|
|
May 26 12:52:06 PM PDT 24 |
May 26 12:52:08 PM PDT 24 |
114678872 ps |
| T829 |
/workspace/coverage/default/48.spi_device_read_buffer_direct.136694427 |
|
|
May 26 12:56:36 PM PDT 24 |
May 26 12:56:42 PM PDT 24 |
7729022625 ps |
| T830 |
/workspace/coverage/default/16.spi_device_csb_read.3394370656 |
|
|
May 26 12:53:36 PM PDT 24 |
May 26 12:53:38 PM PDT 24 |
19817699 ps |
| T831 |
/workspace/coverage/default/22.spi_device_csb_read.2805660311 |
|
|
May 26 12:54:16 PM PDT 24 |
May 26 12:54:18 PM PDT 24 |
59250835 ps |
| T832 |
/workspace/coverage/default/23.spi_device_upload.1454988842 |
|
|
May 26 12:54:28 PM PDT 24 |
May 26 12:54:35 PM PDT 24 |
2657221519 ps |
| T833 |
/workspace/coverage/default/25.spi_device_flash_mode.2021916369 |
|
|
May 26 12:54:35 PM PDT 24 |
May 26 12:54:54 PM PDT 24 |
2703610143 ps |
| T834 |
/workspace/coverage/default/2.spi_device_cfg_cmd.1366408743 |
|
|
May 26 12:52:01 PM PDT 24 |
May 26 12:52:20 PM PDT 24 |
7043088754 ps |
| T835 |
/workspace/coverage/default/45.spi_device_upload.1407976559 |
|
|
May 26 12:56:27 PM PDT 24 |
May 26 12:56:32 PM PDT 24 |
748003945 ps |
| T836 |
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.1121669329 |
|
|
May 26 12:53:00 PM PDT 24 |
May 26 12:53:09 PM PDT 24 |
7453325606 ps |
| T267 |
/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3303790834 |
|
|
May 26 12:52:15 PM PDT 24 |
May 26 12:53:44 PM PDT 24 |
7893124215 ps |
| T837 |
/workspace/coverage/default/46.spi_device_alert_test.332766926 |
|
|
May 26 12:56:35 PM PDT 24 |
May 26 12:56:38 PM PDT 24 |
11728746 ps |
| T838 |
/workspace/coverage/default/23.spi_device_tpm_rw.463956215 |
|
|
May 26 12:54:25 PM PDT 24 |
May 26 12:54:27 PM PDT 24 |
12147454 ps |
| T839 |
/workspace/coverage/default/18.spi_device_mailbox.3770963915 |
|
|
May 26 12:53:49 PM PDT 24 |
May 26 12:53:53 PM PDT 24 |
74313349 ps |
| T840 |
/workspace/coverage/default/3.spi_device_cfg_cmd.3480381636 |
|
|
May 26 12:52:07 PM PDT 24 |
May 26 12:52:21 PM PDT 24 |
1414573646 ps |
| T841 |
/workspace/coverage/default/17.spi_device_flash_all.4230811613 |
|
|
May 26 12:53:50 PM PDT 24 |
May 26 12:54:08 PM PDT 24 |
686438740 ps |
| T842 |
/workspace/coverage/default/40.spi_device_intercept.84974710 |
|
|
May 26 12:55:59 PM PDT 24 |
May 26 12:56:02 PM PDT 24 |
32173316 ps |
| T246 |
/workspace/coverage/default/33.spi_device_flash_and_tpm.524640037 |
|
|
May 26 12:55:26 PM PDT 24 |
May 26 01:00:06 PM PDT 24 |
113246284819 ps |
| T843 |
/workspace/coverage/default/33.spi_device_csb_read.2467082993 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:24 PM PDT 24 |
41793979 ps |
| T844 |
/workspace/coverage/default/2.spi_device_mailbox.3663054533 |
|
|
May 26 12:51:58 PM PDT 24 |
May 26 12:52:12 PM PDT 24 |
2805859070 ps |
| T845 |
/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2839674087 |
|
|
May 26 12:56:41 PM PDT 24 |
May 26 12:56:48 PM PDT 24 |
1941592547 ps |
| T846 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.1056794606 |
|
|
May 26 12:56:27 PM PDT 24 |
May 26 12:56:30 PM PDT 24 |
82511904 ps |
| T847 |
/workspace/coverage/default/41.spi_device_flash_all.760299278 |
|
|
May 26 12:56:16 PM PDT 24 |
May 26 01:00:18 PM PDT 24 |
191174409852 ps |
| T848 |
/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1107676389 |
|
|
May 26 12:54:51 PM PDT 24 |
May 26 12:54:59 PM PDT 24 |
6982357262 ps |
| T849 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.1692153757 |
|
|
May 26 12:54:14 PM PDT 24 |
May 26 12:54:20 PM PDT 24 |
190927634 ps |
| T850 |
/workspace/coverage/default/25.spi_device_alert_test.1193420216 |
|
|
May 26 12:54:36 PM PDT 24 |
May 26 12:54:39 PM PDT 24 |
24207818 ps |
| T851 |
/workspace/coverage/default/43.spi_device_cfg_cmd.2705174827 |
|
|
May 26 12:56:19 PM PDT 24 |
May 26 12:56:36 PM PDT 24 |
4301361508 ps |
| T852 |
/workspace/coverage/default/2.spi_device_flash_all.968459846 |
|
|
May 26 12:52:01 PM PDT 24 |
May 26 12:53:41 PM PDT 24 |
57957588619 ps |
| T853 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.3768706353 |
|
|
May 26 12:56:00 PM PDT 24 |
May 26 12:56:02 PM PDT 24 |
19361120 ps |
| T854 |
/workspace/coverage/default/32.spi_device_flash_mode.1390970883 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:34 PM PDT 24 |
3507842211 ps |
| T855 |
/workspace/coverage/default/19.spi_device_alert_test.3203084657 |
|
|
May 26 12:53:54 PM PDT 24 |
May 26 12:53:56 PM PDT 24 |
29226229 ps |
| T856 |
/workspace/coverage/default/10.spi_device_cfg_cmd.2243538517 |
|
|
May 26 12:53:02 PM PDT 24 |
May 26 12:53:07 PM PDT 24 |
1316695951 ps |
| T857 |
/workspace/coverage/default/39.spi_device_read_buffer_direct.3280839828 |
|
|
May 26 12:56:01 PM PDT 24 |
May 26 12:56:10 PM PDT 24 |
1970192619 ps |
| T858 |
/workspace/coverage/default/21.spi_device_tpm_sts_read.1376277041 |
|
|
May 26 12:54:06 PM PDT 24 |
May 26 12:54:08 PM PDT 24 |
36887136 ps |
| T859 |
/workspace/coverage/default/43.spi_device_flash_all.6433120 |
|
|
May 26 12:56:20 PM PDT 24 |
May 26 12:57:55 PM PDT 24 |
90342744681 ps |
| T860 |
/workspace/coverage/default/2.spi_device_read_buffer_direct.1725768336 |
|
|
May 26 12:51:59 PM PDT 24 |
May 26 12:52:04 PM PDT 24 |
246473451 ps |
| T861 |
/workspace/coverage/default/44.spi_device_stress_all.888910604 |
|
|
May 26 12:56:19 PM PDT 24 |
May 26 12:56:22 PM PDT 24 |
738655332 ps |
| T862 |
/workspace/coverage/default/24.spi_device_upload.312920379 |
|
|
May 26 12:54:35 PM PDT 24 |
May 26 12:54:41 PM PDT 24 |
2266826798 ps |
| T863 |
/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.801550133 |
|
|
May 26 12:54:41 PM PDT 24 |
May 26 12:55:01 PM PDT 24 |
6148890825 ps |
| T864 |
/workspace/coverage/default/28.spi_device_tpm_rw.3960314984 |
|
|
May 26 12:54:54 PM PDT 24 |
May 26 12:54:57 PM PDT 24 |
1427607831 ps |
| T865 |
/workspace/coverage/default/6.spi_device_tpm_rw.2725594958 |
|
|
May 26 12:52:33 PM PDT 24 |
May 26 12:52:42 PM PDT 24 |
1281160965 ps |
| T866 |
/workspace/coverage/default/43.spi_device_intercept.1269010694 |
|
|
May 26 12:56:17 PM PDT 24 |
May 26 12:56:27 PM PDT 24 |
2423808457 ps |
| T867 |
/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2185066718 |
|
|
May 26 12:55:19 PM PDT 24 |
May 26 12:55:24 PM PDT 24 |
156210876 ps |
| T868 |
/workspace/coverage/default/7.spi_device_tpm_rw.3896006474 |
|
|
May 26 12:52:34 PM PDT 24 |
May 26 12:52:42 PM PDT 24 |
548669840 ps |
| T869 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.661691889 |
|
|
May 26 12:53:39 PM PDT 24 |
May 26 12:59:15 PM PDT 24 |
150313727760 ps |
| T870 |
/workspace/coverage/default/3.spi_device_intercept.1629679868 |
|
|
May 26 12:52:06 PM PDT 24 |
May 26 12:52:10 PM PDT 24 |
126944364 ps |
| T871 |
/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.415027600 |
|
|
May 26 12:54:53 PM PDT 24 |
May 26 12:55:05 PM PDT 24 |
3910773290 ps |
| T872 |
/workspace/coverage/default/42.spi_device_cfg_cmd.4139671681 |
|
|
May 26 12:56:09 PM PDT 24 |
May 26 12:56:17 PM PDT 24 |
513949363 ps |
| T873 |
/workspace/coverage/default/3.spi_device_tpm_all.903796795 |
|
|
May 26 12:52:04 PM PDT 24 |
May 26 12:52:06 PM PDT 24 |
61179086 ps |
| T874 |
/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3888953160 |
|
|
May 26 12:55:51 PM PDT 24 |
May 26 12:58:13 PM PDT 24 |
47040782416 ps |
| T875 |
/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.376110032 |
|
|
May 26 12:55:37 PM PDT 24 |
May 26 12:56:01 PM PDT 24 |
3314848876 ps |
| T876 |
/workspace/coverage/default/38.spi_device_flash_mode.4107758559 |
|
|
May 26 12:55:50 PM PDT 24 |
May 26 12:55:57 PM PDT 24 |
158602615 ps |
| T877 |
/workspace/coverage/default/13.spi_device_flash_mode.2720513224 |
|
|
May 26 12:53:22 PM PDT 24 |
May 26 12:53:38 PM PDT 24 |
605469485 ps |
| T69 |
/workspace/coverage/default/0.spi_device_sec_cm.4247532030 |
|
|
May 26 12:51:52 PM PDT 24 |
May 26 12:51:53 PM PDT 24 |
133074953 ps |
| T878 |
/workspace/coverage/default/5.spi_device_flash_mode.1757637881 |
|
|
May 26 12:52:24 PM PDT 24 |
May 26 12:52:33 PM PDT 24 |
274243232 ps |
| T879 |
/workspace/coverage/default/26.spi_device_alert_test.3411843910 |
|
|
May 26 12:54:41 PM PDT 24 |
May 26 12:54:44 PM PDT 24 |
42602680 ps |
| T880 |
/workspace/coverage/default/36.spi_device_intercept.3250274756 |
|
|
May 26 12:55:35 PM PDT 24 |
May 26 12:55:41 PM PDT 24 |
157073628 ps |
| T881 |
/workspace/coverage/default/10.spi_device_alert_test.2078353051 |
|
|
May 26 12:53:02 PM PDT 24 |
May 26 12:53:04 PM PDT 24 |
15892739 ps |
| T882 |
/workspace/coverage/default/1.spi_device_read_buffer_direct.2980985391 |
|
|
May 26 12:52:00 PM PDT 24 |
May 26 12:52:07 PM PDT 24 |
1533208321 ps |
| T132 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.4048051239 |
|
|
May 26 12:52:43 PM PDT 24 |
May 26 01:04:07 PM PDT 24 |
150260670206 ps |
| T255 |
/workspace/coverage/default/21.spi_device_flash_all.3924171645 |
|
|
May 26 12:54:14 PM PDT 24 |
May 26 12:54:29 PM PDT 24 |
4441040944 ps |
| T883 |
/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3797275096 |
|
|
May 26 12:56:10 PM PDT 24 |
May 26 12:56:19 PM PDT 24 |
4823893268 ps |
| T884 |
/workspace/coverage/default/0.spi_device_csb_read.1345534037 |
|
|
May 26 12:51:42 PM PDT 24 |
May 26 12:51:43 PM PDT 24 |
62527620 ps |
| T885 |
/workspace/coverage/default/13.spi_device_intercept.418201105 |
|
|
May 26 12:53:15 PM PDT 24 |
May 26 12:53:19 PM PDT 24 |
237649057 ps |
| T886 |
/workspace/coverage/default/15.spi_device_pass_cmd_filtering.4024145 |
|
|
May 26 12:53:29 PM PDT 24 |
May 26 12:53:37 PM PDT 24 |
381329088 ps |
| T887 |
/workspace/coverage/default/3.spi_device_upload.1028990657 |
|
|
May 26 12:52:08 PM PDT 24 |
May 26 12:52:20 PM PDT 24 |
1460814661 ps |
| T888 |
/workspace/coverage/default/34.spi_device_stress_all.1390238173 |
|
|
May 26 12:55:27 PM PDT 24 |
May 26 12:55:30 PM PDT 24 |
367922235 ps |
| T251 |
/workspace/coverage/default/48.spi_device_flash_all.3727403938 |
|
|
May 26 12:56:37 PM PDT 24 |
May 26 12:58:35 PM PDT 24 |
14953779502 ps |
| T889 |
/workspace/coverage/default/28.spi_device_pass_cmd_filtering.2820134175 |
|
|
May 26 12:54:50 PM PDT 24 |
May 26 12:54:54 PM PDT 24 |
214525605 ps |
| T890 |
/workspace/coverage/default/23.spi_device_stress_all.3000316417 |
|
|
May 26 12:54:29 PM PDT 24 |
May 26 12:54:31 PM PDT 24 |
162338288 ps |
| T891 |
/workspace/coverage/default/16.spi_device_intercept.1607487480 |
|
|
May 26 12:53:39 PM PDT 24 |
May 26 12:53:47 PM PDT 24 |
7640871326 ps |
| T247 |
/workspace/coverage/default/11.spi_device_stress_all.2044872480 |
|
|
May 26 12:53:04 PM PDT 24 |
May 26 12:55:26 PM PDT 24 |
9977823820 ps |
| T892 |
/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1865074675 |
|
|
May 26 12:54:06 PM PDT 24 |
May 26 12:54:11 PM PDT 24 |
664090859 ps |
| T893 |
/workspace/coverage/default/29.spi_device_tpm_sts_read.798474185 |
|
|
May 26 12:54:54 PM PDT 24 |
May 26 12:54:57 PM PDT 24 |
52042336 ps |
| T894 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2952374539 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:33 PM PDT 24 |
4517058735 ps |
| T895 |
/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3452295490 |
|
|
May 26 12:55:17 PM PDT 24 |
May 26 12:56:33 PM PDT 24 |
3565177173 ps |
| T896 |
/workspace/coverage/default/26.spi_device_upload.366961783 |
|
|
May 26 12:54:42 PM PDT 24 |
May 26 12:55:03 PM PDT 24 |
34628775275 ps |
| T897 |
/workspace/coverage/default/49.spi_device_tpm_all.1605146650 |
|
|
May 26 12:56:47 PM PDT 24 |
May 26 12:57:03 PM PDT 24 |
2516255035 ps |
| T898 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.1746391771 |
|
|
May 26 12:56:37 PM PDT 24 |
May 26 12:56:48 PM PDT 24 |
979237102 ps |
| T899 |
/workspace/coverage/default/1.spi_device_flash_all.4219251864 |
|
|
May 26 12:51:59 PM PDT 24 |
May 26 12:54:39 PM PDT 24 |
433580859542 ps |
| T900 |
/workspace/coverage/default/33.spi_device_mailbox.3106609004 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:26 PM PDT 24 |
39818694 ps |
| T901 |
/workspace/coverage/default/36.spi_device_flash_and_tpm.2264408106 |
|
|
May 26 12:55:36 PM PDT 24 |
May 26 12:58:44 PM PDT 24 |
85013876731 ps |
| T902 |
/workspace/coverage/default/36.spi_device_mailbox.1676183756 |
|
|
May 26 12:55:40 PM PDT 24 |
May 26 12:55:47 PM PDT 24 |
371014231 ps |
| T903 |
/workspace/coverage/default/24.spi_device_tpm_sts_read.1146426630 |
|
|
May 26 12:54:25 PM PDT 24 |
May 26 12:54:27 PM PDT 24 |
106643243 ps |
| T904 |
/workspace/coverage/default/31.spi_device_cfg_cmd.14033765 |
|
|
May 26 12:55:18 PM PDT 24 |
May 26 12:55:24 PM PDT 24 |
252962174 ps |
| T64 |
/workspace/coverage/default/0.spi_device_ram_cfg.507405132 |
|
|
May 26 12:51:39 PM PDT 24 |
May 26 12:51:41 PM PDT 24 |
15328257 ps |
| T905 |
/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.511470537 |
|
|
May 26 12:55:46 PM PDT 24 |
May 26 12:55:53 PM PDT 24 |
4482603328 ps |
| T906 |
/workspace/coverage/default/3.spi_device_read_buffer_direct.489645163 |
|
|
May 26 12:52:06 PM PDT 24 |
May 26 12:52:12 PM PDT 24 |
550648038 ps |
| T907 |
/workspace/coverage/default/37.spi_device_tpm_all.2167210648 |
|
|
May 26 12:55:35 PM PDT 24 |
May 26 12:56:30 PM PDT 24 |
39965631654 ps |
| T908 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2702897350 |
|
|
May 26 12:52:55 PM PDT 24 |
May 26 12:53:03 PM PDT 24 |
1636631355 ps |
| T909 |
/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3306594681 |
|
|
May 26 12:55:29 PM PDT 24 |
May 26 12:55:43 PM PDT 24 |
16035033226 ps |
| T910 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1352621 |
|
|
May 26 12:54:29 PM PDT 24 |
May 26 12:54:33 PM PDT 24 |
1324067257 ps |
| T911 |
/workspace/coverage/default/20.spi_device_pass_cmd_filtering.3089415975 |
|
|
May 26 12:54:05 PM PDT 24 |
May 26 12:54:18 PM PDT 24 |
7232770959 ps |
| T912 |
/workspace/coverage/default/19.spi_device_tpm_sts_read.2550902271 |
|
|
May 26 12:53:54 PM PDT 24 |
May 26 12:53:56 PM PDT 24 |
482782688 ps |
| T231 |
/workspace/coverage/default/6.spi_device_flash_all.323246039 |
|
|
May 26 12:52:36 PM PDT 24 |
May 26 12:55:49 PM PDT 24 |
113373098812 ps |
| T913 |
/workspace/coverage/default/38.spi_device_cfg_cmd.2569614866 |
|
|
May 26 12:55:44 PM PDT 24 |
May 26 12:55:49 PM PDT 24 |
188798036 ps |
| T914 |
/workspace/coverage/default/29.spi_device_flash_all.3023273004 |
|
|
May 26 12:55:07 PM PDT 24 |
May 26 12:58:04 PM PDT 24 |
33573832867 ps |
| T915 |
/workspace/coverage/default/46.spi_device_read_buffer_direct.4133709289 |
|
|
May 26 12:56:31 PM PDT 24 |
May 26 12:56:35 PM PDT 24 |
95840434 ps |
| T916 |
/workspace/coverage/default/18.spi_device_flash_all.527405369 |
|
|
May 26 12:53:47 PM PDT 24 |
May 26 12:58:39 PM PDT 24 |
80225652032 ps |
| T917 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.189219998 |
|
|
May 26 12:56:37 PM PDT 24 |
May 26 12:56:41 PM PDT 24 |
34274734 ps |
| T918 |
/workspace/coverage/default/17.spi_device_alert_test.1816055576 |
|
|
May 26 12:53:47 PM PDT 24 |
May 26 12:53:49 PM PDT 24 |
69873081 ps |
| T919 |
/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2353920154 |
|
|
May 26 12:55:09 PM PDT 24 |
May 26 12:57:42 PM PDT 24 |
34270868661 ps |
| T920 |
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.318107485 |
|
|
May 26 12:52:53 PM PDT 24 |
May 26 12:53:06 PM PDT 24 |
5983574738 ps |
| T921 |
/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4132546383 |
|
|
May 26 12:53:02 PM PDT 24 |
May 26 12:53:18 PM PDT 24 |
3426478611 ps |
| T922 |
/workspace/coverage/default/35.spi_device_stress_all.2650937445 |
|
|
May 26 12:55:35 PM PDT 24 |
May 26 01:00:33 PM PDT 24 |
61539782151 ps |
| T923 |
/workspace/coverage/default/10.spi_device_mailbox.3251627081 |
|
|
May 26 12:53:05 PM PDT 24 |
May 26 12:53:09 PM PDT 24 |
38977590 ps |
| T924 |
/workspace/coverage/default/6.spi_device_csb_read.2627236493 |
|
|
May 26 12:52:33 PM PDT 24 |
May 26 12:52:35 PM PDT 24 |
13717956 ps |
| T925 |
/workspace/coverage/default/41.spi_device_tpm_all.67568655 |
|
|
May 26 12:56:11 PM PDT 24 |
May 26 12:56:18 PM PDT 24 |
999888199 ps |
| T926 |
/workspace/coverage/default/12.spi_device_stress_all.1854407004 |
|
|
May 26 12:53:12 PM PDT 24 |
May 26 12:54:19 PM PDT 24 |
7466030412 ps |
| T927 |
/workspace/coverage/default/28.spi_device_flash_all.2708784637 |
|
|
May 26 12:54:50 PM PDT 24 |
May 26 12:55:07 PM PDT 24 |
4006890795 ps |
| T928 |
/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.228691160 |
|
|
May 26 12:56:44 PM PDT 24 |
May 26 12:56:47 PM PDT 24 |
106185148 ps |
| T929 |
/workspace/coverage/default/9.spi_device_tpm_rw.4155365395 |
|
|
May 26 12:52:54 PM PDT 24 |
May 26 12:52:57 PM PDT 24 |
394324639 ps |
| T930 |
/workspace/coverage/default/16.spi_device_cfg_cmd.1392477444 |
|
|
May 26 12:53:38 PM PDT 24 |
May 26 12:53:49 PM PDT 24 |
2196834124 ps |
| T931 |
/workspace/coverage/default/21.spi_device_flash_mode.2110372819 |
|
|
May 26 12:54:14 PM PDT 24 |
May 26 12:54:48 PM PDT 24 |
1763894602 ps |
| T932 |
/workspace/coverage/default/26.spi_device_mailbox.1425069451 |
|
|
May 26 12:54:41 PM PDT 24 |
May 26 12:54:53 PM PDT 24 |
552461304 ps |
| T933 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1851798400 |
|
|
May 26 12:55:34 PM PDT 24 |
May 26 12:55:41 PM PDT 24 |
5659479279 ps |
| T133 |
/workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1357576387 |
|
|
May 26 12:56:23 PM PDT 24 |
May 26 01:01:31 PM PDT 24 |
161983505893 ps |
| T934 |
/workspace/coverage/default/5.spi_device_stress_all.2748766864 |
|
|
May 26 12:52:26 PM PDT 24 |
May 26 12:55:17 PM PDT 24 |
19042985077 ps |
| T935 |
/workspace/coverage/default/8.spi_device_intercept.760619171 |
|
|
May 26 12:52:42 PM PDT 24 |
May 26 12:52:45 PM PDT 24 |
270131262 ps |
| T936 |
/workspace/coverage/default/46.spi_device_pass_cmd_filtering.468819057 |
|
|
May 26 12:56:29 PM PDT 24 |
May 26 12:56:32 PM PDT 24 |
29836669 ps |
| T937 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.2494789717 |
|
|
May 26 12:54:34 PM PDT 24 |
May 26 12:54:54 PM PDT 24 |
6239493239 ps |
| T938 |
/workspace/coverage/default/4.spi_device_upload.3154908127 |
|
|
May 26 12:52:14 PM PDT 24 |
May 26 12:52:21 PM PDT 24 |
302544425 ps |
| T939 |
/workspace/coverage/default/3.spi_device_flash_and_tpm.3950145740 |
|
|
May 26 12:52:08 PM PDT 24 |
May 26 12:54:42 PM PDT 24 |
175599885585 ps |
| T940 |
/workspace/coverage/default/31.spi_device_stress_all.1481165051 |
|
|
May 26 12:55:20 PM PDT 24 |
May 26 12:55:57 PM PDT 24 |
25815115757 ps |
| T941 |
/workspace/coverage/default/15.spi_device_tpm_all.1899974151 |
|
|
May 26 12:53:33 PM PDT 24 |
May 26 12:53:51 PM PDT 24 |
45255044137 ps |
| T942 |
/workspace/coverage/default/17.spi_device_mailbox.2748992441 |
|
|
May 26 12:53:48 PM PDT 24 |
May 26 12:54:57 PM PDT 24 |
9718669552 ps |
| T943 |
/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3998785830 |
|
|
May 26 12:55:17 PM PDT 24 |
May 26 12:55:28 PM PDT 24 |
4700339584 ps |
| T944 |
/workspace/coverage/default/9.spi_device_intercept.19443938 |
|
|
May 26 12:52:55 PM PDT 24 |
May 26 12:53:04 PM PDT 24 |
952591216 ps |
| T945 |
/workspace/coverage/default/33.spi_device_cfg_cmd.752193239 |
|
|
May 26 12:55:18 PM PDT 24 |
May 26 12:55:26 PM PDT 24 |
254351304 ps |
| T946 |
/workspace/coverage/default/34.spi_device_flash_and_tpm.1514821527 |
|
|
May 26 12:55:29 PM PDT 24 |
May 26 12:56:02 PM PDT 24 |
5814413568 ps |
| T947 |
/workspace/coverage/default/9.spi_device_alert_test.574082974 |
|
|
May 26 12:52:55 PM PDT 24 |
May 26 12:52:57 PM PDT 24 |
58237213 ps |
| T252 |
/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2069472193 |
|
|
May 26 12:51:51 PM PDT 24 |
May 26 12:52:00 PM PDT 24 |
7485272348 ps |
| T948 |
/workspace/coverage/default/4.spi_device_mailbox.3822733948 |
|
|
May 26 12:52:14 PM PDT 24 |
May 26 12:52:29 PM PDT 24 |
1790287194 ps |
| T949 |
/workspace/coverage/default/18.spi_device_tpm_all.1638613755 |
|
|
May 26 12:53:48 PM PDT 24 |
May 26 12:53:50 PM PDT 24 |
38720602 ps |
| T950 |
/workspace/coverage/default/43.spi_device_flash_and_tpm.1250829127 |
|
|
May 26 12:56:23 PM PDT 24 |
May 26 12:56:45 PM PDT 24 |
1977085383 ps |
| T951 |
/workspace/coverage/default/48.spi_device_flash_mode.3830244920 |
|
|
May 26 12:56:37 PM PDT 24 |
May 26 12:56:57 PM PDT 24 |
4804486056 ps |
| T952 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.554592954 |
|
|
May 26 12:52:16 PM PDT 24 |
May 26 12:52:18 PM PDT 24 |
68289578 ps |
| T953 |
/workspace/coverage/default/5.spi_device_flash_all.1542543836 |
|
|
May 26 12:52:23 PM PDT 24 |
May 26 12:53:21 PM PDT 24 |
13557088440 ps |
| T954 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.3050749365 |
|
|
May 26 12:55:17 PM PDT 24 |
May 26 12:55:33 PM PDT 24 |
3257519016 ps |
| T955 |
/workspace/coverage/default/23.spi_device_tpm_all.1050732146 |
|
|
May 26 12:54:27 PM PDT 24 |
May 26 12:55:15 PM PDT 24 |
8802849368 ps |
| T134 |
/workspace/coverage/default/47.spi_device_flash_and_tpm.3057583691 |
|
|
May 26 12:56:38 PM PDT 24 |
May 26 12:57:15 PM PDT 24 |
12310800580 ps |
| T956 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.221514334 |
|
|
May 26 12:40:13 PM PDT 24 |
May 26 12:40:14 PM PDT 24 |
11653749 ps |
| T110 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1142264818 |
|
|
May 26 12:39:47 PM PDT 24 |
May 26 12:39:49 PM PDT 24 |
46458689 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.2302854312 |
|
|
May 26 12:39:20 PM PDT 24 |
May 26 12:39:21 PM PDT 24 |
18452395 ps |
| T61 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3620645963 |
|
|
May 26 12:39:20 PM PDT 24 |
May 26 12:39:22 PM PDT 24 |
55561023 ps |
| T62 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.312221592 |
|
|
May 26 12:39:38 PM PDT 24 |
May 26 12:39:42 PM PDT 24 |
390613165 ps |
| T135 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3156499806 |
|
|
May 26 12:39:35 PM PDT 24 |
May 26 12:39:39 PM PDT 24 |
149140507 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1808449549 |
|
|
May 26 12:38:43 PM PDT 24 |
May 26 12:38:45 PM PDT 24 |
103831039 ps |
| T63 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1247578609 |
|
|
May 26 12:40:04 PM PDT 24 |
May 26 12:40:13 PM PDT 24 |
301907020 ps |
| T136 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1365148812 |
|
|
May 26 12:38:44 PM PDT 24 |
May 26 12:38:46 PM PDT 24 |
70041244 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.606814186 |
|
|
May 26 12:39:28 PM PDT 24 |
May 26 12:39:30 PM PDT 24 |
235195552 ps |
| T958 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3421611340 |
|
|
May 26 12:39:55 PM PDT 24 |
May 26 12:39:56 PM PDT 24 |
17217717 ps |
| T959 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1729550210 |
|
|
May 26 12:40:23 PM PDT 24 |
May 26 12:40:24 PM PDT 24 |
11890892 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1386824677 |
|
|
May 26 12:39:17 PM PDT 24 |
May 26 12:39:19 PM PDT 24 |
204323800 ps |
| T960 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.3535922544 |
|
|
May 26 12:40:14 PM PDT 24 |
May 26 12:40:15 PM PDT 24 |
112821116 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1174503858 |
|
|
May 26 12:39:19 PM PDT 24 |
May 26 12:39:27 PM PDT 24 |
421511758 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2246068291 |
|
|
May 26 12:39:36 PM PDT 24 |
May 26 12:39:55 PM PDT 24 |
304100513 ps |
| T137 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.153474058 |
|
|
May 26 12:39:33 PM PDT 24 |
May 26 12:39:36 PM PDT 24 |
201817867 ps |
| T145 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1411382413 |
|
|
May 26 12:39:01 PM PDT 24 |
May 26 12:39:19 PM PDT 24 |
4284108227 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3320097294 |
|
|
May 26 12:39:17 PM PDT 24 |
May 26 12:39:22 PM PDT 24 |
204016947 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.1491299515 |
|
|
May 26 12:39:28 PM PDT 24 |
May 26 12:39:30 PM PDT 24 |
14539790 ps |
| T106 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3183604338 |
|
|
May 26 12:39:20 PM PDT 24 |
May 26 12:39:35 PM PDT 24 |
453937531 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2392609874 |
|
|
May 26 12:39:57 PM PDT 24 |
May 26 12:40:01 PM PDT 24 |
257725061 ps |
| T138 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.915414575 |
|
|
May 26 12:40:06 PM PDT 24 |
May 26 12:40:09 PM PDT 24 |
283683832 ps |
| T962 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.4010963349 |
|
|
May 26 12:40:14 PM PDT 24 |
May 26 12:40:16 PM PDT 24 |
20220611 ps |
| T963 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.850686923 |
|
|
May 26 12:40:14 PM PDT 24 |
May 26 12:40:15 PM PDT 24 |
14605109 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2032835691 |
|
|
May 26 12:39:03 PM PDT 24 |
May 26 12:39:07 PM PDT 24 |
156412674 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2790783077 |
|
|
May 26 12:38:45 PM PDT 24 |
May 26 12:39:11 PM PDT 24 |
1376280964 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3774689636 |
|
|
May 26 12:39:56 PM PDT 24 |
May 26 12:39:58 PM PDT 24 |
66068354 ps |
| T108 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3495637650 |
|
|
May 26 12:40:04 PM PDT 24 |
May 26 12:40:20 PM PDT 24 |
235095762 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.477511780 |
|
|
May 26 12:40:06 PM PDT 24 |
May 26 12:40:10 PM PDT 24 |
649674725 ps |
| T967 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1665952926 |
|
|
May 26 12:40:14 PM PDT 24 |
May 26 12:40:16 PM PDT 24 |
84991868 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1847265867 |
|
|
May 26 12:39:27 PM PDT 24 |
May 26 12:39:29 PM PDT 24 |
57712631 ps |
| T102 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2547597990 |
|
|
May 26 12:40:07 PM PDT 24 |
May 26 12:40:12 PM PDT 24 |
144167210 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4133609823 |
|
|
May 26 12:38:36 PM PDT 24 |
May 26 12:38:43 PM PDT 24 |
928115566 ps |
| T275 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2629889256 |
|
|
May 26 12:39:37 PM PDT 24 |
May 26 12:39:44 PM PDT 24 |
115065109 ps |
| T113 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.680022895 |
|
|
May 26 12:40:03 PM PDT 24 |
May 26 12:40:05 PM PDT 24 |
70994130 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.148204311 |
|
|
May 26 12:38:34 PM PDT 24 |
May 26 12:38:35 PM PDT 24 |
78712302 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2823537837 |
|
|
May 26 12:39:56 PM PDT 24 |
May 26 12:40:01 PM PDT 24 |
245370543 ps |
| T270 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1304048464 |
|
|
May 26 12:39:28 PM PDT 24 |
May 26 12:39:41 PM PDT 24 |
744749335 ps |
| T146 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1402398 |
|
|
May 26 12:39:27 PM PDT 24 |
May 26 12:39:49 PM PDT 24 |
2046454425 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1490542857 |
|
|
May 26 12:40:04 PM PDT 24 |
May 26 12:40:05 PM PDT 24 |
29602578 ps |
| T970 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2856705320 |
|
|
May 26 12:39:34 PM PDT 24 |
May 26 12:39:38 PM PDT 24 |
1512768820 ps |
| T147 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1000005502 |
|
|
May 26 12:40:07 PM PDT 24 |
May 26 12:40:09 PM PDT 24 |
264313447 ps |
| T971 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.1759490206 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:07 PM PDT 24 |
123202535 ps |
| T148 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2322945006 |
|
|
May 26 12:39:34 PM PDT 24 |
May 26 12:39:38 PM PDT 24 |
152999581 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.199181657 |
|
|
May 26 12:39:55 PM PDT 24 |
May 26 12:39:58 PM PDT 24 |
195843320 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.896963383 |
|
|
May 26 12:38:36 PM PDT 24 |
May 26 12:38:37 PM PDT 24 |
66912635 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.858497979 |
|
|
May 26 12:39:17 PM PDT 24 |
May 26 12:39:21 PM PDT 24 |
186185429 ps |
| T114 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2711101832 |
|
|
May 26 12:40:03 PM PDT 24 |
May 26 12:40:06 PM PDT 24 |
74137779 ps |
| T975 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.3565706182 |
|
|
May 26 12:38:44 PM PDT 24 |
May 26 12:38:45 PM PDT 24 |
12847598 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3087641457 |
|
|
May 26 12:39:20 PM PDT 24 |
May 26 12:39:29 PM PDT 24 |
111159167 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1186313655 |
|
|
May 26 12:38:53 PM PDT 24 |
May 26 12:38:54 PM PDT 24 |
44492577 ps |
| T116 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4262405450 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:08 PM PDT 24 |
91157266 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1052249624 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:07 PM PDT 24 |
104750261 ps |
| T105 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1853138160 |
|
|
May 26 12:39:55 PM PDT 24 |
May 26 12:40:01 PM PDT 24 |
3067153344 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3864115215 |
|
|
May 26 12:39:19 PM PDT 24 |
May 26 12:39:20 PM PDT 24 |
21871187 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3109062257 |
|
|
May 26 12:40:06 PM PDT 24 |
May 26 12:40:08 PM PDT 24 |
14589046 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3165544018 |
|
|
May 26 12:38:43 PM PDT 24 |
May 26 12:38:44 PM PDT 24 |
13604728 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4125444262 |
|
|
May 26 12:39:19 PM PDT 24 |
May 26 12:39:21 PM PDT 24 |
24796643 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3181145599 |
|
|
May 26 12:39:56 PM PDT 24 |
May 26 12:39:58 PM PDT 24 |
12634333 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.359138418 |
|
|
May 26 12:38:35 PM PDT 24 |
May 26 12:39:00 PM PDT 24 |
7374645922 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3452759212 |
|
|
May 26 12:38:36 PM PDT 24 |
May 26 12:38:38 PM PDT 24 |
12251060 ps |
| T983 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.516351307 |
|
|
May 26 12:40:15 PM PDT 24 |
May 26 12:40:16 PM PDT 24 |
15296456 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3173604808 |
|
|
May 26 12:38:52 PM PDT 24 |
May 26 12:38:58 PM PDT 24 |
197326439 ps |
| T118 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3521953981 |
|
|
May 26 12:39:35 PM PDT 24 |
May 26 12:39:37 PM PDT 24 |
41223056 ps |
| T984 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.881920422 |
|
|
May 26 12:40:04 PM PDT 24 |
May 26 12:40:05 PM PDT 24 |
41655560 ps |
| T985 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.427158608 |
|
|
May 26 12:40:04 PM PDT 24 |
May 26 12:40:05 PM PDT 24 |
15362036 ps |
| T119 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3954097622 |
|
|
May 26 12:39:02 PM PDT 24 |
May 26 12:39:29 PM PDT 24 |
7522197340 ps |
| T986 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2363926498 |
|
|
May 26 12:39:37 PM PDT 24 |
May 26 12:39:40 PM PDT 24 |
91843408 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1223096342 |
|
|
May 26 12:39:09 PM PDT 24 |
May 26 12:39:12 PM PDT 24 |
1047325262 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3850153431 |
|
|
May 26 12:39:40 PM PDT 24 |
May 26 12:39:42 PM PDT 24 |
452604951 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2173301081 |
|
|
May 26 12:40:06 PM PDT 24 |
May 26 12:40:11 PM PDT 24 |
216381169 ps |
| T990 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.2965794482 |
|
|
May 26 12:40:13 PM PDT 24 |
May 26 12:40:15 PM PDT 24 |
12234128 ps |
| T120 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.426155209 |
|
|
May 26 12:39:34 PM PDT 24 |
May 26 12:39:36 PM PDT 24 |
442401762 ps |
| T991 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3892444127 |
|
|
May 26 12:40:17 PM PDT 24 |
May 26 12:40:18 PM PDT 24 |
49035762 ps |
| T276 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2088617684 |
|
|
May 26 12:39:57 PM PDT 24 |
May 26 12:40:05 PM PDT 24 |
201622532 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3408234184 |
|
|
May 26 12:39:02 PM PDT 24 |
May 26 12:39:06 PM PDT 24 |
224939150 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.4186536924 |
|
|
May 26 12:38:53 PM PDT 24 |
May 26 12:38:54 PM PDT 24 |
51363495 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.364975773 |
|
|
May 26 12:39:34 PM PDT 24 |
May 26 12:39:36 PM PDT 24 |
27127352 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.114138560 |
|
|
May 26 12:40:07 PM PDT 24 |
May 26 12:40:10 PM PDT 24 |
103681812 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4099925815 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:10 PM PDT 24 |
1729628988 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1310274747 |
|
|
May 26 12:38:52 PM PDT 24 |
May 26 12:39:14 PM PDT 24 |
316587983 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3371366657 |
|
|
May 26 12:39:58 PM PDT 24 |
May 26 12:40:01 PM PDT 24 |
59579708 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3557112257 |
|
|
May 26 12:39:45 PM PDT 24 |
May 26 12:39:48 PM PDT 24 |
88091713 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3870619031 |
|
|
May 26 12:39:47 PM PDT 24 |
May 26 12:39:50 PM PDT 24 |
256124422 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3349992879 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:09 PM PDT 24 |
59857750 ps |
| T1001 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3592457974 |
|
|
May 26 12:40:11 PM PDT 24 |
May 26 12:40:13 PM PDT 24 |
22791547 ps |
| T1002 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.797182707 |
|
|
May 26 12:40:14 PM PDT 24 |
May 26 12:40:16 PM PDT 24 |
49311714 ps |
| T1003 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2113244009 |
|
|
May 26 12:38:37 PM PDT 24 |
May 26 12:38:54 PM PDT 24 |
5887695609 ps |
| T272 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2806084783 |
|
|
May 26 12:39:58 PM PDT 24 |
May 26 12:40:08 PM PDT 24 |
1395818423 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2781421596 |
|
|
May 26 12:38:44 PM PDT 24 |
May 26 12:38:45 PM PDT 24 |
33373246 ps |
| T268 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1208166369 |
|
|
May 26 12:38:36 PM PDT 24 |
May 26 12:38:41 PM PDT 24 |
671002933 ps |
| T1004 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2719965851 |
|
|
May 26 12:39:28 PM PDT 24 |
May 26 12:39:33 PM PDT 24 |
417461275 ps |
| T1005 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2792347721 |
|
|
May 26 12:39:56 PM PDT 24 |
May 26 12:39:58 PM PDT 24 |
40312185 ps |
| T1006 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1871929542 |
|
|
May 26 12:40:05 PM PDT 24 |
May 26 12:40:08 PM PDT 24 |
306174035 ps |