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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.30 94.11 98.61 89.36 97.14 95.84 99.20


Total test records in report: 1080
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T1007 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.726365284 May 26 12:39:19 PM PDT 24 May 26 12:39:23 PM PDT 24 524501692 ps
T1008 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1597830028 May 26 12:40:06 PM PDT 24 May 26 12:40:10 PM PDT 24 55450333 ps
T1009 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3152398567 May 26 12:40:15 PM PDT 24 May 26 12:40:16 PM PDT 24 64233908 ps
T1010 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1745997155 May 26 12:39:32 PM PDT 24 May 26 12:39:33 PM PDT 24 28307779 ps
T1011 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1671349674 May 26 12:40:15 PM PDT 24 May 26 12:40:17 PM PDT 24 22452055 ps
T1012 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.820941538 May 26 12:39:45 PM PDT 24 May 26 12:39:49 PM PDT 24 161044163 ps
T1013 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3204431895 May 26 12:40:06 PM PDT 24 May 26 12:40:07 PM PDT 24 36846350 ps
T1014 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3545195319 May 26 12:40:15 PM PDT 24 May 26 12:40:16 PM PDT 24 16156191 ps
T277 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.401801786 May 26 12:39:43 PM PDT 24 May 26 12:39:58 PM PDT 24 423918353 ps
T1015 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4254625672 May 26 12:39:35 PM PDT 24 May 26 12:39:36 PM PDT 24 27931646 ps
T1016 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3379404433 May 26 12:39:45 PM PDT 24 May 26 12:39:48 PM PDT 24 91921667 ps
T1017 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1617671618 May 26 12:39:25 PM PDT 24 May 26 12:39:30 PM PDT 24 571335146 ps
T1018 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3567861519 May 26 12:40:00 PM PDT 24 May 26 12:40:03 PM PDT 24 84881233 ps
T1019 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3278069767 May 26 12:39:56 PM PDT 24 May 26 12:40:05 PM PDT 24 563419499 ps
T1020 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1867774783 May 26 12:38:36 PM PDT 24 May 26 12:38:38 PM PDT 24 17585666 ps
T1021 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2476562936 May 26 12:39:26 PM PDT 24 May 26 12:39:27 PM PDT 24 32729038 ps
T1022 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2095593581 May 26 12:40:13 PM PDT 24 May 26 12:40:14 PM PDT 24 48360028 ps
T1023 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2795061964 May 26 12:39:09 PM PDT 24 May 26 12:39:10 PM PDT 24 18613689 ps
T1024 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3912961335 May 26 12:39:34 PM PDT 24 May 26 12:39:38 PM PDT 24 1912563272 ps
T1025 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2864188950 May 26 12:38:37 PM PDT 24 May 26 12:38:53 PM PDT 24 558363201 ps
T1026 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.531036954 May 26 12:38:51 PM PDT 24 May 26 12:38:59 PM PDT 24 105466573 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3617598302 May 26 12:38:36 PM PDT 24 May 26 12:38:49 PM PDT 24 809107145 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1437372028 May 26 12:39:10 PM PDT 24 May 26 12:39:39 PM PDT 24 1887001681 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1533367112 May 26 12:39:18 PM PDT 24 May 26 12:39:21 PM PDT 24 123439113 ps
T1030 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2887826230 May 26 12:39:40 PM PDT 24 May 26 12:39:42 PM PDT 24 67918960 ps
T1031 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3710141330 May 26 12:39:26 PM PDT 24 May 26 12:39:28 PM PDT 24 27899164 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1969923302 May 26 12:39:18 PM PDT 24 May 26 12:39:19 PM PDT 24 23153023 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.706601063 May 26 12:39:10 PM PDT 24 May 26 12:39:13 PM PDT 24 258183536 ps
T269 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.385947729 May 26 12:39:26 PM PDT 24 May 26 12:39:29 PM PDT 24 104085191 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2459953600 May 26 12:38:36 PM PDT 24 May 26 12:38:38 PM PDT 24 29802042 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1524878716 May 26 12:38:51 PM PDT 24 May 26 12:38:55 PM PDT 24 428607522 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4072282583 May 26 12:39:17 PM PDT 24 May 26 12:39:20 PM PDT 24 46047339 ps
T273 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2533995937 May 26 12:39:00 PM PDT 24 May 26 12:39:18 PM PDT 24 285414774 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3156631699 May 26 12:40:08 PM PDT 24 May 26 12:40:15 PM PDT 24 790493888 ps
T1038 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2295251792 May 26 12:40:09 PM PDT 24 May 26 12:40:10 PM PDT 24 34162150 ps
T1039 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2644955551 May 26 12:39:17 PM PDT 24 May 26 12:39:31 PM PDT 24 502343784 ps
T1040 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2848468018 May 26 12:40:12 PM PDT 24 May 26 12:40:14 PM PDT 24 13084219 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.137366304 May 26 12:40:07 PM PDT 24 May 26 12:40:09 PM PDT 24 29338046 ps
T1042 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.134462685 May 26 12:39:48 PM PDT 24 May 26 12:39:53 PM PDT 24 209700933 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.142774035 May 26 12:39:02 PM PDT 24 May 26 12:39:04 PM PDT 24 221341322 ps
T1044 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3819627705 May 26 12:39:57 PM PDT 24 May 26 12:40:00 PM PDT 24 34434188 ps
T271 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3333036329 May 26 12:40:06 PM PDT 24 May 26 12:40:28 PM PDT 24 833338424 ps
T1045 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1002178147 May 26 12:39:34 PM PDT 24 May 26 12:39:39 PM PDT 24 97729322 ps
T1046 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3213488265 May 26 12:40:14 PM PDT 24 May 26 12:40:16 PM PDT 24 13375198 ps
T81 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2494499142 May 26 12:39:10 PM PDT 24 May 26 12:39:12 PM PDT 24 35723070 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.923508240 May 26 12:39:18 PM PDT 24 May 26 12:39:23 PM PDT 24 290639205 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2710688264 May 26 12:39:33 PM PDT 24 May 26 12:39:50 PM PDT 24 3188244734 ps
T1049 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.437965467 May 26 12:39:47 PM PDT 24 May 26 12:39:48 PM PDT 24 17534870 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3607577853 May 26 12:39:40 PM PDT 24 May 26 12:39:41 PM PDT 24 17901645 ps
T274 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3816414509 May 26 12:40:04 PM PDT 24 May 26 12:40:12 PM PDT 24 108380208 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2030143537 May 26 12:40:04 PM PDT 24 May 26 12:40:05 PM PDT 24 51239294 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.117106644 May 26 12:39:28 PM PDT 24 May 26 12:39:37 PM PDT 24 2436324243 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1474326458 May 26 12:38:35 PM PDT 24 May 26 12:38:39 PM PDT 24 482518177 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3645679438 May 26 12:38:54 PM PDT 24 May 26 12:38:57 PM PDT 24 161503604 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2967113611 May 26 12:39:33 PM PDT 24 May 26 12:39:38 PM PDT 24 162388528 ps
T1056 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2367747623 May 26 12:40:16 PM PDT 24 May 26 12:40:17 PM PDT 24 31508063 ps
T1057 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.891805838 May 26 12:40:13 PM PDT 24 May 26 12:40:14 PM PDT 24 20169814 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.608456043 May 26 12:40:08 PM PDT 24 May 26 12:40:12 PM PDT 24 223391481 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3778900905 May 26 12:39:17 PM PDT 24 May 26 12:39:19 PM PDT 24 32199001 ps
T1060 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1499418320 May 26 12:40:07 PM PDT 24 May 26 12:40:09 PM PDT 24 261187603 ps
T1061 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2918828449 May 26 12:40:16 PM PDT 24 May 26 12:40:18 PM PDT 24 156576351 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2053536491 May 26 12:39:14 PM PDT 24 May 26 12:39:18 PM PDT 24 392393415 ps
T1063 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3611934052 May 26 12:40:15 PM PDT 24 May 26 12:40:17 PM PDT 24 25498427 ps
T1064 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2466445841 May 26 12:40:09 PM PDT 24 May 26 12:40:10 PM PDT 24 32234463 ps
T1065 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.951311875 May 26 12:40:15 PM PDT 24 May 26 12:40:17 PM PDT 24 14916076 ps
T1066 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4031945197 May 26 12:40:14 PM PDT 24 May 26 12:40:15 PM PDT 24 13797562 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2317453529 May 26 12:38:52 PM PDT 24 May 26 12:38:55 PM PDT 24 26788486 ps
T1068 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1291837778 May 26 12:40:15 PM PDT 24 May 26 12:40:16 PM PDT 24 14913198 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4044595666 May 26 12:39:19 PM PDT 24 May 26 12:39:23 PM PDT 24 606124086 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2969979325 May 26 12:39:36 PM PDT 24 May 26 12:39:41 PM PDT 24 573300378 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.763592649 May 26 12:39:28 PM PDT 24 May 26 12:39:34 PM PDT 24 790728783 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.982719375 May 26 12:39:02 PM PDT 24 May 26 12:39:04 PM PDT 24 250641648 ps
T1073 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1863153931 May 26 12:40:12 PM PDT 24 May 26 12:40:13 PM PDT 24 13528374 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4063288664 May 26 12:39:10 PM PDT 24 May 26 12:39:11 PM PDT 24 50949856 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2341450145 May 26 12:39:31 PM PDT 24 May 26 12:39:32 PM PDT 24 61774201 ps
T1076 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.105376992 May 26 12:39:55 PM PDT 24 May 26 12:39:59 PM PDT 24 39208105 ps
T1077 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2583450114 May 26 12:39:32 PM PDT 24 May 26 12:39:34 PM PDT 24 115206308 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3574829568 May 26 12:39:19 PM PDT 24 May 26 12:39:45 PM PDT 24 7649052094 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3664388689 May 26 12:38:36 PM PDT 24 May 26 12:38:38 PM PDT 24 52470922 ps
T1080 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2313155897 May 26 12:39:26 PM PDT 24 May 26 12:39:28 PM PDT 24 152671758 ps

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1067701125
Short name T9
Test name
Test status
Simulation time 44494713087 ps
CPU time 169.48 seconds
Started May 26 12:52:53 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 249000 kb
Host smart-a10692f8-9594-4c28-bf31-3c878f5463a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067701125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1067701125
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4098249990
Short name T17
Test name
Test status
Simulation time 23668458735 ps
CPU time 57.61 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:57:28 PM PDT 24
Peak memory 242928 kb
Host smart-49896017-df75-416f-865f-39ef7cb3bbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098249990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4098249990
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3548470177
Short name T35
Test name
Test status
Simulation time 57963740060 ps
CPU time 546.12 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 257296 kb
Host smart-2c461283-3ddd-4dad-a1d5-84095f208a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548470177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3548470177
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3620645963
Short name T61
Test name
Test status
Simulation time 55561023 ps
CPU time 1.77 seconds
Started May 26 12:39:20 PM PDT 24
Finished May 26 12:39:22 PM PDT 24
Peak memory 215096 kb
Host smart-c19969ed-b969-4373-b2bf-cd3e5f36406b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620645963 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3620645963
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.372998424
Short name T12
Test name
Test status
Simulation time 129594709085 ps
CPU time 115.04 seconds
Started May 26 12:54:29 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 256480 kb
Host smart-d460c7f6-c4f9-41de-9e29-b32b0a26e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372998424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.372998424
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3914352766
Short name T29
Test name
Test status
Simulation time 83100981896 ps
CPU time 808.32 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 01:06:52 PM PDT 24
Peak memory 264220 kb
Host smart-72af7c60-7e53-4ae2-9941-b42945d8801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914352766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3914352766
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1086368603
Short name T155
Test name
Test status
Simulation time 63179072248 ps
CPU time 698.31 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 01:06:17 PM PDT 24
Peak memory 271624 kb
Host smart-8a35d15a-2011-4efe-bbdc-5faf625aa45a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086368603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1086368603
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.507405132
Short name T64
Test name
Test status
Simulation time 15328257 ps
CPU time 0.74 seconds
Started May 26 12:51:39 PM PDT 24
Finished May 26 12:51:41 PM PDT 24
Peak memory 215924 kb
Host smart-3adeac7d-a8db-440c-824c-9b4d122c50f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507405132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.507405132
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1928446811
Short name T176
Test name
Test status
Simulation time 75829138402 ps
CPU time 679.92 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 01:05:36 PM PDT 24
Peak memory 254128 kb
Host smart-ad3f90a0-4dc4-4bcb-af30-7cb92fdcd505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928446811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1928446811
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.507231053
Short name T159
Test name
Test status
Simulation time 19141720513 ps
CPU time 263.24 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:56:40 PM PDT 24
Peak memory 250004 kb
Host smart-6b8ec79a-7daa-48cf-9760-dc4215bafe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507231053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.507231053
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2246068291
Short name T95
Test name
Test status
Simulation time 304100513 ps
CPU time 18.99 seconds
Started May 26 12:39:36 PM PDT 24
Finished May 26 12:39:55 PM PDT 24
Peak memory 215112 kb
Host smart-98b347dc-8034-4287-b8f7-38491ebd2e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246068291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2246068291
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2865655352
Short name T141
Test name
Test status
Simulation time 4404829600 ps
CPU time 13.92 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:42 PM PDT 24
Peak memory 238568 kb
Host smart-b82bfeb4-2aa7-4162-9de9-94cb2530a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865655352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2865655352
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2572611245
Short name T57
Test name
Test status
Simulation time 16857256 ps
CPU time 0.68 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:12 PM PDT 24
Peak memory 204804 kb
Host smart-c4322494-32af-48b1-a752-8143cb192da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572611245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2572611245
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1142264818
Short name T110
Test name
Test status
Simulation time 46458689 ps
CPU time 1.49 seconds
Started May 26 12:39:47 PM PDT 24
Finished May 26 12:39:49 PM PDT 24
Peak memory 206856 kb
Host smart-473bc7dd-5892-4508-b7da-4b9effa0d1df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142264818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1142264818
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1182546560
Short name T210
Test name
Test status
Simulation time 13059908085 ps
CPU time 181.3 seconds
Started May 26 12:53:57 PM PDT 24
Finished May 26 12:56:59 PM PDT 24
Peak memory 255104 kb
Host smart-bc5df626-901a-4610-bff9-915edd433cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182546560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1182546560
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2703599084
Short name T40
Test name
Test status
Simulation time 50962753945 ps
CPU time 214.74 seconds
Started May 26 12:56:43 PM PDT 24
Finished May 26 01:00:19 PM PDT 24
Peak memory 249088 kb
Host smart-ff79f92f-1189-4af1-ab1f-b484d7c805aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703599084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2703599084
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2032835691
Short name T100
Test name
Test status
Simulation time 156412674 ps
CPU time 3.44 seconds
Started May 26 12:39:03 PM PDT 24
Finished May 26 12:39:07 PM PDT 24
Peak memory 216252 kb
Host smart-12341193-5c36-4a9b-845e-fad119fcf93b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032835691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
032835691
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.594501487
Short name T229
Test name
Test status
Simulation time 23982771784 ps
CPU time 234.46 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:59:31 PM PDT 24
Peak memory 249928 kb
Host smart-ae8a514b-fb00-4fcc-8ac9-db05fd7892af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594501487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.594501487
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2232997674
Short name T152
Test name
Test status
Simulation time 143117191999 ps
CPU time 737.41 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 01:04:34 PM PDT 24
Peak memory 268364 kb
Host smart-0cd25ba2-e050-4a49-b6c9-ab26f2711487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232997674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2232997674
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1486204717
Short name T32
Test name
Test status
Simulation time 29714726634 ps
CPU time 59.84 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 256460 kb
Host smart-fb2519e5-6d46-4882-a0b5-ec8a0e4ef7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486204717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1486204717
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1018966190
Short name T298
Test name
Test status
Simulation time 144869150818 ps
CPU time 311.76 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:59:26 PM PDT 24
Peak memory 251044 kb
Host smart-eb44740e-173f-4ec7-987c-34e9f59b39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018966190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1018966190
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2330397911
Short name T44
Test name
Test status
Simulation time 30364693803 ps
CPU time 338.62 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 01:00:22 PM PDT 24
Peak memory 268560 kb
Host smart-28f7a825-e26c-4177-963e-4203829f43b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330397911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2330397911
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.70553720
Short name T248
Test name
Test status
Simulation time 16966858556 ps
CPU time 218.84 seconds
Started May 26 12:51:51 PM PDT 24
Finished May 26 12:55:31 PM PDT 24
Peak memory 284664 kb
Host smart-bb2d9244-bd41-446d-81dc-573f847493ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70553720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_
all.70553720
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4247532030
Short name T69
Test name
Test status
Simulation time 133074953 ps
CPU time 0.96 seconds
Started May 26 12:51:52 PM PDT 24
Finished May 26 12:51:53 PM PDT 24
Peak memory 234952 kb
Host smart-9b79d095-8c55-4d2d-8125-155aab569330
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247532030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4247532030
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3125939278
Short name T241
Test name
Test status
Simulation time 165009888981 ps
CPU time 545.16 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 01:03:49 PM PDT 24
Peak memory 270684 kb
Host smart-7bb0542c-7723-48fd-b906-8d70c6675109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125939278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3125939278
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3113386018
Short name T162
Test name
Test status
Simulation time 14672509429 ps
CPU time 62.15 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:56:31 PM PDT 24
Peak memory 249000 kb
Host smart-32acdeef-970b-41cd-8378-ca04d3bcf9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113386018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3113386018
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.524640037
Short name T246
Test name
Test status
Simulation time 113246284819 ps
CPU time 277.59 seconds
Started May 26 12:55:26 PM PDT 24
Finished May 26 01:00:06 PM PDT 24
Peak memory 261272 kb
Host smart-fe759f27-2dbf-415e-9d5f-d76da165673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524640037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.524640037
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.643091102
Short name T256
Test name
Test status
Simulation time 45655061787 ps
CPU time 372.52 seconds
Started May 26 12:52:53 PM PDT 24
Finished May 26 12:59:07 PM PDT 24
Peak memory 248952 kb
Host smart-3e9f270d-d9ee-4b7d-a6eb-1a35c079916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643091102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.643091102
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2892402642
Short name T163
Test name
Test status
Simulation time 17597941262 ps
CPU time 69.63 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:54:13 PM PDT 24
Peak memory 249240 kb
Host smart-e2b145ca-8dc4-4c70-be15-d42c3eb93806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892402642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2892402642
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2324617458
Short name T245
Test name
Test status
Simulation time 59025995915 ps
CPU time 287.85 seconds
Started May 26 12:55:51 PM PDT 24
Finished May 26 01:00:41 PM PDT 24
Peak memory 264516 kb
Host smart-d83b8eeb-1064-46cf-9ba7-35317625f1e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324617458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2324617458
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3585739711
Short name T242
Test name
Test status
Simulation time 14905640034 ps
CPU time 246.69 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:56:07 PM PDT 24
Peak memory 264204 kb
Host smart-22d49c0b-ab6d-4a95-8c93-cd912ba2f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585739711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3585739711
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1208166369
Short name T268
Test name
Test status
Simulation time 671002933 ps
CPU time 3.86 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:41 PM PDT 24
Peak memory 215600 kb
Host smart-d0216ef3-06a6-4ee3-b139-edf453969b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208166369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
208166369
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2533995937
Short name T273
Test name
Test status
Simulation time 285414774 ps
CPU time 16.89 seconds
Started May 26 12:39:00 PM PDT 24
Finished May 26 12:39:18 PM PDT 24
Peak memory 215048 kb
Host smart-9048d0fa-a5b8-4d54-acda-b9bce4a6d9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533995937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2533995937
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3596230136
Short name T352
Test name
Test status
Simulation time 8752130028 ps
CPU time 23.53 seconds
Started May 26 12:51:40 PM PDT 24
Finished May 26 12:52:04 PM PDT 24
Peak memory 216140 kb
Host smart-76f46ce7-6248-4015-9e0a-f3e36c3a7d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596230136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3596230136
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.820470626
Short name T202
Test name
Test status
Simulation time 94673879992 ps
CPU time 399.22 seconds
Started May 26 12:53:30 PM PDT 24
Finished May 26 01:00:09 PM PDT 24
Peak memory 250092 kb
Host smart-e3ace31d-eab7-424a-bce9-2513748e0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820470626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.820470626
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1063630509
Short name T266
Test name
Test status
Simulation time 16666377936 ps
CPU time 177.85 seconds
Started May 26 12:53:32 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 249004 kb
Host smart-ffe5f759-5df3-4bba-ae3b-04877fcd5a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063630509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1063630509
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.697172107
Short name T243
Test name
Test status
Simulation time 97274528159 ps
CPU time 184.72 seconds
Started May 26 12:53:39 PM PDT 24
Finished May 26 12:56:44 PM PDT 24
Peak memory 255448 kb
Host smart-c20bd962-0dd2-4207-9e3c-d15277ea7468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697172107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.697172107
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3046078461
Short name T333
Test name
Test status
Simulation time 369979158 ps
CPU time 9.13 seconds
Started May 26 12:53:49 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 235544 kb
Host smart-cfe688e4-cac4-4adc-9cf4-cc12c4c57878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046078461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3046078461
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.432487645
Short name T19
Test name
Test status
Simulation time 1682064490 ps
CPU time 13.61 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:52:37 PM PDT 24
Peak memory 218372 kb
Host smart-022b940f-08a0-412a-84a0-3a328929be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432487645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.432487645
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1402398
Short name T146
Test name
Test status
Simulation time 2046454425 ps
CPU time 22.24 seconds
Started May 26 12:39:27 PM PDT 24
Finished May 26 12:39:49 PM PDT 24
Peak memory 215488 kb
Host smart-3459640d-191a-4235-b8b1-8a7e7a78d925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl
_intg_err.1402398
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1788532160
Short name T470
Test name
Test status
Simulation time 3251642305 ps
CPU time 57.35 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:52:57 PM PDT 24
Peak memory 249540 kb
Host smart-d40190e2-18fe-4a81-9f94-2c806ebefa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788532160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1788532160
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.777402213
Short name T187
Test name
Test status
Simulation time 33681254258 ps
CPU time 217.39 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:57:33 PM PDT 24
Peak memory 257176 kb
Host smart-44c62026-ead6-4ced-9641-d3e79bfaa47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777402213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.777402213
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3116302213
Short name T325
Test name
Test status
Simulation time 6945249794 ps
CPU time 57.1 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:56:25 PM PDT 24
Peak memory 240424 kb
Host smart-d0ec4a18-71f5-48bb-88f7-fd0c0f6affff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116302213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3116302213
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3265351174
Short name T289
Test name
Test status
Simulation time 21725824429 ps
CPU time 73.36 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:57:44 PM PDT 24
Peak memory 227240 kb
Host smart-53eeb788-583c-43dd-bf07-a5cbc59a7d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265351174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3265351174
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2471156866
Short name T264
Test name
Test status
Simulation time 53768173098 ps
CPU time 291.64 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:57:56 PM PDT 24
Peak memory 270224 kb
Host smart-df51e454-0009-4e91-8515-5ff6a9a35542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471156866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2471156866
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3924171645
Short name T255
Test name
Test status
Simulation time 4441040944 ps
CPU time 14.14 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:29 PM PDT 24
Peak memory 240752 kb
Host smart-734c33d8-03db-461e-bad2-f9af98e5bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924171645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3924171645
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3922324764
Short name T30
Test name
Test status
Simulation time 167983486086 ps
CPU time 421.97 seconds
Started May 26 12:54:40 PM PDT 24
Finished May 26 01:01:45 PM PDT 24
Peak memory 255888 kb
Host smart-900ad7ea-5203-4202-877e-9ac6d94a7be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922324764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3922324764
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1033560654
Short name T265
Test name
Test status
Simulation time 28766530141 ps
CPU time 21.27 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:54:58 PM PDT 24
Peak memory 229228 kb
Host smart-c4c53943-b8fb-46af-a4d2-ff10107f271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033560654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1033560654
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3328385919
Short name T240
Test name
Test status
Simulation time 36590846088 ps
CPU time 181.21 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:58:21 PM PDT 24
Peak memory 253892 kb
Host smart-287c9bca-c6a0-4fcb-a6c4-9f622d1c84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328385919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3328385919
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3708942264
Short name T244
Test name
Test status
Simulation time 35919559384 ps
CPU time 376.56 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 273548 kb
Host smart-e12e1128-aca9-4d34-9d63-12ac84b3f770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708942264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3708942264
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3704792273
Short name T31
Test name
Test status
Simulation time 3017211952 ps
CPU time 74.26 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:57:17 PM PDT 24
Peak memory 248984 kb
Host smart-c5c42d69-df44-46db-8ba4-faa0715f7fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704792273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3704792273
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1555853338
Short name T158
Test name
Test status
Simulation time 18239468079 ps
CPU time 189.11 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:59:40 PM PDT 24
Peak memory 255460 kb
Host smart-ce80f492-3a59-4d2d-a9e6-8a084a8b69ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555853338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1555853338
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3473200270
Short name T6
Test name
Test status
Simulation time 311546450 ps
CPU time 4.09 seconds
Started May 26 12:53:06 PM PDT 24
Finished May 26 12:53:11 PM PDT 24
Peak memory 222688 kb
Host smart-c433f812-fb8f-4080-bc5b-2718c9ad0f0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3473200270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3473200270
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.148204311
Short name T79
Test name
Test status
Simulation time 78712302 ps
CPU time 0.91 seconds
Started May 26 12:38:34 PM PDT 24
Finished May 26 12:38:35 PM PDT 24
Peak memory 206552 kb
Host smart-e7c190ce-6748-4f43-9a57-f0b4dcf1ef2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148204311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.148204311
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1683006849
Short name T356
Test name
Test status
Simulation time 15198513 ps
CPU time 0.76 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:51:52 PM PDT 24
Peak memory 205548 kb
Host smart-296b9c5f-5ca5-40e9-a761-3423e2d575f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683006849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1683006849
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.176975803
Short name T2
Test name
Test status
Simulation time 201717268 ps
CPU time 5.08 seconds
Started May 26 12:53:06 PM PDT 24
Finished May 26 12:53:11 PM PDT 24
Peak memory 233716 kb
Host smart-78f320ff-c1d7-4800-8eab-acbf02b7666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176975803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.176975803
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3106186461
Short name T21
Test name
Test status
Simulation time 72960889403 ps
CPU time 371.68 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 01:00:18 PM PDT 24
Peak memory 254760 kb
Host smart-89deec82-0bbf-4aba-8dc9-839aa32a8424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106186461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3106186461
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2113244009
Short name T1003
Test name
Test status
Simulation time 5887695609 ps
CPU time 16.84 seconds
Started May 26 12:38:37 PM PDT 24
Finished May 26 12:38:54 PM PDT 24
Peak memory 215048 kb
Host smart-14bd3995-4f49-483d-9896-0c1400d47bbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113244009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2113244009
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3617598302
Short name T1027
Test name
Test status
Simulation time 809107145 ps
CPU time 13.13 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:49 PM PDT 24
Peak memory 206700 kb
Host smart-e84b871b-500b-4ade-a105-0ec595b8a843
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617598302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3617598302
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3664388689
Short name T1079
Test name
Test status
Simulation time 52470922 ps
CPU time 2.01 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:38 PM PDT 24
Peak memory 215276 kb
Host smart-4fc0d588-2dce-4c31-8621-19f5b2ec51ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664388689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3664388689
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2459953600
Short name T1034
Test name
Test status
Simulation time 29802042 ps
CPU time 1.84 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:38 PM PDT 24
Peak memory 206872 kb
Host smart-02550513-95d1-4906-8f42-cd1f772460f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459953600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
459953600
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.896963383
Short name T973
Test name
Test status
Simulation time 66912635 ps
CPU time 0.73 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:37 PM PDT 24
Peak memory 203520 kb
Host smart-bc35929a-d55b-4d4f-914d-852896dd537d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896963383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.896963383
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1867774783
Short name T1020
Test name
Test status
Simulation time 17585666 ps
CPU time 1.27 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:38 PM PDT 24
Peak memory 215192 kb
Host smart-5bd0ff42-a364-4cef-bb54-03fc158678f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867774783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1867774783
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3452759212
Short name T982
Test name
Test status
Simulation time 12251060 ps
CPU time 0.66 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:38 PM PDT 24
Peak memory 203700 kb
Host smart-05124921-0374-4e68-9f6c-ff5d65b6c5be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452759212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3452759212
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1474326458
Short name T1053
Test name
Test status
Simulation time 482518177 ps
CPU time 3.02 seconds
Started May 26 12:38:35 PM PDT 24
Finished May 26 12:38:39 PM PDT 24
Peak memory 215008 kb
Host smart-8ec742f8-606d-44af-a7de-dcca6c4e7c44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474326458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1474326458
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4133609823
Short name T101
Test name
Test status
Simulation time 928115566 ps
CPU time 6.61 seconds
Started May 26 12:38:36 PM PDT 24
Finished May 26 12:38:43 PM PDT 24
Peak memory 215196 kb
Host smart-d4e7aa40-f8e1-430d-8c3d-b7253dcd2bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133609823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
133609823
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.359138418
Short name T981
Test name
Test status
Simulation time 7374645922 ps
CPU time 23.84 seconds
Started May 26 12:38:35 PM PDT 24
Finished May 26 12:39:00 PM PDT 24
Peak memory 215068 kb
Host smart-4009d02c-daf7-46ff-bf40-0b4d6ddbdf70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359138418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.359138418
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1310274747
Short name T121
Test name
Test status
Simulation time 316587983 ps
CPU time 21.54 seconds
Started May 26 12:38:52 PM PDT 24
Finished May 26 12:39:14 PM PDT 24
Peak memory 215032 kb
Host smart-e73a6fc9-9618-4869-ad57-98ff8a39568f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310274747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1310274747
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2790783077
Short name T964
Test name
Test status
Simulation time 1376280964 ps
CPU time 26.19 seconds
Started May 26 12:38:45 PM PDT 24
Finished May 26 12:39:11 PM PDT 24
Peak memory 206928 kb
Host smart-d38ca091-f059-49d8-9746-3e04f6c1a4ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790783077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2790783077
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2781421596
Short name T80
Test name
Test status
Simulation time 33373246 ps
CPU time 1.25 seconds
Started May 26 12:38:44 PM PDT 24
Finished May 26 12:38:45 PM PDT 24
Peak memory 216080 kb
Host smart-364ace22-82d7-4263-b83c-35b724148bb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781421596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2781421596
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1524878716
Short name T1035
Test name
Test status
Simulation time 428607522 ps
CPU time 3.5 seconds
Started May 26 12:38:51 PM PDT 24
Finished May 26 12:38:55 PM PDT 24
Peak memory 218248 kb
Host smart-a22c7241-24b1-43c0-8676-d688752d52f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524878716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1524878716
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1365148812
Short name T136
Test name
Test status
Simulation time 70041244 ps
CPU time 2.08 seconds
Started May 26 12:38:44 PM PDT 24
Finished May 26 12:38:46 PM PDT 24
Peak memory 206836 kb
Host smart-3d40f42d-a1e6-4891-a6a0-977ce0e94808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365148812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
365148812
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3565706182
Short name T975
Test name
Test status
Simulation time 12847598 ps
CPU time 0.69 seconds
Started May 26 12:38:44 PM PDT 24
Finished May 26 12:38:45 PM PDT 24
Peak memory 203772 kb
Host smart-d03dc4ea-5c25-4a0f-b8ae-05c6f2e747f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565706182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
565706182
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1808449549
Short name T111
Test name
Test status
Simulation time 103831039 ps
CPU time 1.64 seconds
Started May 26 12:38:43 PM PDT 24
Finished May 26 12:38:45 PM PDT 24
Peak memory 215028 kb
Host smart-70d01036-e78f-43db-8c1f-7033d4136ec1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808449549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1808449549
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3165544018
Short name T979
Test name
Test status
Simulation time 13604728 ps
CPU time 0.71 seconds
Started May 26 12:38:43 PM PDT 24
Finished May 26 12:38:44 PM PDT 24
Peak memory 203728 kb
Host smart-66eb86ff-4a40-41c1-8cf7-564bb769d891
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165544018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3165544018
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3645679438
Short name T1054
Test name
Test status
Simulation time 161503604 ps
CPU time 2.85 seconds
Started May 26 12:38:54 PM PDT 24
Finished May 26 12:38:57 PM PDT 24
Peak memory 215028 kb
Host smart-ec0ba7bf-ca83-4ebd-bc05-a5c4ca01ba7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645679438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3645679438
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2864188950
Short name T1025
Test name
Test status
Simulation time 558363201 ps
CPU time 15.4 seconds
Started May 26 12:38:37 PM PDT 24
Finished May 26 12:38:53 PM PDT 24
Peak memory 215352 kb
Host smart-71dfe0dd-d710-4f19-8b83-ac94fab14436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864188950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2864188950
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2967113611
Short name T1055
Test name
Test status
Simulation time 162388528 ps
CPU time 3.74 seconds
Started May 26 12:39:33 PM PDT 24
Finished May 26 12:39:38 PM PDT 24
Peak memory 217080 kb
Host smart-bb652be2-6d6b-43af-b565-e37cfc4eafb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967113611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2967113611
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2887826230
Short name T1030
Test name
Test status
Simulation time 67918960 ps
CPU time 1.32 seconds
Started May 26 12:39:40 PM PDT 24
Finished May 26 12:39:42 PM PDT 24
Peak memory 206156 kb
Host smart-f4e9564c-1447-4051-8c11-dada7176d3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887826230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2887826230
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.364975773
Short name T994
Test name
Test status
Simulation time 27127352 ps
CPU time 0.71 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:36 PM PDT 24
Peak memory 203668 kb
Host smart-41d5cb8b-4fd8-453e-b444-6b1663fc386c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364975773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.364975773
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.153474058
Short name T137
Test name
Test status
Simulation time 201817867 ps
CPU time 1.89 seconds
Started May 26 12:39:33 PM PDT 24
Finished May 26 12:39:36 PM PDT 24
Peak memory 215040 kb
Host smart-a6d932fb-846b-469e-b5f9-3d2faa7c4a56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153474058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.153474058
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.312221592
Short name T62
Test name
Test status
Simulation time 390613165 ps
CPU time 3.54 seconds
Started May 26 12:39:38 PM PDT 24
Finished May 26 12:39:42 PM PDT 24
Peak memory 215232 kb
Host smart-c6b34a60-a8fe-4f0e-8f8a-8719b1dba93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312221592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.312221592
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2629889256
Short name T275
Test name
Test status
Simulation time 115065109 ps
CPU time 7.09 seconds
Started May 26 12:39:37 PM PDT 24
Finished May 26 12:39:44 PM PDT 24
Peak memory 215084 kb
Host smart-2749caf1-bc16-476e-9c14-28e0acc105ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629889256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2629889256
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.820941538
Short name T1012
Test name
Test status
Simulation time 161044163 ps
CPU time 3.8 seconds
Started May 26 12:39:45 PM PDT 24
Finished May 26 12:39:49 PM PDT 24
Peak memory 216840 kb
Host smart-4e682f01-9bab-47a8-b05e-63707a7b5ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820941538 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.820941538
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3521953981
Short name T118
Test name
Test status
Simulation time 41223056 ps
CPU time 1.63 seconds
Started May 26 12:39:35 PM PDT 24
Finished May 26 12:39:37 PM PDT 24
Peak memory 215100 kb
Host smart-57407c55-048a-4eae-91b0-f62244b303c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521953981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3521953981
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4254625672
Short name T1015
Test name
Test status
Simulation time 27931646 ps
CPU time 0.72 seconds
Started May 26 12:39:35 PM PDT 24
Finished May 26 12:39:36 PM PDT 24
Peak memory 203464 kb
Host smart-3a050126-4c15-446c-b424-3da7e528b63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254625672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4254625672
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3156499806
Short name T135
Test name
Test status
Simulation time 149140507 ps
CPU time 3.05 seconds
Started May 26 12:39:35 PM PDT 24
Finished May 26 12:39:39 PM PDT 24
Peak memory 215396 kb
Host smart-015cdb9b-2f87-4bd0-aa2c-ffd9b3aea489
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156499806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3156499806
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1002178147
Short name T1045
Test name
Test status
Simulation time 97729322 ps
CPU time 3.81 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:39 PM PDT 24
Peak memory 215396 kb
Host smart-25f757f0-278d-4810-bfe0-b34d8212363b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002178147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1002178147
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3557112257
Short name T998
Test name
Test status
Simulation time 88091713 ps
CPU time 2.85 seconds
Started May 26 12:39:45 PM PDT 24
Finished May 26 12:39:48 PM PDT 24
Peak memory 216384 kb
Host smart-eafe5f2f-e0f5-4188-b1ae-444075257d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557112257 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3557112257
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.437965467
Short name T1049
Test name
Test status
Simulation time 17534870 ps
CPU time 0.72 seconds
Started May 26 12:39:47 PM PDT 24
Finished May 26 12:39:48 PM PDT 24
Peak memory 203472 kb
Host smart-4e68362b-f41e-47d4-bff5-fb05b374be6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437965467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.437965467
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.134462685
Short name T1042
Test name
Test status
Simulation time 209700933 ps
CPU time 4.78 seconds
Started May 26 12:39:48 PM PDT 24
Finished May 26 12:39:53 PM PDT 24
Peak memory 215040 kb
Host smart-5f7c17e8-51bd-4374-96c0-b11b1e40b910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134462685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.134462685
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3379404433
Short name T1016
Test name
Test status
Simulation time 91921667 ps
CPU time 2.85 seconds
Started May 26 12:39:45 PM PDT 24
Finished May 26 12:39:48 PM PDT 24
Peak memory 215372 kb
Host smart-6a004526-c036-40e1-9d7d-8f0d6a4822ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379404433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3379404433
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.401801786
Short name T277
Test name
Test status
Simulation time 423918353 ps
CPU time 14.79 seconds
Started May 26 12:39:43 PM PDT 24
Finished May 26 12:39:58 PM PDT 24
Peak memory 214996 kb
Host smart-b07ca5bf-c639-486b-bb00-984778fa79bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401801786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.401801786
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2823537837
Short name T968
Test name
Test status
Simulation time 245370543 ps
CPU time 4.03 seconds
Started May 26 12:39:56 PM PDT 24
Finished May 26 12:40:01 PM PDT 24
Peak memory 217744 kb
Host smart-9d6cdef2-a9c4-4541-8321-6475f3fb344c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823537837 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2823537837
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.105376992
Short name T1076
Test name
Test status
Simulation time 39208105 ps
CPU time 2.88 seconds
Started May 26 12:39:55 PM PDT 24
Finished May 26 12:39:59 PM PDT 24
Peak memory 215076 kb
Host smart-0b658fa4-a9b2-4765-98bc-39105d80e438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105376992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.105376992
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2792347721
Short name T1005
Test name
Test status
Simulation time 40312185 ps
CPU time 0.76 seconds
Started May 26 12:39:56 PM PDT 24
Finished May 26 12:39:58 PM PDT 24
Peak memory 203812 kb
Host smart-e1956ad6-64f4-43b7-9294-872a7f8c4f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792347721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2792347721
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3774689636
Short name T965
Test name
Test status
Simulation time 66068354 ps
CPU time 2.08 seconds
Started May 26 12:39:56 PM PDT 24
Finished May 26 12:39:58 PM PDT 24
Peak memory 207004 kb
Host smart-f2f33e49-7775-41da-844c-fe4a1ce3c3f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774689636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3774689636
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3870619031
Short name T999
Test name
Test status
Simulation time 256124422 ps
CPU time 2.47 seconds
Started May 26 12:39:47 PM PDT 24
Finished May 26 12:39:50 PM PDT 24
Peak memory 215284 kb
Host smart-a9e693c9-d7c1-4b88-966d-4bb47f2f4306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870619031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3870619031
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2806084783
Short name T272
Test name
Test status
Simulation time 1395818423 ps
CPU time 9.19 seconds
Started May 26 12:39:58 PM PDT 24
Finished May 26 12:40:08 PM PDT 24
Peak memory 216228 kb
Host smart-5874b045-ab17-4200-bf51-6855837de39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806084783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2806084783
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.199181657
Short name T972
Test name
Test status
Simulation time 195843320 ps
CPU time 3.36 seconds
Started May 26 12:39:55 PM PDT 24
Finished May 26 12:39:58 PM PDT 24
Peak memory 217692 kb
Host smart-0fe4e4a8-55df-4130-a65b-60d1a58486c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199181657 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.199181657
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3371366657
Short name T997
Test name
Test status
Simulation time 59579708 ps
CPU time 2.02 seconds
Started May 26 12:39:58 PM PDT 24
Finished May 26 12:40:01 PM PDT 24
Peak memory 206772 kb
Host smart-d05927c0-8f19-471d-bb60-7bc120da000c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371366657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3371366657
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3421611340
Short name T958
Test name
Test status
Simulation time 17217717 ps
CPU time 0.78 seconds
Started May 26 12:39:55 PM PDT 24
Finished May 26 12:39:56 PM PDT 24
Peak memory 203548 kb
Host smart-f8d88fc7-3796-42ed-82cd-e56b1b9365cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421611340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3421611340
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3567861519
Short name T1018
Test name
Test status
Simulation time 84881233 ps
CPU time 1.7 seconds
Started May 26 12:40:00 PM PDT 24
Finished May 26 12:40:03 PM PDT 24
Peak memory 215096 kb
Host smart-89c1657d-83f3-4164-9e7e-bd7f1d2c5f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567861519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3567861519
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2392609874
Short name T97
Test name
Test status
Simulation time 257725061 ps
CPU time 3.78 seconds
Started May 26 12:39:57 PM PDT 24
Finished May 26 12:40:01 PM PDT 24
Peak memory 215168 kb
Host smart-8de5c40a-1fda-4dd7-91f1-60363509f42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392609874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2392609874
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2088617684
Short name T276
Test name
Test status
Simulation time 201622532 ps
CPU time 6.79 seconds
Started May 26 12:39:57 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 215024 kb
Host smart-e37d7513-02ea-41ae-9206-b01c5adb534c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088617684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2088617684
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1597830028
Short name T1008
Test name
Test status
Simulation time 55450333 ps
CPU time 3.79 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 217156 kb
Host smart-e4128726-0d65-4d1a-9956-60f8715e4b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597830028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1597830028
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3819627705
Short name T1044
Test name
Test status
Simulation time 34434188 ps
CPU time 2.35 seconds
Started May 26 12:39:57 PM PDT 24
Finished May 26 12:40:00 PM PDT 24
Peak memory 215020 kb
Host smart-390c1530-9b06-49c7-bfac-6a04030bc9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819627705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3819627705
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3181145599
Short name T980
Test name
Test status
Simulation time 12634333 ps
CPU time 0.73 seconds
Started May 26 12:39:56 PM PDT 24
Finished May 26 12:39:58 PM PDT 24
Peak memory 203448 kb
Host smart-b984e177-8051-443a-b412-e447efd75b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181145599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3181145599
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3349992879
Short name T1000
Test name
Test status
Simulation time 59857750 ps
CPU time 3.96 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:09 PM PDT 24
Peak memory 215028 kb
Host smart-d96e9a13-9af6-4e2d-8dd7-53f38788c700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349992879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3349992879
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1853138160
Short name T105
Test name
Test status
Simulation time 3067153344 ps
CPU time 5.39 seconds
Started May 26 12:39:55 PM PDT 24
Finished May 26 12:40:01 PM PDT 24
Peak memory 215220 kb
Host smart-a70e2e4d-028c-4f97-b9d3-272bd34a5ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853138160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1853138160
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3278069767
Short name T1019
Test name
Test status
Simulation time 563419499 ps
CPU time 7.79 seconds
Started May 26 12:39:56 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 215132 kb
Host smart-a483158d-3054-4f40-93b2-b92215be7d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278069767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3278069767
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.114138560
Short name T995
Test name
Test status
Simulation time 103681812 ps
CPU time 1.97 seconds
Started May 26 12:40:07 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 216100 kb
Host smart-933beef1-fbf1-4953-ba4a-0d78bbcf7147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114138560 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.114138560
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4262405450
Short name T116
Test name
Test status
Simulation time 91157266 ps
CPU time 2.24 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:08 PM PDT 24
Peak memory 206832 kb
Host smart-2264d725-aab6-49ee-952f-6350d106c756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262405450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4262405450
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2030143537
Short name T1051
Test name
Test status
Simulation time 51239294 ps
CPU time 0.72 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 203568 kb
Host smart-613f22aa-068f-4207-9ece-81fab91788a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030143537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2030143537
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.477511780
Short name T966
Test name
Test status
Simulation time 649674725 ps
CPU time 3.07 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 215088 kb
Host smart-4646727b-1b69-413b-a2f3-33d0103fef07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477511780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.477511780
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1052249624
Short name T103
Test name
Test status
Simulation time 104750261 ps
CPU time 1.9 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:07 PM PDT 24
Peak memory 215384 kb
Host smart-65bce376-18b0-41e7-97c6-82879836c238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052249624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1052249624
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1247578609
Short name T63
Test name
Test status
Simulation time 301907020 ps
CPU time 8.38 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:13 PM PDT 24
Peak memory 215132 kb
Host smart-4fd4b415-9021-4ff0-b11b-07699a647104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247578609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1247578609
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.608456043
Short name T1058
Test name
Test status
Simulation time 223391481 ps
CPU time 3.95 seconds
Started May 26 12:40:08 PM PDT 24
Finished May 26 12:40:12 PM PDT 24
Peak memory 217848 kb
Host smart-66830bbc-d32d-434c-925a-66f06e420d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608456043 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.608456043
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2711101832
Short name T114
Test name
Test status
Simulation time 74137779 ps
CPU time 2.09 seconds
Started May 26 12:40:03 PM PDT 24
Finished May 26 12:40:06 PM PDT 24
Peak memory 215316 kb
Host smart-3bb2610e-cafb-4e15-aa98-6c1b7d9b4706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711101832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2711101832
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3109062257
Short name T978
Test name
Test status
Simulation time 14589046 ps
CPU time 0.72 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:08 PM PDT 24
Peak memory 203784 kb
Host smart-a1b6c117-14e2-44c4-9ee8-63a2d9a417e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109062257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3109062257
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.915414575
Short name T138
Test name
Test status
Simulation time 283683832 ps
CPU time 2.99 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:09 PM PDT 24
Peak memory 215168 kb
Host smart-861739bf-a224-4594-90d7-d54b2723f4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915414575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.915414575
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2547597990
Short name T102
Test name
Test status
Simulation time 144167210 ps
CPU time 4.44 seconds
Started May 26 12:40:07 PM PDT 24
Finished May 26 12:40:12 PM PDT 24
Peak memory 215388 kb
Host smart-e47cebc7-2ce4-4a9f-93e3-c502f13150b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547597990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2547597990
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3495637650
Short name T108
Test name
Test status
Simulation time 235095762 ps
CPU time 15.2 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:20 PM PDT 24
Peak memory 214980 kb
Host smart-48c18121-dd4a-4bcc-8bb2-45d94d5d2b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495637650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3495637650
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1871929542
Short name T1006
Test name
Test status
Simulation time 306174035 ps
CPU time 2.72 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:08 PM PDT 24
Peak memory 216424 kb
Host smart-25b844f5-e1e7-463d-8c56-09e71c3957e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871929542 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1871929542
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.680022895
Short name T113
Test name
Test status
Simulation time 70994130 ps
CPU time 1.38 seconds
Started May 26 12:40:03 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 206836 kb
Host smart-97b1a640-3b19-4bb4-a4de-31e8e93a4cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680022895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.680022895
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3204431895
Short name T1013
Test name
Test status
Simulation time 36846350 ps
CPU time 0.76 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:07 PM PDT 24
Peak memory 203564 kb
Host smart-fca2356f-258c-4435-b554-c65c1dfce814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204431895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3204431895
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1000005502
Short name T147
Test name
Test status
Simulation time 264313447 ps
CPU time 1.89 seconds
Started May 26 12:40:07 PM PDT 24
Finished May 26 12:40:09 PM PDT 24
Peak memory 215100 kb
Host smart-50263ef1-7545-4976-8c9e-14e030a19a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000005502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1000005502
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3156631699
Short name T1037
Test name
Test status
Simulation time 790493888 ps
CPU time 5.78 seconds
Started May 26 12:40:08 PM PDT 24
Finished May 26 12:40:15 PM PDT 24
Peak memory 215264 kb
Host smart-7ac85def-3da0-404b-b0f4-1fdeff7de457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156631699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3156631699
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3816414509
Short name T274
Test name
Test status
Simulation time 108380208 ps
CPU time 7.16 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:12 PM PDT 24
Peak memory 215284 kb
Host smart-de3cae23-9c3e-4465-9d19-c89fc14088ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816414509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3816414509
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4099925815
Short name T996
Test name
Test status
Simulation time 1729628988 ps
CPU time 3.95 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 218060 kb
Host smart-54bd0200-d542-459a-9757-57a71456cb97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099925815 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4099925815
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.137366304
Short name T1041
Test name
Test status
Simulation time 29338046 ps
CPU time 2.16 seconds
Started May 26 12:40:07 PM PDT 24
Finished May 26 12:40:09 PM PDT 24
Peak memory 206848 kb
Host smart-90a1eafe-649d-4acb-b27a-f85a966007bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137366304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.137366304
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1490542857
Short name T969
Test name
Test status
Simulation time 29602578 ps
CPU time 0.76 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 203492 kb
Host smart-b58ccc3a-a764-4044-85c1-66a93e5bdf9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490542857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1490542857
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2173301081
Short name T989
Test name
Test status
Simulation time 216381169 ps
CPU time 4.36 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:11 PM PDT 24
Peak memory 215012 kb
Host smart-be5b51d2-67ca-425f-a710-24b208fb6c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173301081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2173301081
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1499418320
Short name T1060
Test name
Test status
Simulation time 261187603 ps
CPU time 2.16 seconds
Started May 26 12:40:07 PM PDT 24
Finished May 26 12:40:09 PM PDT 24
Peak memory 216260 kb
Host smart-08c66940-fbd9-4ca3-b9fd-25ef38772506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499418320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1499418320
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3333036329
Short name T271
Test name
Test status
Simulation time 833338424 ps
CPU time 21.67 seconds
Started May 26 12:40:06 PM PDT 24
Finished May 26 12:40:28 PM PDT 24
Peak memory 215024 kb
Host smart-85499261-8a40-4254-ad10-4e134934af79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333036329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3333036329
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1411382413
Short name T145
Test name
Test status
Simulation time 4284108227 ps
CPU time 17 seconds
Started May 26 12:39:01 PM PDT 24
Finished May 26 12:39:19 PM PDT 24
Peak memory 206876 kb
Host smart-217108ae-d3c4-4ed1-97b9-f12e9e55b9c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411382413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1411382413
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3954097622
Short name T119
Test name
Test status
Simulation time 7522197340 ps
CPU time 27.32 seconds
Started May 26 12:39:02 PM PDT 24
Finished May 26 12:39:29 PM PDT 24
Peak memory 215080 kb
Host smart-2d1ad90d-3307-4e5d-9f5b-c6cc6f5b6e89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954097622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3954097622
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.982719375
Short name T1072
Test name
Test status
Simulation time 250641648 ps
CPU time 1.18 seconds
Started May 26 12:39:02 PM PDT 24
Finished May 26 12:39:04 PM PDT 24
Peak memory 206772 kb
Host smart-770500db-abc3-42df-9043-1765ae00e1c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982719375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.982719375
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2053536491
Short name T1062
Test name
Test status
Simulation time 392393415 ps
CPU time 3.64 seconds
Started May 26 12:39:14 PM PDT 24
Finished May 26 12:39:18 PM PDT 24
Peak memory 216728 kb
Host smart-73019c87-69be-400b-911f-e162272e466a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053536491 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2053536491
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.142774035
Short name T1043
Test name
Test status
Simulation time 221341322 ps
CPU time 2.13 seconds
Started May 26 12:39:02 PM PDT 24
Finished May 26 12:39:04 PM PDT 24
Peak memory 215044 kb
Host smart-8072a1d2-a23f-4ba8-aeaa-a9e6095fb8ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142774035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.142774035
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4186536924
Short name T993
Test name
Test status
Simulation time 51363495 ps
CPU time 0.75 seconds
Started May 26 12:38:53 PM PDT 24
Finished May 26 12:38:54 PM PDT 24
Peak memory 203880 kb
Host smart-56ac53b0-9dfa-45de-af29-e8b30405c91b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186536924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
186536924
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2317453529
Short name T1067
Test name
Test status
Simulation time 26788486 ps
CPU time 2.2 seconds
Started May 26 12:38:52 PM PDT 24
Finished May 26 12:38:55 PM PDT 24
Peak memory 215248 kb
Host smart-dfe983ee-b8ba-4367-abae-21dca1d684a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317453529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2317453529
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1186313655
Short name T976
Test name
Test status
Simulation time 44492577 ps
CPU time 0.67 seconds
Started May 26 12:38:53 PM PDT 24
Finished May 26 12:38:54 PM PDT 24
Peak memory 203692 kb
Host smart-1652a4c0-6c09-4c28-813f-7b6a0715ecb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186313655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1186313655
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3408234184
Short name T992
Test name
Test status
Simulation time 224939150 ps
CPU time 3.91 seconds
Started May 26 12:39:02 PM PDT 24
Finished May 26 12:39:06 PM PDT 24
Peak memory 215060 kb
Host smart-9041270c-17e4-4fd9-a61f-f38e558d8f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408234184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3408234184
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3173604808
Short name T104
Test name
Test status
Simulation time 197326439 ps
CPU time 5.23 seconds
Started May 26 12:38:52 PM PDT 24
Finished May 26 12:38:58 PM PDT 24
Peak memory 216316 kb
Host smart-526e3af3-d1e7-4380-b7cf-ffb49535f90e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173604808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
173604808
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.531036954
Short name T1026
Test name
Test status
Simulation time 105466573 ps
CPU time 7.12 seconds
Started May 26 12:38:51 PM PDT 24
Finished May 26 12:38:59 PM PDT 24
Peak memory 215400 kb
Host smart-39024f38-3b6a-45fb-88c5-bce1de06fa5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531036954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.531036954
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1759490206
Short name T971
Test name
Test status
Simulation time 123202535 ps
CPU time 0.76 seconds
Started May 26 12:40:05 PM PDT 24
Finished May 26 12:40:07 PM PDT 24
Peak memory 203792 kb
Host smart-338180bf-26c1-4de4-b663-35bd12672fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759490206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1759490206
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.427158608
Short name T985
Test name
Test status
Simulation time 15362036 ps
CPU time 0.73 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 203872 kb
Host smart-5a9eaf15-3ed5-420a-b12d-adf1f02ef696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427158608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.427158608
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2466445841
Short name T1064
Test name
Test status
Simulation time 32234463 ps
CPU time 0.74 seconds
Started May 26 12:40:09 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 203808 kb
Host smart-a521ef79-6bab-4d69-97ea-004fcb06372b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466445841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2466445841
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2295251792
Short name T1038
Test name
Test status
Simulation time 34162150 ps
CPU time 0.72 seconds
Started May 26 12:40:09 PM PDT 24
Finished May 26 12:40:10 PM PDT 24
Peak memory 203496 kb
Host smart-975b8873-8e72-45dd-a390-b37883cdeeae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295251792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2295251792
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.881920422
Short name T984
Test name
Test status
Simulation time 41655560 ps
CPU time 0.72 seconds
Started May 26 12:40:04 PM PDT 24
Finished May 26 12:40:05 PM PDT 24
Peak memory 203800 kb
Host smart-291511c7-839b-4ec0-a285-20a06ed4b758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881920422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.881920422
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3152398567
Short name T1009
Test name
Test status
Simulation time 64233908 ps
CPU time 0.7 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203764 kb
Host smart-1dd59fae-a930-4b55-b3e8-339e2f21f1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152398567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3152398567
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1671349674
Short name T1011
Test name
Test status
Simulation time 22452055 ps
CPU time 0.73 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:17 PM PDT 24
Peak memory 203492 kb
Host smart-19ba5bdc-335f-43b4-a933-2cd90ebd9e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671349674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1671349674
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.951311875
Short name T1065
Test name
Test status
Simulation time 14916076 ps
CPU time 0.74 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:17 PM PDT 24
Peak memory 203796 kb
Host smart-61c180cf-3f37-4e1d-bd13-24024e175eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951311875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.951311875
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.221514334
Short name T956
Test name
Test status
Simulation time 11653749 ps
CPU time 0.72 seconds
Started May 26 12:40:13 PM PDT 24
Finished May 26 12:40:14 PM PDT 24
Peak memory 203472 kb
Host smart-7c48bcba-6bd2-4a15-8e22-34ceb33a7394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221514334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.221514334
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3213488265
Short name T1046
Test name
Test status
Simulation time 13375198 ps
CPU time 0.81 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203372 kb
Host smart-d0c6f72d-d479-4665-a93f-f1a4940d7dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213488265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3213488265
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3087641457
Short name T115
Test name
Test status
Simulation time 111159167 ps
CPU time 7.96 seconds
Started May 26 12:39:20 PM PDT 24
Finished May 26 12:39:29 PM PDT 24
Peak memory 206844 kb
Host smart-46c1e30e-2889-40f6-94fd-dd4739a7eff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087641457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3087641457
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1437372028
Short name T1028
Test name
Test status
Simulation time 1887001681 ps
CPU time 29.14 seconds
Started May 26 12:39:10 PM PDT 24
Finished May 26 12:39:39 PM PDT 24
Peak memory 214996 kb
Host smart-57fa0e8d-36ef-41a6-8b45-fc43bb5e7c15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437372028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1437372028
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2494499142
Short name T81
Test name
Test status
Simulation time 35723070 ps
CPU time 1.21 seconds
Started May 26 12:39:10 PM PDT 24
Finished May 26 12:39:12 PM PDT 24
Peak memory 206860 kb
Host smart-7d15813c-e6c6-4584-8866-83974e28f2c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494499142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2494499142
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1223096342
Short name T987
Test name
Test status
Simulation time 1047325262 ps
CPU time 2.58 seconds
Started May 26 12:39:09 PM PDT 24
Finished May 26 12:39:12 PM PDT 24
Peak memory 215372 kb
Host smart-055d0521-8461-4e65-a7b0-243493e21057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223096342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
223096342
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4063288664
Short name T1074
Test name
Test status
Simulation time 50949856 ps
CPU time 0.72 seconds
Started May 26 12:39:10 PM PDT 24
Finished May 26 12:39:11 PM PDT 24
Peak memory 203468 kb
Host smart-6cf243f0-0a9b-4293-b559-e9b2d3fa37d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063288664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
063288664
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.706601063
Short name T1033
Test name
Test status
Simulation time 258183536 ps
CPU time 2.06 seconds
Started May 26 12:39:10 PM PDT 24
Finished May 26 12:39:13 PM PDT 24
Peak memory 215056 kb
Host smart-32f691bf-04c9-4b8b-8064-1de36d789bae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706601063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.706601063
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2795061964
Short name T1023
Test name
Test status
Simulation time 18613689 ps
CPU time 0.68 seconds
Started May 26 12:39:09 PM PDT 24
Finished May 26 12:39:10 PM PDT 24
Peak memory 203756 kb
Host smart-8ad062a9-0e38-42ae-9696-accc4759b5a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795061964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2795061964
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.858497979
Short name T974
Test name
Test status
Simulation time 186185429 ps
CPU time 2.84 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:21 PM PDT 24
Peak memory 215060 kb
Host smart-57007a5b-4e8e-43ef-85fd-9544ce35d203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858497979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.858497979
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1291837778
Short name T1068
Test name
Test status
Simulation time 14913198 ps
CPU time 0.78 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203476 kb
Host smart-05085116-d30a-428b-85f7-4cc72d7a487d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291837778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1291837778
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.891805838
Short name T1057
Test name
Test status
Simulation time 20169814 ps
CPU time 0.7 seconds
Started May 26 12:40:13 PM PDT 24
Finished May 26 12:40:14 PM PDT 24
Peak memory 203436 kb
Host smart-d98c88d7-4190-4016-b01c-b4dbd72c9a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891805838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.891805838
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2965794482
Short name T990
Test name
Test status
Simulation time 12234128 ps
CPU time 0.72 seconds
Started May 26 12:40:13 PM PDT 24
Finished May 26 12:40:15 PM PDT 24
Peak memory 203484 kb
Host smart-d579e796-b226-463e-9a6e-3902c074d962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965794482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2965794482
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2848468018
Short name T1040
Test name
Test status
Simulation time 13084219 ps
CPU time 0.72 seconds
Started May 26 12:40:12 PM PDT 24
Finished May 26 12:40:14 PM PDT 24
Peak memory 203452 kb
Host smart-e66616c3-3761-471d-92e9-79208906f59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848468018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2848468018
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1665952926
Short name T967
Test name
Test status
Simulation time 84991868 ps
CPU time 0.69 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203456 kb
Host smart-c9bb73fa-55a6-4f1a-acde-b884cc9ac6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665952926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1665952926
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.797182707
Short name T1002
Test name
Test status
Simulation time 49311714 ps
CPU time 0.72 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203756 kb
Host smart-57d1997f-d649-4b01-bbd1-aeaffe15e86e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797182707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.797182707
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2095593581
Short name T1022
Test name
Test status
Simulation time 48360028 ps
CPU time 0.7 seconds
Started May 26 12:40:13 PM PDT 24
Finished May 26 12:40:14 PM PDT 24
Peak memory 203776 kb
Host smart-f5cd7ca8-8ef5-4a39-b99c-ead475aa1cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095593581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2095593581
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2918828449
Short name T1061
Test name
Test status
Simulation time 156576351 ps
CPU time 0.73 seconds
Started May 26 12:40:16 PM PDT 24
Finished May 26 12:40:18 PM PDT 24
Peak memory 203476 kb
Host smart-e08692a0-6111-4b4e-bf27-64917138a423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918828449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2918828449
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.516351307
Short name T983
Test name
Test status
Simulation time 15296456 ps
CPU time 0.73 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203476 kb
Host smart-628d666d-a698-4b79-bac7-b107d4632fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516351307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.516351307
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3535922544
Short name T960
Test name
Test status
Simulation time 112821116 ps
CPU time 0.76 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:15 PM PDT 24
Peak memory 203520 kb
Host smart-e789d214-d433-43ad-987f-f6c429db5a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535922544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3535922544
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3574829568
Short name T1078
Test name
Test status
Simulation time 7649052094 ps
CPU time 25.89 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:45 PM PDT 24
Peak memory 215444 kb
Host smart-d4dfa69b-f50c-4acb-82b3-150023adc722
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574829568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3574829568
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2644955551
Short name T1039
Test name
Test status
Simulation time 502343784 ps
CPU time 13.42 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:31 PM PDT 24
Peak memory 215356 kb
Host smart-27cf9de0-14e9-4e15-84ea-4a6efff0c32e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644955551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2644955551
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3778900905
Short name T1059
Test name
Test status
Simulation time 32199001 ps
CPU time 1.23 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:19 PM PDT 24
Peak memory 216140 kb
Host smart-8350b080-9ab6-4ab1-8b3f-3620c71a8a36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778900905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3778900905
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4044595666
Short name T1069
Test name
Test status
Simulation time 606124086 ps
CPU time 3.48 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:23 PM PDT 24
Peak memory 215352 kb
Host smart-fa7af7ea-a422-46ae-a3b4-a823f2f092bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044595666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4044595666
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1533367112
Short name T1029
Test name
Test status
Simulation time 123439113 ps
CPU time 1.8 seconds
Started May 26 12:39:18 PM PDT 24
Finished May 26 12:39:21 PM PDT 24
Peak memory 215072 kb
Host smart-587384bb-d698-4393-b038-23861cb45c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533367112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
533367112
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2302854312
Short name T957
Test name
Test status
Simulation time 18452395 ps
CPU time 0.72 seconds
Started May 26 12:39:20 PM PDT 24
Finished May 26 12:39:21 PM PDT 24
Peak memory 203444 kb
Host smart-5fb015fa-cfe4-479d-9f1f-8fe9e4d5a898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302854312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
302854312
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4125444262
Short name T117
Test name
Test status
Simulation time 24796643 ps
CPU time 1.77 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:21 PM PDT 24
Peak memory 215444 kb
Host smart-24fc8f48-6f31-494d-aec0-6204a0f801ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125444262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4125444262
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3864115215
Short name T977
Test name
Test status
Simulation time 21871187 ps
CPU time 0.67 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:20 PM PDT 24
Peak memory 203392 kb
Host smart-378b4fed-dc7c-460e-9424-4eeabfc4316b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864115215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3864115215
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4072282583
Short name T1036
Test name
Test status
Simulation time 46047339 ps
CPU time 2.74 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:20 PM PDT 24
Peak memory 215052 kb
Host smart-78ecf721-fefd-4f4b-9170-c8c6aee7b50e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072282583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4072282583
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3320097294
Short name T96
Test name
Test status
Simulation time 204016947 ps
CPU time 3.91 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:22 PM PDT 24
Peak memory 216236 kb
Host smart-cb0124d2-2999-4f63-8eb6-618f88a7b221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320097294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
320097294
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1174503858
Short name T94
Test name
Test status
Simulation time 421511758 ps
CPU time 7.96 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:27 PM PDT 24
Peak memory 216344 kb
Host smart-62b681a2-f295-4d06-811b-c1acb85e5257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174503858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1174503858
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1863153931
Short name T1073
Test name
Test status
Simulation time 13528374 ps
CPU time 0.72 seconds
Started May 26 12:40:12 PM PDT 24
Finished May 26 12:40:13 PM PDT 24
Peak memory 203500 kb
Host smart-de4c46b7-6804-4603-92a5-34f5408aaea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863153931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1863153931
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3545195319
Short name T1014
Test name
Test status
Simulation time 16156191 ps
CPU time 0.74 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203796 kb
Host smart-6c854669-3921-478f-923f-4f2aa51bc40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545195319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3545195319
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4031945197
Short name T1066
Test name
Test status
Simulation time 13797562 ps
CPU time 0.75 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:15 PM PDT 24
Peak memory 203504 kb
Host smart-f5433036-440b-4b8e-b187-caaf732e5f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031945197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4031945197
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3892444127
Short name T991
Test name
Test status
Simulation time 49035762 ps
CPU time 0.7 seconds
Started May 26 12:40:17 PM PDT 24
Finished May 26 12:40:18 PM PDT 24
Peak memory 203492 kb
Host smart-55eafa9d-2c86-4714-82e0-09ab9d7e522c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892444127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3892444127
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3611934052
Short name T1063
Test name
Test status
Simulation time 25498427 ps
CPU time 0.8 seconds
Started May 26 12:40:15 PM PDT 24
Finished May 26 12:40:17 PM PDT 24
Peak memory 203488 kb
Host smart-f611dfab-4669-4f49-9329-a88be321ee78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611934052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3611934052
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3592457974
Short name T1001
Test name
Test status
Simulation time 22791547 ps
CPU time 0.77 seconds
Started May 26 12:40:11 PM PDT 24
Finished May 26 12:40:13 PM PDT 24
Peak memory 203416 kb
Host smart-8d284c95-449e-4fcb-9f21-4aa72dfc5296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592457974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3592457974
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4010963349
Short name T962
Test name
Test status
Simulation time 20220611 ps
CPU time 0.76 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:16 PM PDT 24
Peak memory 203464 kb
Host smart-f493133b-b85b-4d01-b1c5-6c6eca5237ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010963349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4010963349
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.850686923
Short name T963
Test name
Test status
Simulation time 14605109 ps
CPU time 0.79 seconds
Started May 26 12:40:14 PM PDT 24
Finished May 26 12:40:15 PM PDT 24
Peak memory 203424 kb
Host smart-a5da00a5-73d1-43a9-a09a-f5ca81763192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850686923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.850686923
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2367747623
Short name T1056
Test name
Test status
Simulation time 31508063 ps
CPU time 0.7 seconds
Started May 26 12:40:16 PM PDT 24
Finished May 26 12:40:17 PM PDT 24
Peak memory 203484 kb
Host smart-d5b156c5-4538-4ab0-a665-aad1decb806f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367747623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2367747623
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1729550210
Short name T959
Test name
Test status
Simulation time 11890892 ps
CPU time 0.71 seconds
Started May 26 12:40:23 PM PDT 24
Finished May 26 12:40:24 PM PDT 24
Peak memory 203492 kb
Host smart-c2f57036-f17a-46f3-9bdd-e3f6e98d072c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729550210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1729550210
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2719965851
Short name T1004
Test name
Test status
Simulation time 417461275 ps
CPU time 4.1 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:33 PM PDT 24
Peak memory 217208 kb
Host smart-fc2c4947-ceeb-44bd-9ca5-bdb41812f7b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719965851 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2719965851
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1386824677
Short name T112
Test name
Test status
Simulation time 204323800 ps
CPU time 1.63 seconds
Started May 26 12:39:17 PM PDT 24
Finished May 26 12:39:19 PM PDT 24
Peak memory 206964 kb
Host smart-73148715-4f28-4e58-ac42-4c564f463f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386824677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
386824677
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1969923302
Short name T1032
Test name
Test status
Simulation time 23153023 ps
CPU time 0.72 seconds
Started May 26 12:39:18 PM PDT 24
Finished May 26 12:39:19 PM PDT 24
Peak memory 203476 kb
Host smart-9f33a82f-cc72-4641-a7c6-e88e64526b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969923302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
969923302
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.923508240
Short name T1047
Test name
Test status
Simulation time 290639205 ps
CPU time 4.13 seconds
Started May 26 12:39:18 PM PDT 24
Finished May 26 12:39:23 PM PDT 24
Peak memory 215024 kb
Host smart-083a9b61-d25d-40a4-b397-60abdb7ea5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923508240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.923508240
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.726365284
Short name T1007
Test name
Test status
Simulation time 524501692 ps
CPU time 3.85 seconds
Started May 26 12:39:19 PM PDT 24
Finished May 26 12:39:23 PM PDT 24
Peak memory 215252 kb
Host smart-29edfc7d-bc05-4d43-836d-ac115717c726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726365284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.726365284
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3183604338
Short name T106
Test name
Test status
Simulation time 453937531 ps
CPU time 14.79 seconds
Started May 26 12:39:20 PM PDT 24
Finished May 26 12:39:35 PM PDT 24
Peak memory 215488 kb
Host smart-407014de-1fa3-4797-8175-830e0cd18c40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183604338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3183604338
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1847265867
Short name T107
Test name
Test status
Simulation time 57712631 ps
CPU time 1.81 seconds
Started May 26 12:39:27 PM PDT 24
Finished May 26 12:39:29 PM PDT 24
Peak memory 215116 kb
Host smart-f640e8b5-6be3-4126-abd9-3812303b1f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847265867 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1847265867
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1745997155
Short name T1010
Test name
Test status
Simulation time 28307779 ps
CPU time 1.23 seconds
Started May 26 12:39:32 PM PDT 24
Finished May 26 12:39:33 PM PDT 24
Peak memory 215012 kb
Host smart-6f1ec108-1c3e-42a1-8c78-66a5e3c28ac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745997155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
745997155
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1491299515
Short name T961
Test name
Test status
Simulation time 14539790 ps
CPU time 0.78 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:30 PM PDT 24
Peak memory 203792 kb
Host smart-bb8117a9-3ce7-4aad-96ce-723e4ba543a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491299515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
491299515
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1617671618
Short name T1017
Test name
Test status
Simulation time 571335146 ps
CPU time 3.95 seconds
Started May 26 12:39:25 PM PDT 24
Finished May 26 12:39:30 PM PDT 24
Peak memory 215064 kb
Host smart-11e0a246-b824-4452-8280-730eec51d63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617671618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1617671618
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.763592649
Short name T1071
Test name
Test status
Simulation time 790728783 ps
CPU time 5.1 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:34 PM PDT 24
Peak memory 215216 kb
Host smart-5d92a83a-476d-4c76-afb0-a70f0124d208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763592649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.763592649
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.606814186
Short name T93
Test name
Test status
Simulation time 235195552 ps
CPU time 1.54 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:30 PM PDT 24
Peak memory 215112 kb
Host smart-5bc5c279-9b8e-4b15-bcee-61088957b196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606814186 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.606814186
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2313155897
Short name T1080
Test name
Test status
Simulation time 152671758 ps
CPU time 2.08 seconds
Started May 26 12:39:26 PM PDT 24
Finished May 26 12:39:28 PM PDT 24
Peak memory 215156 kb
Host smart-f0d0db2c-ef6a-431c-9a2b-e16d0302152a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313155897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
313155897
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2341450145
Short name T1075
Test name
Test status
Simulation time 61774201 ps
CPU time 0.75 seconds
Started May 26 12:39:31 PM PDT 24
Finished May 26 12:39:32 PM PDT 24
Peak memory 203420 kb
Host smart-6b42a341-8d8b-43a5-a1fb-e86b0486e534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341450145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
341450145
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2583450114
Short name T1077
Test name
Test status
Simulation time 115206308 ps
CPU time 1.83 seconds
Started May 26 12:39:32 PM PDT 24
Finished May 26 12:39:34 PM PDT 24
Peak memory 214964 kb
Host smart-7bae050f-6a09-4ddb-89af-4eba47366042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583450114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2583450114
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3710141330
Short name T1031
Test name
Test status
Simulation time 27899164 ps
CPU time 1.51 seconds
Started May 26 12:39:26 PM PDT 24
Finished May 26 12:39:28 PM PDT 24
Peak memory 215256 kb
Host smart-ed165ab1-393a-460f-9717-5970d75f3e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710141330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
710141330
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1304048464
Short name T270
Test name
Test status
Simulation time 744749335 ps
CPU time 12.92 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:41 PM PDT 24
Peak memory 222384 kb
Host smart-98a3e712-3a78-46e2-ab24-abe404363bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304048464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1304048464
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3912961335
Short name T1024
Test name
Test status
Simulation time 1912563272 ps
CPU time 3.52 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:38 PM PDT 24
Peak memory 217956 kb
Host smart-fb1c354c-6acb-49aa-bf85-46d5b35d7f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912961335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3912961335
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.426155209
Short name T120
Test name
Test status
Simulation time 442401762 ps
CPU time 1.82 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:36 PM PDT 24
Peak memory 206760 kb
Host smart-c1dc406d-d12f-4dee-9713-1ee8d3b8441e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426155209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.426155209
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2476562936
Short name T1021
Test name
Test status
Simulation time 32729038 ps
CPU time 0.7 seconds
Started May 26 12:39:26 PM PDT 24
Finished May 26 12:39:27 PM PDT 24
Peak memory 203564 kb
Host smart-02cadde1-6048-46fb-8dcd-f699ca75342c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476562936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
476562936
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2856705320
Short name T970
Test name
Test status
Simulation time 1512768820 ps
CPU time 4.08 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:38 PM PDT 24
Peak memory 215064 kb
Host smart-83a38910-1245-4199-b9d0-cf8fc4f06edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856705320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2856705320
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.385947729
Short name T269
Test name
Test status
Simulation time 104085191 ps
CPU time 3.34 seconds
Started May 26 12:39:26 PM PDT 24
Finished May 26 12:39:29 PM PDT 24
Peak memory 215248 kb
Host smart-ae4006f9-d06b-4777-8f5a-068dc37dfa94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385947729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.385947729
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.117106644
Short name T1052
Test name
Test status
Simulation time 2436324243 ps
CPU time 7.72 seconds
Started May 26 12:39:28 PM PDT 24
Finished May 26 12:39:37 PM PDT 24
Peak memory 215152 kb
Host smart-900a278f-83cd-4554-86db-ebb200068a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117106644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.117106644
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2322945006
Short name T148
Test name
Test status
Simulation time 152999581 ps
CPU time 3.88 seconds
Started May 26 12:39:34 PM PDT 24
Finished May 26 12:39:38 PM PDT 24
Peak memory 216832 kb
Host smart-bac457c8-a99d-41a5-9b71-cffbec3be0ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322945006 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2322945006
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2363926498
Short name T986
Test name
Test status
Simulation time 91843408 ps
CPU time 2.3 seconds
Started May 26 12:39:37 PM PDT 24
Finished May 26 12:39:40 PM PDT 24
Peak memory 215176 kb
Host smart-877a47bd-6799-4a8d-bc09-e8ff98847767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363926498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
363926498
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3607577853
Short name T1050
Test name
Test status
Simulation time 17901645 ps
CPU time 0.73 seconds
Started May 26 12:39:40 PM PDT 24
Finished May 26 12:39:41 PM PDT 24
Peak memory 203424 kb
Host smart-08f03509-9e16-4bdf-bff2-555c9da6eeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607577853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
607577853
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2969979325
Short name T1070
Test name
Test status
Simulation time 573300378 ps
CPU time 4.33 seconds
Started May 26 12:39:36 PM PDT 24
Finished May 26 12:39:41 PM PDT 24
Peak memory 215160 kb
Host smart-fe745531-566b-4c24-bc0d-34e9f7ad4337
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969979325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2969979325
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3850153431
Short name T988
Test name
Test status
Simulation time 452604951 ps
CPU time 1.48 seconds
Started May 26 12:39:40 PM PDT 24
Finished May 26 12:39:42 PM PDT 24
Peak memory 214716 kb
Host smart-5cc1170a-fc4b-45a3-bfdd-21164ad80a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850153431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
850153431
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2710688264
Short name T1048
Test name
Test status
Simulation time 3188244734 ps
CPU time 16.25 seconds
Started May 26 12:39:33 PM PDT 24
Finished May 26 12:39:50 PM PDT 24
Peak memory 216468 kb
Host smart-ddb93e8e-e220-48de-a270-df842d6a4c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710688264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2710688264
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.329509336
Short name T505
Test name
Test status
Simulation time 20052512 ps
CPU time 0.71 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:51 PM PDT 24
Peak memory 205280 kb
Host smart-5f470057-1947-4f72-bb62-7edccd171259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329509336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.329509336
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3554736339
Short name T527
Test name
Test status
Simulation time 228688139 ps
CPU time 4.34 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:51:55 PM PDT 24
Peak memory 219540 kb
Host smart-877439b5-6a78-4fef-a8e3-b55de3935b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554736339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3554736339
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1345534037
Short name T884
Test name
Test status
Simulation time 62527620 ps
CPU time 0.78 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:43 PM PDT 24
Peak memory 206616 kb
Host smart-f8d68de1-8dd3-4101-ae7c-75e9a49a08a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345534037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1345534037
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1833902601
Short name T429
Test name
Test status
Simulation time 72086444938 ps
CPU time 146.26 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:54:16 PM PDT 24
Peak memory 251700 kb
Host smart-1fd34ccc-974e-45ed-8ba1-cbfc8133cf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833902601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1833902601
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2849953007
Short name T168
Test name
Test status
Simulation time 3324735596 ps
CPU time 68.01 seconds
Started May 26 12:51:52 PM PDT 24
Finished May 26 12:53:00 PM PDT 24
Peak memory 257172 kb
Host smart-0b9128c8-53a9-4b47-9e7f-18f4ed5c64c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849953007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2849953007
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1360520330
Short name T560
Test name
Test status
Simulation time 14196492806 ps
CPU time 114.51 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:53:45 PM PDT 24
Peak memory 265356 kb
Host smart-cb417250-8a84-40fb-ae3d-1d5d76fa58b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360520330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1360520330
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1376152829
Short name T676
Test name
Test status
Simulation time 196390163 ps
CPU time 3.42 seconds
Started May 26 12:51:52 PM PDT 24
Finished May 26 12:51:56 PM PDT 24
Peak memory 232448 kb
Host smart-ea81c5f2-4bdb-4b10-9b63-0b93e93e1e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376152829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1376152829
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.854436228
Short name T190
Test name
Test status
Simulation time 294530386 ps
CPU time 5.27 seconds
Started May 26 12:51:48 PM PDT 24
Finished May 26 12:51:54 PM PDT 24
Peak memory 218356 kb
Host smart-1dcc4dd1-d424-4247-a5a4-06d708b6410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854436228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.854436228
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.769635402
Short name T717
Test name
Test status
Simulation time 36471196313 ps
CPU time 77.9 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:53:09 PM PDT 24
Peak memory 232128 kb
Host smart-c29cf262-3d8e-4552-8792-f87fe1286bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769635402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.769635402
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2069472193
Short name T252
Test name
Test status
Simulation time 7485272348 ps
CPU time 8.56 seconds
Started May 26 12:51:51 PM PDT 24
Finished May 26 12:52:00 PM PDT 24
Peak memory 233540 kb
Host smart-ff26ce89-c696-4c2c-8f19-084ee5cc7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069472193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2069472193
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.419224183
Short name T458
Test name
Test status
Simulation time 215147266 ps
CPU time 4.98 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:54 PM PDT 24
Peak memory 222420 kb
Host smart-8bfa1d6a-149a-47d5-81f6-6e879c7d0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419224183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.419224183
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1865640724
Short name T793
Test name
Test status
Simulation time 1114772658 ps
CPU time 10.04 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:52:01 PM PDT 24
Peak memory 222624 kb
Host smart-88e8bb3b-9386-42a4-bdd3-07634b3dc058
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1865640724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1865640724
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.406700936
Short name T342
Test name
Test status
Simulation time 3898717433 ps
CPU time 25.56 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:52:09 PM PDT 24
Peak memory 216176 kb
Host smart-4b2a023f-2a48-4686-9b8b-d6ef21935cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406700936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.406700936
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.885580046
Short name T345
Test name
Test status
Simulation time 260718886 ps
CPU time 2.81 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:52 PM PDT 24
Peak memory 216144 kb
Host smart-07f7d10f-c8be-400e-a771-0a8f84ab9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885580046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.885580046
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1838555604
Short name T825
Test name
Test status
Simulation time 54163287 ps
CPU time 0.9 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:51 PM PDT 24
Peak memory 205516 kb
Host smart-abcdb2d2-c0b1-4c00-b709-b4d99fb7ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838555604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1838555604
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2065120516
Short name T200
Test name
Test status
Simulation time 1643493166 ps
CPU time 3.69 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:54 PM PDT 24
Peak memory 218624 kb
Host smart-f75b50be-f5fa-45b8-9ca0-89b3dab79cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065120516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2065120516
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.23774727
Short name T377
Test name
Test status
Simulation time 79160341 ps
CPU time 0.68 seconds
Started May 26 12:51:58 PM PDT 24
Finished May 26 12:52:00 PM PDT 24
Peak memory 204628 kb
Host smart-fea6b123-7dd0-4206-9f7f-3a681acfcdc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.23774727
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.292063377
Short name T410
Test name
Test status
Simulation time 1859650493 ps
CPU time 4.3 seconds
Started May 26 12:51:58 PM PDT 24
Finished May 26 12:52:03 PM PDT 24
Peak memory 219472 kb
Host smart-dbbe25ee-61ba-40dc-86f7-0836a97b8aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292063377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.292063377
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4219251864
Short name T899
Test name
Test status
Simulation time 433580859542 ps
CPU time 158.98 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 249008 kb
Host smart-f8922e84-8f70-4349-8600-f5f3fb3bc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219251864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4219251864
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.212214304
Short name T493
Test name
Test status
Simulation time 12454675253 ps
CPU time 47.57 seconds
Started May 26 12:52:02 PM PDT 24
Finished May 26 12:52:50 PM PDT 24
Peak memory 240724 kb
Host smart-ace0d8a6-1d2e-4ff4-adcf-759e0ffd737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212214304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
212214304
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2003269204
Short name T688
Test name
Test status
Simulation time 25050557714 ps
CPU time 44.05 seconds
Started May 26 12:52:02 PM PDT 24
Finished May 26 12:52:46 PM PDT 24
Peak memory 241896 kb
Host smart-a25f3677-9704-4ff2-962a-4021cd1158fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003269204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2003269204
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1148971929
Short name T719
Test name
Test status
Simulation time 250329169 ps
CPU time 4.78 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:52:05 PM PDT 24
Peak memory 218312 kb
Host smart-09108e18-91c8-494a-9a16-f2118c3af253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148971929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1148971929
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3351085976
Short name T449
Test name
Test status
Simulation time 157245328 ps
CPU time 2.59 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:52:05 PM PDT 24
Peak memory 218292 kb
Host smart-121b4a6f-8358-4b4f-9ab5-3c2be61c4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351085976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3351085976
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3564610102
Short name T666
Test name
Test status
Simulation time 247463062 ps
CPU time 5.2 seconds
Started May 26 12:51:51 PM PDT 24
Finished May 26 12:51:57 PM PDT 24
Peak memory 233036 kb
Host smart-1a2906a9-6402-4121-89e5-5e88332ca0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564610102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3564610102
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2542551816
Short name T280
Test name
Test status
Simulation time 17021864584 ps
CPU time 15.04 seconds
Started May 26 12:51:51 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 234132 kb
Host smart-9dbcc357-18cb-430a-be87-efd76eafe159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542551816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2542551816
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2980985391
Short name T882
Test name
Test status
Simulation time 1533208321 ps
CPU time 6.26 seconds
Started May 26 12:52:00 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 218804 kb
Host smart-d567cf8b-e858-47b7-ab4d-b7fc92c83881
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2980985391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2980985391
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1170808076
Short name T65
Test name
Test status
Simulation time 161551413 ps
CPU time 1.13 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:52:03 PM PDT 24
Peak memory 234960 kb
Host smart-468f13a7-b931-4d66-b64a-0a5f6d64ff2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170808076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1170808076
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1998636962
Short name T737
Test name
Test status
Simulation time 724600243 ps
CPU time 1.06 seconds
Started May 26 12:51:57 PM PDT 24
Finished May 26 12:51:59 PM PDT 24
Peak memory 206952 kb
Host smart-ca7b6a0f-fdaa-4e3b-b06e-37d56deaa975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998636962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1998636962
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.553405777
Short name T341
Test name
Test status
Simulation time 1635639002 ps
CPU time 11.35 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:52:02 PM PDT 24
Peak memory 216136 kb
Host smart-2a864b7b-f7ff-4a0c-b2ae-74dfb21c317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553405777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.553405777
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1289100442
Short name T827
Test name
Test status
Simulation time 974287508 ps
CPU time 1.8 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:52 PM PDT 24
Peak memory 207584 kb
Host smart-bf6c6d18-0b50-4f39-860b-508e354ad26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289100442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1289100442
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1562031033
Short name T639
Test name
Test status
Simulation time 46364233 ps
CPU time 1.3 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:51:52 PM PDT 24
Peak memory 216076 kb
Host smart-38deb1db-415d-457e-a498-a0d3dde0e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562031033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1562031033
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2703869706
Short name T801
Test name
Test status
Simulation time 205243575 ps
CPU time 1.08 seconds
Started May 26 12:51:49 PM PDT 24
Finished May 26 12:51:51 PM PDT 24
Peak memory 206564 kb
Host smart-369f18d8-fdde-410b-a9cd-638081e4b6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703869706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2703869706
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1439503590
Short name T735
Test name
Test status
Simulation time 1185723399 ps
CPU time 8.09 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:52:08 PM PDT 24
Peak memory 220832 kb
Host smart-d338fb6f-0ddd-4b0f-8ff9-df19b50f01e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439503590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1439503590
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2078353051
Short name T881
Test name
Test status
Simulation time 15892739 ps
CPU time 0.73 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:04 PM PDT 24
Peak memory 205396 kb
Host smart-514957ee-cd91-4da6-88f1-5801121e0e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078353051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2078353051
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2243538517
Short name T856
Test name
Test status
Simulation time 1316695951 ps
CPU time 3.27 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:07 PM PDT 24
Peak memory 218352 kb
Host smart-80a8d42a-5418-444d-a87e-383141967be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243538517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2243538517
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1371268584
Short name T522
Test name
Test status
Simulation time 12946828 ps
CPU time 0.75 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:52:56 PM PDT 24
Peak memory 205288 kb
Host smart-74a0ef62-0add-4bae-abb9-9d709ab95a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371268584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1371268584
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1850198763
Short name T521
Test name
Test status
Simulation time 2562168467 ps
CPU time 31.1 seconds
Started May 26 12:53:07 PM PDT 24
Finished May 26 12:53:39 PM PDT 24
Peak memory 256656 kb
Host smart-6ff380a7-d7a9-4b7a-906f-0b23d4dcc259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850198763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1850198763
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3430860434
Short name T486
Test name
Test status
Simulation time 16817191392 ps
CPU time 108.44 seconds
Started May 26 12:53:07 PM PDT 24
Finished May 26 12:54:56 PM PDT 24
Peak memory 258048 kb
Host smart-a5001407-4df6-4844-b445-75c6b2438a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430860434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3430860434
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3377528196
Short name T660
Test name
Test status
Simulation time 235107708 ps
CPU time 7.19 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:12 PM PDT 24
Peak memory 248888 kb
Host smart-04a224ce-11d8-4729-9055-46b74ddbdcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377528196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3377528196
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.545191479
Short name T806
Test name
Test status
Simulation time 744154491 ps
CPU time 4.25 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:16 PM PDT 24
Peak memory 219336 kb
Host smart-7c1d36ae-3548-4aa9-b90d-68887de05118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545191479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.545191479
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3251627081
Short name T923
Test name
Test status
Simulation time 38977590 ps
CPU time 2.76 seconds
Started May 26 12:53:05 PM PDT 24
Finished May 26 12:53:09 PM PDT 24
Peak memory 232552 kb
Host smart-0b3ec903-2055-446f-849b-69f83279ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251627081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3251627081
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4132546383
Short name T921
Test name
Test status
Simulation time 3426478611 ps
CPU time 15.33 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:18 PM PDT 24
Peak memory 239388 kb
Host smart-59d08546-520e-4405-b01a-246a04402976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132546383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4132546383
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2143791299
Short name T807
Test name
Test status
Simulation time 5540365068 ps
CPU time 15.81 seconds
Started May 26 12:53:03 PM PDT 24
Finished May 26 12:53:20 PM PDT 24
Peak memory 234016 kb
Host smart-3f3da175-4602-41f8-8bbd-cd823c171bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143791299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2143791299
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3995957265
Short name T695
Test name
Test status
Simulation time 463834955 ps
CPU time 5.24 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:10 PM PDT 24
Peak memory 222808 kb
Host smart-0eadc145-e3dd-404f-a9a3-dce4d3eced8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995957265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3995957265
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3171452549
Short name T150
Test name
Test status
Simulation time 5607138185 ps
CPU time 37.8 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 248992 kb
Host smart-0f0150af-23d5-46c2-bc60-43a953130c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171452549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3171452549
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3790520984
Short name T784
Test name
Test status
Simulation time 2949932365 ps
CPU time 27.27 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:53:23 PM PDT 24
Peak memory 216228 kb
Host smart-631e866e-0fd6-4136-b3d7-36d902fdaab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790520984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3790520984
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2702897350
Short name T908
Test name
Test status
Simulation time 1636631355 ps
CPU time 6.39 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:53:03 PM PDT 24
Peak memory 215996 kb
Host smart-24dc5293-44f5-4ddb-81aa-4fffa5f111d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702897350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2702897350
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3351526274
Short name T360
Test name
Test status
Simulation time 41848329 ps
CPU time 0.85 seconds
Started May 26 12:53:05 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 206344 kb
Host smart-11a4faae-4471-42b1-ba76-457b7432f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351526274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3351526274
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4062701449
Short name T742
Test name
Test status
Simulation time 114955524 ps
CPU time 1.16 seconds
Started May 26 12:52:56 PM PDT 24
Finished May 26 12:52:58 PM PDT 24
Peak memory 206500 kb
Host smart-668d0c26-47c3-44b1-8687-9ac69f5f0e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062701449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4062701449
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.758249432
Short name T175
Test name
Test status
Simulation time 1123621923 ps
CPU time 6.31 seconds
Started May 26 12:53:06 PM PDT 24
Finished May 26 12:53:13 PM PDT 24
Peak memory 234800 kb
Host smart-66761a42-1327-48c3-a8c6-1f23298b4993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758249432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.758249432
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1877620894
Short name T682
Test name
Test status
Simulation time 2884596410 ps
CPU time 9 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:14 PM PDT 24
Peak memory 219932 kb
Host smart-fd992008-572c-412d-84cf-cac5c4b9020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877620894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1877620894
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3541927218
Short name T538
Test name
Test status
Simulation time 14956760 ps
CPU time 0.82 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 205352 kb
Host smart-6d1f459c-e2a8-4e81-9461-870567f0ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541927218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3541927218
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1556819264
Short name T692
Test name
Test status
Simulation time 4542136436 ps
CPU time 63.59 seconds
Started May 26 12:53:03 PM PDT 24
Finished May 26 12:54:07 PM PDT 24
Peak memory 248920 kb
Host smart-05ae8fe0-e77d-4199-b3e4-0abbb4ceec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556819264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1556819264
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3477984079
Short name T502
Test name
Test status
Simulation time 8239992039 ps
CPU time 50.64 seconds
Started May 26 12:53:07 PM PDT 24
Finished May 26 12:53:58 PM PDT 24
Peak memory 249856 kb
Host smart-bbc5301e-fccd-45e0-8590-4aa3d481720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477984079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3477984079
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1056448570
Short name T764
Test name
Test status
Simulation time 1180100063 ps
CPU time 7.21 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:12 PM PDT 24
Peak memory 219532 kb
Host smart-c0b7f8b9-ab16-4dee-91d2-4ceb90ea40c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056448570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1056448570
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1861745254
Short name T109
Test name
Test status
Simulation time 1407629822 ps
CPU time 20.86 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 235560 kb
Host smart-20ac1b38-7e12-4ab0-a1cb-3838b70c905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861745254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1861745254
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1967304774
Short name T188
Test name
Test status
Simulation time 56396638 ps
CPU time 2.87 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:08 PM PDT 24
Peak memory 232496 kb
Host smart-114807e8-fc13-41cf-bddc-4c2ab5a459b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967304774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1967304774
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1152614358
Short name T656
Test name
Test status
Simulation time 6060463640 ps
CPU time 19.03 seconds
Started May 26 12:53:05 PM PDT 24
Finished May 26 12:53:25 PM PDT 24
Peak memory 219736 kb
Host smart-07998afe-0959-4608-8cef-34f966dc1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152614358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1152614358
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2044872480
Short name T247
Test name
Test status
Simulation time 9977823820 ps
CPU time 141.41 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 265844 kb
Host smart-3fa94724-4736-4407-a760-f6a1369adeec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044872480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2044872480
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1607798619
Short name T381
Test name
Test status
Simulation time 13487455066 ps
CPU time 19.77 seconds
Started May 26 12:53:03 PM PDT 24
Finished May 26 12:53:23 PM PDT 24
Peak memory 216352 kb
Host smart-4971f37b-d06d-4bec-b39e-df9f00e82dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607798619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1607798619
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1179267306
Short name T490
Test name
Test status
Simulation time 1086659747 ps
CPU time 3.66 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:07 PM PDT 24
Peak memory 215996 kb
Host smart-17b01dbe-6a99-4e33-8913-e529eefe290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179267306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1179267306
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2855420509
Short name T436
Test name
Test status
Simulation time 763968349 ps
CPU time 3.2 seconds
Started May 26 12:53:02 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 216116 kb
Host smart-2b92c543-a8a3-48dc-8ecb-70a0653a0b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855420509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2855420509
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4010209161
Short name T675
Test name
Test status
Simulation time 16940922 ps
CPU time 0.75 seconds
Started May 26 12:53:03 PM PDT 24
Finished May 26 12:53:05 PM PDT 24
Peak memory 205528 kb
Host smart-9dffac3d-512f-47bd-b7be-f731a9f8b22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010209161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4010209161
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4025300954
Short name T438
Test name
Test status
Simulation time 34762619493 ps
CPU time 24.59 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:37 PM PDT 24
Peak memory 228380 kb
Host smart-7e75ea09-d88c-4597-a887-b024cf41e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025300954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4025300954
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1050974005
Short name T607
Test name
Test status
Simulation time 39006775 ps
CPU time 0.73 seconds
Started May 26 12:53:14 PM PDT 24
Finished May 26 12:53:15 PM PDT 24
Peak memory 205284 kb
Host smart-1c33ceba-7f81-4c71-bfdd-1a1d581abb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050974005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1050974005
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.938511974
Short name T707
Test name
Test status
Simulation time 4407904324 ps
CPU time 11.45 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:53:24 PM PDT 24
Peak memory 219452 kb
Host smart-28289089-c7a4-4843-b548-da548946bbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938511974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.938511974
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2992029398
Short name T604
Test name
Test status
Simulation time 37501459 ps
CPU time 0.81 seconds
Started May 26 12:53:04 PM PDT 24
Finished May 26 12:53:05 PM PDT 24
Peak memory 206376 kb
Host smart-20ab7365-2120-403c-bbce-e238f2f50f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992029398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2992029398
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2484469619
Short name T474
Test name
Test status
Simulation time 24359800181 ps
CPU time 82.33 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:54:36 PM PDT 24
Peak memory 224336 kb
Host smart-8da1023e-2e55-4698-a102-4f62d6169ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484469619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2484469619
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.207659046
Short name T249
Test name
Test status
Simulation time 21788646981 ps
CPU time 117.43 seconds
Started May 26 12:53:13 PM PDT 24
Finished May 26 12:55:11 PM PDT 24
Peak memory 255684 kb
Host smart-8995ecb9-5537-4db8-825c-795947a14a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207659046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.207659046
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.663750371
Short name T614
Test name
Test status
Simulation time 78535962263 ps
CPU time 362.07 seconds
Started May 26 12:53:14 PM PDT 24
Finished May 26 12:59:17 PM PDT 24
Peak memory 249040 kb
Host smart-a77e936c-1a0e-4e2a-af7e-363fc38b7679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663750371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.663750371
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3891155429
Short name T358
Test name
Test status
Simulation time 15945281178 ps
CPU time 76.55 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:54:29 PM PDT 24
Peak memory 233608 kb
Host smart-3e6b43bc-61a2-4117-a972-93d2bd10d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891155429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3891155429
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.523195798
Short name T576
Test name
Test status
Simulation time 225944182 ps
CPU time 3.17 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:53:16 PM PDT 24
Peak memory 218172 kb
Host smart-eeace30f-867b-4551-8db2-5b813e02615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523195798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.523195798
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.617966568
Short name T561
Test name
Test status
Simulation time 14795932121 ps
CPU time 48.04 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:54:00 PM PDT 24
Peak memory 219592 kb
Host smart-79822baa-b784-47a3-a3f4-d1770b48d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617966568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.617966568
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2979963558
Short name T301
Test name
Test status
Simulation time 11141039054 ps
CPU time 12.94 seconds
Started May 26 12:53:14 PM PDT 24
Finished May 26 12:53:27 PM PDT 24
Peak memory 228296 kb
Host smart-c6cbdf5a-95c0-421a-8065-0d1d0554afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979963558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2979963558
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.855871857
Short name T127
Test name
Test status
Simulation time 2416792031 ps
CPU time 7.16 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:19 PM PDT 24
Peak memory 233056 kb
Host smart-4fc48f67-55c6-4afa-a04a-20d91df6ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855871857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.855871857
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3245075820
Short name T767
Test name
Test status
Simulation time 732967923 ps
CPU time 8.36 seconds
Started May 26 12:53:15 PM PDT 24
Finished May 26 12:53:24 PM PDT 24
Peak memory 218624 kb
Host smart-86dc3aa8-88e8-42bb-a7af-0a092bb1eb2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3245075820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3245075820
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1854407004
Short name T926
Test name
Test status
Simulation time 7466030412 ps
CPU time 66.73 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:54:19 PM PDT 24
Peak memory 224492 kb
Host smart-574b6a1c-86b9-4b23-af7a-290b671fe307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854407004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1854407004
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2589263277
Short name T693
Test name
Test status
Simulation time 7660729524 ps
CPU time 39.48 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:51 PM PDT 24
Peak memory 216292 kb
Host smart-b7a294b0-f2a4-46f5-942d-ccd0db9dec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589263277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2589263277
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3518963160
Short name T774
Test name
Test status
Simulation time 336397461 ps
CPU time 1.94 seconds
Started May 26 12:53:05 PM PDT 24
Finished May 26 12:53:08 PM PDT 24
Peak memory 207484 kb
Host smart-1e4315d2-79c7-47f1-ba5e-f8db2df6f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518963160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3518963160
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2535321174
Short name T51
Test name
Test status
Simulation time 28608329 ps
CPU time 1.1 seconds
Started May 26 12:53:15 PM PDT 24
Finished May 26 12:53:17 PM PDT 24
Peak memory 207788 kb
Host smart-48d18108-8454-4b0c-bb0d-7f90b69ca432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535321174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2535321174
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3264771472
Short name T640
Test name
Test status
Simulation time 74572000 ps
CPU time 0.76 seconds
Started May 26 12:53:05 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 205552 kb
Host smart-63c2d317-b3a8-451b-978d-ff65632f1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264771472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3264771472
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2384274879
Short name T596
Test name
Test status
Simulation time 2266747237 ps
CPU time 15.54 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:53:28 PM PDT 24
Peak memory 237748 kb
Host smart-aa64a193-0046-4d37-ae17-750a77a07468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384274879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2384274879
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1176692030
Short name T650
Test name
Test status
Simulation time 20202295 ps
CPU time 0.73 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:53:24 PM PDT 24
Peak memory 205296 kb
Host smart-3c99b405-a829-4932-8b05-a13cd2a3383f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176692030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1176692030
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1942233202
Short name T313
Test name
Test status
Simulation time 365801384 ps
CPU time 3.45 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:53:26 PM PDT 24
Peak memory 218532 kb
Host smart-db69f8e8-421c-4861-acf9-9827346166e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942233202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1942233202
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3126412845
Short name T5
Test name
Test status
Simulation time 28685003 ps
CPU time 0.79 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:53:14 PM PDT 24
Peak memory 206324 kb
Host smart-d276572e-a184-45c8-8bd2-bb0fb7292df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126412845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3126412845
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1268785999
Short name T751
Test name
Test status
Simulation time 24035577921 ps
CPU time 84.86 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:54:48 PM PDT 24
Peak memory 239396 kb
Host smart-348f7edf-4dd7-4bd3-8e66-21ab454a35d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268785999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1268785999
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1518775646
Short name T800
Test name
Test status
Simulation time 33381057998 ps
CPU time 355.74 seconds
Started May 26 12:53:20 PM PDT 24
Finished May 26 12:59:16 PM PDT 24
Peak memory 250076 kb
Host smart-720a9941-7c6f-4b1b-95ca-f062c8e11338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518775646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1518775646
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1946600652
Short name T387
Test name
Test status
Simulation time 4674767001 ps
CPU time 36.72 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 217304 kb
Host smart-26dc82fe-6d06-46cb-b75d-e19e08fd44b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946600652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1946600652
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2720513224
Short name T877
Test name
Test status
Simulation time 605469485 ps
CPU time 15.71 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:53:38 PM PDT 24
Peak memory 229288 kb
Host smart-26ac4579-250e-4ae5-b37b-17fe63736e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720513224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2720513224
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.418201105
Short name T885
Test name
Test status
Simulation time 237649057 ps
CPU time 3.36 seconds
Started May 26 12:53:15 PM PDT 24
Finished May 26 12:53:19 PM PDT 24
Peak memory 234080 kb
Host smart-1dee766e-94b3-4d53-9df9-4621b246bdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418201105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.418201105
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3700958035
Short name T748
Test name
Test status
Simulation time 3519866034 ps
CPU time 27.33 seconds
Started May 26 12:53:12 PM PDT 24
Finished May 26 12:53:40 PM PDT 24
Peak memory 227148 kb
Host smart-c219892a-4713-462c-b4ea-4d48567a7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700958035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3700958035
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1417591078
Short name T47
Test name
Test status
Simulation time 2166253711 ps
CPU time 4.8 seconds
Started May 26 12:53:14 PM PDT 24
Finished May 26 12:53:19 PM PDT 24
Peak memory 219308 kb
Host smart-37c47a36-3cc1-4feb-8c95-26b1e3b8b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417591078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1417591078
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2301951875
Short name T608
Test name
Test status
Simulation time 49535987 ps
CPU time 2.21 seconds
Started May 26 12:53:13 PM PDT 24
Finished May 26 12:53:16 PM PDT 24
Peak memory 218456 kb
Host smart-82f5d64c-4b11-481e-b9e7-9688a9a613a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301951875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2301951875
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2358046496
Short name T602
Test name
Test status
Simulation time 940685883 ps
CPU time 10.9 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:39 PM PDT 24
Peak memory 220168 kb
Host smart-c2a15698-9beb-4f41-be24-ee3ba8c7c630
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358046496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2358046496
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1052863399
Short name T232
Test name
Test status
Simulation time 27073221597 ps
CPU time 275.86 seconds
Started May 26 12:53:27 PM PDT 24
Finished May 26 12:58:04 PM PDT 24
Peak memory 250012 kb
Host smart-1e95ecfb-fd2e-455f-bfd4-e2f6c75999e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052863399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1052863399
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2252358935
Short name T771
Test name
Test status
Simulation time 2983996058 ps
CPU time 21.2 seconds
Started May 26 12:53:11 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 216348 kb
Host smart-9bc97db4-573d-4e9e-950b-44114a111f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252358935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2252358935
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.664844991
Short name T446
Test name
Test status
Simulation time 1609302592 ps
CPU time 7.34 seconds
Started May 26 12:53:13 PM PDT 24
Finished May 26 12:53:21 PM PDT 24
Peak memory 216036 kb
Host smart-8ed9bc27-a910-4496-b368-d0f54cc6b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664844991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.664844991
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1171778712
Short name T543
Test name
Test status
Simulation time 43337650 ps
CPU time 0.78 seconds
Started May 26 12:53:13 PM PDT 24
Finished May 26 12:53:14 PM PDT 24
Peak memory 205904 kb
Host smart-85952069-b744-449a-a651-f162c56e86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171778712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1171778712
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.630637662
Short name T805
Test name
Test status
Simulation time 82856353 ps
CPU time 0.77 seconds
Started May 26 12:53:15 PM PDT 24
Finished May 26 12:53:16 PM PDT 24
Peak memory 205628 kb
Host smart-50a431c3-d7fd-47c4-9861-1293a09aa7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630637662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.630637662
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.891607813
Short name T300
Test name
Test status
Simulation time 11158880795 ps
CPU time 42.73 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:54:06 PM PDT 24
Peak memory 249640 kb
Host smart-8814031f-6fb6-4534-8b6d-e003bda342f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891607813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.891607813
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3574342540
Short name T519
Test name
Test status
Simulation time 59623943 ps
CPU time 0.71 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:24 PM PDT 24
Peak memory 205296 kb
Host smart-26c081ba-d97f-4c65-883f-1dd959a15f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574342540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3574342540
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1053186990
Short name T206
Test name
Test status
Simulation time 707502902 ps
CPU time 5.84 seconds
Started May 26 12:53:26 PM PDT 24
Finished May 26 12:53:32 PM PDT 24
Peak memory 233140 kb
Host smart-e00661a8-6242-44d3-a06a-85d8ee492ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053186990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1053186990
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3336979790
Short name T786
Test name
Test status
Simulation time 24946503 ps
CPU time 0.81 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:24 PM PDT 24
Peak memory 206396 kb
Host smart-289d31d8-1a6b-4d1e-8a52-dc9f8ab20e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336979790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3336979790
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2574635176
Short name T372
Test name
Test status
Simulation time 43739244 ps
CPU time 0.73 seconds
Started May 26 12:53:27 PM PDT 24
Finished May 26 12:53:28 PM PDT 24
Peak memory 215600 kb
Host smart-10a81899-3395-40a8-8132-ea331a5f4bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574635176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2574635176
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3866346702
Short name T779
Test name
Test status
Simulation time 42696108909 ps
CPU time 121.31 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 249032 kb
Host smart-a4d77b90-4709-4350-97a5-24796dcb1864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866346702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3866346702
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.721327476
Short name T297
Test name
Test status
Simulation time 750703581 ps
CPU time 3.24 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:27 PM PDT 24
Peak memory 232428 kb
Host smart-ef8c86d8-2265-4954-b3aa-19f44d913c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721327476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.721327476
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2657876807
Short name T638
Test name
Test status
Simulation time 13653263311 ps
CPU time 30.33 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 220516 kb
Host smart-d7185dab-eecf-4330-94d3-772c696659f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657876807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2657876807
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2567066421
Short name T315
Test name
Test status
Simulation time 1606087012 ps
CPU time 11.32 seconds
Started May 26 12:53:24 PM PDT 24
Finished May 26 12:53:36 PM PDT 24
Peak memory 216096 kb
Host smart-b574b9fe-ff83-43a7-b6c5-2922c36541aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567066421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2567066421
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1045255279
Short name T26
Test name
Test status
Simulation time 173211468 ps
CPU time 3.42 seconds
Started May 26 12:53:21 PM PDT 24
Finished May 26 12:53:25 PM PDT 24
Peak memory 233516 kb
Host smart-e5ec57e4-9f7f-490b-aca2-a2cd95289849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045255279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1045255279
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.525477814
Short name T282
Test name
Test status
Simulation time 677707035 ps
CPU time 9.76 seconds
Started May 26 12:53:22 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 250708 kb
Host smart-6ca5aef2-37d9-49f6-9481-75ee230957de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525477814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.525477814
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.468172706
Short name T815
Test name
Test status
Simulation time 113805857 ps
CPU time 3.92 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 222816 kb
Host smart-ee9a9d01-4e17-4a58-ad81-fdabb39dd78d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=468172706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.468172706
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3574296212
Short name T236
Test name
Test status
Simulation time 236997158788 ps
CPU time 420.4 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 01:00:24 PM PDT 24
Peak memory 254960 kb
Host smart-dac1d8e9-4398-404d-84ad-388ce7d7e2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574296212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3574296212
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4138821918
Short name T338
Test name
Test status
Simulation time 2463283559 ps
CPU time 24.32 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:48 PM PDT 24
Peak memory 219836 kb
Host smart-46327f5f-2fe4-4794-bb38-f218a6ae10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138821918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4138821918
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2595738790
Short name T468
Test name
Test status
Simulation time 2946615016 ps
CPU time 2.99 seconds
Started May 26 12:53:27 PM PDT 24
Finished May 26 12:53:31 PM PDT 24
Peak memory 207648 kb
Host smart-1419f011-f6f5-4403-b9c5-a9009c95037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595738790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2595738790
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4045138110
Short name T453
Test name
Test status
Simulation time 78779306 ps
CPU time 3.65 seconds
Started May 26 12:53:26 PM PDT 24
Finished May 26 12:53:30 PM PDT 24
Peak memory 216172 kb
Host smart-4dfe2d94-b5d0-4d2a-a136-8cf7603f8839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045138110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4045138110
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1558694969
Short name T401
Test name
Test status
Simulation time 68039460 ps
CPU time 0.88 seconds
Started May 26 12:53:25 PM PDT 24
Finished May 26 12:53:26 PM PDT 24
Peak memory 205640 kb
Host smart-7fda00cd-cba7-4eb6-b159-410fbafe651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558694969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1558694969
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4116215352
Short name T778
Test name
Test status
Simulation time 318168848 ps
CPU time 2.39 seconds
Started May 26 12:53:23 PM PDT 24
Finished May 26 12:53:26 PM PDT 24
Peak memory 224288 kb
Host smart-210799b9-c39a-4ba5-ac96-4097f6ab8c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116215352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4116215352
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2213257364
Short name T680
Test name
Test status
Simulation time 43193425 ps
CPU time 0.7 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 12:53:30 PM PDT 24
Peak memory 205380 kb
Host smart-1399d9bf-4090-4312-9b92-0b3bdad3e72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213257364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2213257364
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1363221568
Short name T574
Test name
Test status
Simulation time 1010571062 ps
CPU time 11.96 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 232500 kb
Host smart-2652be46-e766-4ac0-93fe-a92f96831445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363221568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1363221568
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1612137609
Short name T781
Test name
Test status
Simulation time 17590978 ps
CPU time 0.8 seconds
Started May 26 12:53:24 PM PDT 24
Finished May 26 12:53:25 PM PDT 24
Peak memory 206288 kb
Host smart-f40429b5-3b0a-45b0-8713-2ce5be87d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612137609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1612137609
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2775046992
Short name T768
Test name
Test status
Simulation time 6879199415 ps
CPU time 20.44 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 12:53:50 PM PDT 24
Peak memory 224284 kb
Host smart-17fcc3b4-fc03-468b-b328-22c36bba577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775046992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2775046992
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2990915505
Short name T665
Test name
Test status
Simulation time 845058544 ps
CPU time 9.59 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:39 PM PDT 24
Peak memory 218344 kb
Host smart-1cb9aeb4-a475-426a-bd3f-f875339aa513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990915505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2990915505
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2502339970
Short name T441
Test name
Test status
Simulation time 17803181393 ps
CPU time 42.56 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 12:54:12 PM PDT 24
Peak memory 222388 kb
Host smart-ce9ab1b9-ab3a-41cf-b5b1-b12ece9afe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502339970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2502339970
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1493281607
Short name T492
Test name
Test status
Simulation time 16389576361 ps
CPU time 12.73 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:42 PM PDT 24
Peak memory 226496 kb
Host smart-6b3dbe62-b2b7-4fd0-a82f-3f3573a47055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493281607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1493281607
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4024145
Short name T886
Test name
Test status
Simulation time 381329088 ps
CPU time 6.55 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 12:53:37 PM PDT 24
Peak memory 217664 kb
Host smart-4aaf3f14-ea43-45cd-9555-e2e9e7a9a1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4024145
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2972498846
Short name T39
Test name
Test status
Simulation time 3439215717 ps
CPU time 9.05 seconds
Started May 26 12:53:30 PM PDT 24
Finished May 26 12:53:39 PM PDT 24
Peak memory 220156 kb
Host smart-688b891e-4cae-4bef-8672-1a5fbbc45157
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972498846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2972498846
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1899974151
Short name T941
Test name
Test status
Simulation time 45255044137 ps
CPU time 18.22 seconds
Started May 26 12:53:33 PM PDT 24
Finished May 26 12:53:51 PM PDT 24
Peak memory 216216 kb
Host smart-e5204aee-0b76-4120-ba84-b9549fbdd99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899974151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1899974151
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3154510385
Short name T423
Test name
Test status
Simulation time 789288195 ps
CPU time 6.54 seconds
Started May 26 12:53:29 PM PDT 24
Finished May 26 12:53:36 PM PDT 24
Peak memory 215936 kb
Host smart-86983991-20a2-4a1d-8ed9-a9f7a6abe8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154510385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3154510385
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2870860667
Short name T755
Test name
Test status
Simulation time 26235295 ps
CPU time 0.84 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:29 PM PDT 24
Peak memory 206320 kb
Host smart-082227ab-06fb-4341-95fe-25f8a9b61815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870860667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2870860667
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2322335576
Short name T531
Test name
Test status
Simulation time 36266204 ps
CPU time 0.85 seconds
Started May 26 12:53:28 PM PDT 24
Finished May 26 12:53:30 PM PDT 24
Peak memory 205524 kb
Host smart-29d10e56-af18-455d-a36b-ede8936c3ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322335576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2322335576
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3064137302
Short name T227
Test name
Test status
Simulation time 3460603758 ps
CPU time 6.97 seconds
Started May 26 12:53:30 PM PDT 24
Finished May 26 12:53:37 PM PDT 24
Peak memory 219812 kb
Host smart-2c4cc3ca-463e-4f57-b988-67d7f1a84710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064137302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3064137302
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1154029962
Short name T724
Test name
Test status
Simulation time 50358758 ps
CPU time 0.7 seconds
Started May 26 12:53:40 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 205704 kb
Host smart-ea6bd79b-9b1f-466b-974a-c05e782d18bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154029962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1154029962
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1392477444
Short name T930
Test name
Test status
Simulation time 2196834124 ps
CPU time 10.16 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:49 PM PDT 24
Peak memory 234524 kb
Host smart-657c4b2f-c557-4e3e-a84d-5ee3ed1093e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392477444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1392477444
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3394370656
Short name T830
Test name
Test status
Simulation time 19817699 ps
CPU time 0.8 seconds
Started May 26 12:53:36 PM PDT 24
Finished May 26 12:53:38 PM PDT 24
Peak memory 206304 kb
Host smart-3bc21871-00ca-4ca7-9633-92d8a8cbd754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394370656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3394370656
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2822082573
Short name T167
Test name
Test status
Simulation time 9932584302 ps
CPU time 103.12 seconds
Started May 26 12:53:36 PM PDT 24
Finished May 26 12:55:20 PM PDT 24
Peak memory 255116 kb
Host smart-d491fb95-a965-4b1b-91e0-9b73bc59aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822082573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2822082573
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.661691889
Short name T869
Test name
Test status
Simulation time 150313727760 ps
CPU time 335.05 seconds
Started May 26 12:53:39 PM PDT 24
Finished May 26 12:59:15 PM PDT 24
Peak memory 256952 kb
Host smart-1e458963-fba9-44c5-9c6c-550119b07fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661691889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.661691889
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.697161702
Short name T173
Test name
Test status
Simulation time 798422826 ps
CPU time 3.33 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:42 PM PDT 24
Peak memory 224232 kb
Host smart-0b6ec0ff-3ea9-4d28-a648-3f89cd1bf0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697161702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.697161702
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1607487480
Short name T891
Test name
Test status
Simulation time 7640871326 ps
CPU time 7.39 seconds
Started May 26 12:53:39 PM PDT 24
Finished May 26 12:53:47 PM PDT 24
Peak memory 224312 kb
Host smart-f414744b-7dc2-4790-ac5e-874d33ff6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607487480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1607487480
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.496736999
Short name T283
Test name
Test status
Simulation time 5199747495 ps
CPU time 17.95 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:56 PM PDT 24
Peak memory 240408 kb
Host smart-b7e8eb77-ce7d-4d2e-b8d4-6894d7b2b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496736999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.496736999
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2319100068
Short name T552
Test name
Test status
Simulation time 107497992 ps
CPU time 2.48 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 221184 kb
Host smart-2d3e2caa-8ec8-4976-9afc-38f198c744c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319100068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2319100068
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4129877638
Short name T817
Test name
Test status
Simulation time 1507660835 ps
CPU time 6.04 seconds
Started May 26 12:54:02 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 218652 kb
Host smart-d80d9656-3037-4b35-8b23-18bbeeb41cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129877638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4129877638
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1184443637
Short name T405
Test name
Test status
Simulation time 3602101773 ps
CPU time 14.53 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:53 PM PDT 24
Peak memory 220032 kb
Host smart-32ccd95b-72d7-4291-8596-9de247c60cf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1184443637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1184443637
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4028072511
Short name T153
Test name
Test status
Simulation time 11193903675 ps
CPU time 103.29 seconds
Started May 26 12:53:37 PM PDT 24
Finished May 26 12:55:20 PM PDT 24
Peak memory 249196 kb
Host smart-9d9701e6-b044-45c6-a602-24650cf2f4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028072511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4028072511
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2629661756
Short name T343
Test name
Test status
Simulation time 42746307669 ps
CPU time 13.49 seconds
Started May 26 12:53:37 PM PDT 24
Finished May 26 12:53:52 PM PDT 24
Peak memory 216332 kb
Host smart-a05215c6-c853-4720-a939-f455065bcf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629661756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2629661756
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.756598651
Short name T349
Test name
Test status
Simulation time 3172207392 ps
CPU time 3.28 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:42 PM PDT 24
Peak memory 215984 kb
Host smart-aa5544ad-3ec9-4c91-a167-69378942c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756598651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.756598651
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2052535428
Short name T420
Test name
Test status
Simulation time 41587797 ps
CPU time 1.42 seconds
Started May 26 12:53:37 PM PDT 24
Finished May 26 12:53:40 PM PDT 24
Peak memory 216076 kb
Host smart-b379ddc4-7c63-4616-9757-f99ec3c22b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052535428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2052535428
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4057522586
Short name T804
Test name
Test status
Simulation time 58645869 ps
CPU time 0.81 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:40 PM PDT 24
Peak memory 205636 kb
Host smart-08696a93-ccd9-4ff5-902c-eda264535cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057522586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4057522586
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.446343587
Short name T295
Test name
Test status
Simulation time 18678438637 ps
CPU time 19.11 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:58 PM PDT 24
Peak memory 245536 kb
Host smart-52179509-3067-493a-ad52-1e2ce8f23863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446343587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.446343587
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1816055576
Short name T918
Test name
Test status
Simulation time 69873081 ps
CPU time 0.71 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:53:49 PM PDT 24
Peak memory 205224 kb
Host smart-6ead3e46-cf7b-4e67-b530-36a5d45536cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816055576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1816055576
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2465399811
Short name T796
Test name
Test status
Simulation time 243848500 ps
CPU time 4.15 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:53:51 PM PDT 24
Peak memory 219424 kb
Host smart-fa506db2-eff4-4268-8d6a-591531345ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465399811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2465399811
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3207857196
Short name T498
Test name
Test status
Simulation time 13998329 ps
CPU time 0.82 seconds
Started May 26 12:53:36 PM PDT 24
Finished May 26 12:53:38 PM PDT 24
Peak memory 206628 kb
Host smart-a9ebd8ce-720b-4870-b995-7bbd73d62e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207857196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3207857196
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4230811613
Short name T841
Test name
Test status
Simulation time 686438740 ps
CPU time 17.09 seconds
Started May 26 12:53:50 PM PDT 24
Finished May 26 12:54:08 PM PDT 24
Peak memory 249888 kb
Host smart-1620fd92-bf7d-4aaa-8855-b2a70a4b8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230811613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4230811613
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.296338452
Short name T309
Test name
Test status
Simulation time 65920061164 ps
CPU time 160.32 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:56:27 PM PDT 24
Peak memory 249040 kb
Host smart-569d8182-2207-4abe-ba07-709ea579f7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296338452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.296338452
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3948547394
Short name T28
Test name
Test status
Simulation time 53367909621 ps
CPU time 423.76 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 01:00:52 PM PDT 24
Peak memory 270132 kb
Host smart-b69ea17f-e78c-4cb0-9f95-46506bdc3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948547394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3948547394
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1771040477
Short name T209
Test name
Test status
Simulation time 1359407311 ps
CPU time 5.68 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 217416 kb
Host smart-d24b4058-04a1-478f-a78d-96631189ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771040477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1771040477
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2748992441
Short name T942
Test name
Test status
Simulation time 9718669552 ps
CPU time 68.29 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 238476 kb
Host smart-076066aa-098a-4306-a4e2-57a45e01436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748992441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2748992441
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2877201808
Short name T520
Test name
Test status
Simulation time 2232787579 ps
CPU time 7.87 seconds
Started May 26 12:53:45 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 219428 kb
Host smart-024ea3f8-89bd-4b35-b6d0-e0c553aebf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877201808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2877201808
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2772789197
Short name T506
Test name
Test status
Simulation time 31433391222 ps
CPU time 12.91 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:54:01 PM PDT 24
Peak memory 237876 kb
Host smart-81b7e22a-b33c-4cde-8cec-e1cb88fb9664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772789197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2772789197
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3461373880
Short name T87
Test name
Test status
Simulation time 343375841 ps
CPU time 3.49 seconds
Started May 26 12:53:57 PM PDT 24
Finished May 26 12:54:01 PM PDT 24
Peak memory 218740 kb
Host smart-bc986b1a-2915-4912-8ab3-8203f73573ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461373880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3461373880
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.19103682
Short name T149
Test name
Test status
Simulation time 68634278 ps
CPU time 1.08 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:53:48 PM PDT 24
Peak memory 206960 kb
Host smart-57e5609d-294c-4d02-b6ee-a59c2c6103ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress
_all.19103682
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.597666502
Short name T528
Test name
Test status
Simulation time 20732545055 ps
CPU time 30.09 seconds
Started May 26 12:53:37 PM PDT 24
Finished May 26 12:54:08 PM PDT 24
Peak memory 220636 kb
Host smart-84bdde55-d084-4c6e-bb6b-ddfc007813c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597666502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.597666502
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3523695611
Short name T702
Test name
Test status
Simulation time 1043374628 ps
CPU time 5.04 seconds
Started May 26 12:53:37 PM PDT 24
Finished May 26 12:53:42 PM PDT 24
Peak memory 215964 kb
Host smart-5cf22aaa-4f9e-4197-b94c-8a16966069ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523695611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3523695611
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1393180969
Short name T126
Test name
Test status
Simulation time 166980056 ps
CPU time 1.21 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:53:49 PM PDT 24
Peak memory 207700 kb
Host smart-6445b8f2-54cc-4c8f-bb50-78a18b04ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393180969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1393180969
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3125392804
Short name T595
Test name
Test status
Simulation time 10038583 ps
CPU time 0.68 seconds
Started May 26 12:53:38 PM PDT 24
Finished May 26 12:53:39 PM PDT 24
Peak memory 205416 kb
Host smart-6754a4b6-14e9-4737-9a84-f18ee1df22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125392804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3125392804
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2986944373
Short name T183
Test name
Test status
Simulation time 12363437344 ps
CPU time 33.76 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:54:20 PM PDT 24
Peak memory 251684 kb
Host smart-bee97ab3-1d0e-4ac6-910c-7a8bae98d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986944373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2986944373
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2600820090
Short name T499
Test name
Test status
Simulation time 11637876 ps
CPU time 0.69 seconds
Started May 26 12:53:54 PM PDT 24
Finished May 26 12:53:55 PM PDT 24
Peak memory 204692 kb
Host smart-c61c414f-2f67-4315-8858-60d874cb029c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600820090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2600820090
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.408231998
Short name T575
Test name
Test status
Simulation time 446037763 ps
CPU time 5.69 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:53:53 PM PDT 24
Peak memory 218440 kb
Host smart-935a4a26-14fe-47e2-a6e7-3da49db58637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408231998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.408231998
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2832003627
Short name T811
Test name
Test status
Simulation time 26033172 ps
CPU time 0.73 seconds
Started May 26 12:53:45 PM PDT 24
Finished May 26 12:53:46 PM PDT 24
Peak memory 205252 kb
Host smart-fb46955b-afd3-4943-a278-cd619226d2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832003627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2832003627
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.527405369
Short name T916
Test name
Test status
Simulation time 80225652032 ps
CPU time 291.52 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:58:39 PM PDT 24
Peak memory 240716 kb
Host smart-50ebc2bc-e0a8-42f0-8374-22fc10081341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527405369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.527405369
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3722890005
Short name T428
Test name
Test status
Simulation time 7611362345 ps
CPU time 125.9 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 252476 kb
Host smart-f31e5b12-0507-485a-8e9b-53185e855bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722890005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3722890005
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3820929699
Short name T643
Test name
Test status
Simulation time 48647986025 ps
CPU time 459.01 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 254168 kb
Host smart-4840d45a-cb1b-4ddc-bc8d-451edd559611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820929699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3820929699
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.248476446
Short name T727
Test name
Test status
Simulation time 238216188 ps
CPU time 4.43 seconds
Started May 26 12:53:49 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 232556 kb
Host smart-c805fb56-0a54-4305-bb8e-79daaf006ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248476446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.248476446
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3273281221
Short name T217
Test name
Test status
Simulation time 284268545 ps
CPU time 5.61 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:53:53 PM PDT 24
Peak memory 219780 kb
Host smart-cfe75556-a509-45a7-99d5-516482b1fbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273281221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3273281221
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3770963915
Short name T839
Test name
Test status
Simulation time 74313349 ps
CPU time 2.92 seconds
Started May 26 12:53:49 PM PDT 24
Finished May 26 12:53:53 PM PDT 24
Peak memory 234048 kb
Host smart-156071aa-cee6-4e39-97d6-5914d6cf1541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770963915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3770963915
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.542214422
Short name T219
Test name
Test status
Simulation time 521222832 ps
CPU time 2.43 seconds
Started May 26 12:53:50 PM PDT 24
Finished May 26 12:53:53 PM PDT 24
Peak memory 218688 kb
Host smart-229e06c4-ec9b-4456-9c50-f18491962f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542214422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.542214422
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3449023196
Short name T182
Test name
Test status
Simulation time 6545937829 ps
CPU time 11.04 seconds
Started May 26 12:53:47 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 232632 kb
Host smart-c99d895e-d53f-44da-be29-f81949931e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449023196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3449023196
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.584196842
Short name T615
Test name
Test status
Simulation time 365047037 ps
CPU time 7.68 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 222616 kb
Host smart-efd37ef8-0ad1-4742-a0f1-490960f04867
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=584196842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.584196842
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.888522731
Short name T122
Test name
Test status
Simulation time 5344610946 ps
CPU time 52.67 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:54:48 PM PDT 24
Peak memory 250764 kb
Host smart-e0a8237a-80e4-4809-b3eb-321d8f855f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888522731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.888522731
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1638613755
Short name T949
Test name
Test status
Simulation time 38720602 ps
CPU time 0.71 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:53:50 PM PDT 24
Peak memory 205276 kb
Host smart-fb8f0105-f516-4cc1-98bf-2bb3e35036d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638613755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1638613755
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1690892358
Short name T86
Test name
Test status
Simulation time 861555594 ps
CPU time 2.76 seconds
Started May 26 12:53:46 PM PDT 24
Finished May 26 12:53:49 PM PDT 24
Peak memory 215940 kb
Host smart-9e850e8a-c593-45e6-9b78-23e8f0c49b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690892358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1690892358
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1177881097
Short name T668
Test name
Test status
Simulation time 3431403834 ps
CPU time 2.62 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:53:51 PM PDT 24
Peak memory 216280 kb
Host smart-ef077f62-8b19-42e6-8d9d-b4730530d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177881097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1177881097
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4263737130
Short name T542
Test name
Test status
Simulation time 55929834 ps
CPU time 0.82 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:53:50 PM PDT 24
Peak memory 205536 kb
Host smart-b460b168-3219-4088-9d6e-edf713359d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263737130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4263737130
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3862993086
Short name T798
Test name
Test status
Simulation time 544305231 ps
CPU time 5.85 seconds
Started May 26 12:53:48 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 233372 kb
Host smart-4a5fc853-1ca3-45ff-9825-b82cb67b3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862993086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3862993086
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3203084657
Short name T855
Test name
Test status
Simulation time 29226229 ps
CPU time 0.72 seconds
Started May 26 12:53:54 PM PDT 24
Finished May 26 12:53:56 PM PDT 24
Peak memory 205228 kb
Host smart-1658f55d-8b54-420f-881d-966b2bf285a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203084657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3203084657
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3241398978
Short name T536
Test name
Test status
Simulation time 1919785254 ps
CPU time 13.6 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 233356 kb
Host smart-118c421a-6351-4cce-9f2b-f41cd3521d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241398978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3241398978
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1766330643
Short name T694
Test name
Test status
Simulation time 22271441 ps
CPU time 0.74 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:53:58 PM PDT 24
Peak memory 205608 kb
Host smart-c34eab0c-5c21-4b4d-b761-fc50650cda34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766330643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1766330643
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1670698303
Short name T169
Test name
Test status
Simulation time 106711599303 ps
CPU time 125.61 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 251840 kb
Host smart-f234cba3-acc3-4b3b-90fe-d8540f16c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670698303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1670698303
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2265626089
Short name T46
Test name
Test status
Simulation time 79140224025 ps
CPU time 374.95 seconds
Started May 26 12:53:56 PM PDT 24
Finished May 26 01:00:12 PM PDT 24
Peak memory 252656 kb
Host smart-7dd5f400-49dc-4fe6-9d2f-1d4554d1303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265626089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2265626089
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3085047548
Short name T537
Test name
Test status
Simulation time 18545291710 ps
CPU time 80.31 seconds
Started May 26 12:53:57 PM PDT 24
Finished May 26 12:55:18 PM PDT 24
Peak memory 240644 kb
Host smart-5a892229-2936-4b6a-a758-57e3528371f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085047548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3085047548
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1401989854
Short name T589
Test name
Test status
Simulation time 339862961 ps
CPU time 5.5 seconds
Started May 26 12:53:56 PM PDT 24
Finished May 26 12:54:03 PM PDT 24
Peak memory 233780 kb
Host smart-5c7ff9d6-44db-43aa-8b7b-d7e4f8fcb4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401989854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1401989854
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.193991228
Short name T450
Test name
Test status
Simulation time 697459606 ps
CPU time 3.17 seconds
Started May 26 12:53:56 PM PDT 24
Finished May 26 12:54:00 PM PDT 24
Peak memory 218416 kb
Host smart-5b97c67d-424e-42cd-be70-9eb976082742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193991228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.193991228
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.338691649
Short name T220
Test name
Test status
Simulation time 44657432500 ps
CPU time 32.83 seconds
Started May 26 12:53:56 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 240772 kb
Host smart-4b6cd696-83f7-4f2e-a312-94b8e28648b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338691649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.338691649
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3814557853
Short name T550
Test name
Test status
Simulation time 1086811119 ps
CPU time 5.55 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:54:01 PM PDT 24
Peak memory 239984 kb
Host smart-0634bfea-9d40-461a-80e3-3c4e5a14324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814557853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3814557853
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.649405546
Short name T448
Test name
Test status
Simulation time 222488121 ps
CPU time 4.58 seconds
Started May 26 12:53:54 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 222852 kb
Host smart-a4ae6b0d-2bb0-490f-87b0-e8b88d955d35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=649405546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.649405546
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1889217426
Short name T557
Test name
Test status
Simulation time 5252134237 ps
CPU time 31.91 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:54:28 PM PDT 24
Peak memory 216216 kb
Host smart-aea946fa-d6d3-4e7a-85ac-0cbfc4fe907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889217426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1889217426
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.191728993
Short name T364
Test name
Test status
Simulation time 1809109979 ps
CPU time 3.8 seconds
Started May 26 12:53:54 PM PDT 24
Finished May 26 12:53:58 PM PDT 24
Peak memory 216020 kb
Host smart-ba491e17-0e3a-4dcb-922c-255c5f44329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191728993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.191728993
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1698754846
Short name T637
Test name
Test status
Simulation time 25320805 ps
CPU time 1.68 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:53:57 PM PDT 24
Peak memory 216192 kb
Host smart-0a3ebc0a-f660-4e2b-8a6e-ea868e510345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698754846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1698754846
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2550902271
Short name T912
Test name
Test status
Simulation time 482782688 ps
CPU time 1.05 seconds
Started May 26 12:53:54 PM PDT 24
Finished May 26 12:53:56 PM PDT 24
Peak memory 206552 kb
Host smart-13c6cf71-9179-497e-988f-1dd510f4d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550902271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2550902271
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3131290848
Short name T414
Test name
Test status
Simulation time 1006407743 ps
CPU time 7.92 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:54:04 PM PDT 24
Peak memory 227368 kb
Host smart-f54662be-b86a-44b6-b70f-7f3edeb48747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131290848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3131290848
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3619032210
Short name T444
Test name
Test status
Simulation time 30117977 ps
CPU time 0.71 seconds
Started May 26 12:52:05 PM PDT 24
Finished May 26 12:52:06 PM PDT 24
Peak memory 205632 kb
Host smart-d700ee5c-1c79-4925-85e5-f86fd1b72c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619032210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
619032210
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1366408743
Short name T834
Test name
Test status
Simulation time 7043088754 ps
CPU time 18.35 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:52:20 PM PDT 24
Peak memory 219732 kb
Host smart-11d54a95-03ed-42c4-8b2b-74da7ca2ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366408743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1366408743
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2766028871
Short name T684
Test name
Test status
Simulation time 57999023 ps
CPU time 0.81 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:52:02 PM PDT 24
Peak memory 206304 kb
Host smart-ef0e4a8c-a297-458c-8302-b86798610781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766028871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2766028871
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.968459846
Short name T852
Test name
Test status
Simulation time 57957588619 ps
CPU time 99.35 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 234780 kb
Host smart-31ad014d-ac68-4dd7-9fe4-c5b67f01d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968459846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.968459846
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1831047788
Short name T171
Test name
Test status
Simulation time 36298765153 ps
CPU time 239.79 seconds
Started May 26 12:52:01 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 255640 kb
Host smart-f9f00730-0ab5-4b5b-9d60-53b04c733d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831047788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1831047788
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2419369179
Short name T143
Test name
Test status
Simulation time 167592653 ps
CPU time 7.16 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 240056 kb
Host smart-325048cc-eb0c-414f-b67e-29d42cd894ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419369179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2419369179
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3526975057
Short name T281
Test name
Test status
Simulation time 125356383 ps
CPU time 4.24 seconds
Started May 26 12:51:57 PM PDT 24
Finished May 26 12:52:02 PM PDT 24
Peak memory 233900 kb
Host smart-051185df-ddba-4a7f-a600-7342bfacf007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526975057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3526975057
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3663054533
Short name T844
Test name
Test status
Simulation time 2805859070 ps
CPU time 12.71 seconds
Started May 26 12:51:58 PM PDT 24
Finished May 26 12:52:12 PM PDT 24
Peak memory 218352 kb
Host smart-5742369c-1a53-4b4c-8bc6-c2d639d6e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663054533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3663054533
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3967161014
Short name T357
Test name
Test status
Simulation time 117101350 ps
CPU time 2.46 seconds
Started May 26 12:51:58 PM PDT 24
Finished May 26 12:52:02 PM PDT 24
Peak memory 221088 kb
Host smart-3ae6ffd8-ae64-43fe-997c-dc036f3b272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967161014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3967161014
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1187363640
Short name T7
Test name
Test status
Simulation time 1102078115 ps
CPU time 6.04 seconds
Started May 26 12:52:00 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 237084 kb
Host smart-eb3d1dc8-d1b4-45d4-9d57-f3623e07821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187363640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1187363640
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1725768336
Short name T860
Test name
Test status
Simulation time 246473451 ps
CPU time 4.49 seconds
Started May 26 12:51:59 PM PDT 24
Finished May 26 12:52:04 PM PDT 24
Peak memory 222696 kb
Host smart-024c8d56-3ed5-42c9-8abb-ef39bb89acfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725768336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1725768336
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2525008455
Short name T66
Test name
Test status
Simulation time 504242436 ps
CPU time 1.21 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:09 PM PDT 24
Peak memory 235028 kb
Host smart-35708a4d-740c-4d82-b13b-67f0def112f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525008455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2525008455
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1522742027
Short name T510
Test name
Test status
Simulation time 24840928039 ps
CPU time 104.15 seconds
Started May 26 12:52:00 PM PDT 24
Finished May 26 12:53:45 PM PDT 24
Peak memory 236052 kb
Host smart-7a7fcbd0-900c-4f1b-8a37-9ff303cdead4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522742027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1522742027
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3340245939
Short name T336
Test name
Test status
Simulation time 12845113676 ps
CPU time 14.84 seconds
Started May 26 12:52:02 PM PDT 24
Finished May 26 12:52:17 PM PDT 24
Peak memory 216252 kb
Host smart-b0d276a4-3e2c-4597-bbcf-ec137b60ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340245939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3340245939
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1179077804
Short name T728
Test name
Test status
Simulation time 11731059520 ps
CPU time 11.32 seconds
Started May 26 12:52:00 PM PDT 24
Finished May 26 12:52:12 PM PDT 24
Peak memory 216072 kb
Host smart-d64f4cb0-d1c2-4d35-9a9f-2dea02f71830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179077804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1179077804
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.201782465
Short name T726
Test name
Test status
Simulation time 791115445 ps
CPU time 1.45 seconds
Started May 26 12:51:58 PM PDT 24
Finished May 26 12:52:00 PM PDT 24
Peak memory 216032 kb
Host smart-d15bedef-e567-4a54-af15-d90c504ea809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201782465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.201782465
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3802414375
Short name T744
Test name
Test status
Simulation time 158961765 ps
CPU time 0.81 seconds
Started May 26 12:52:02 PM PDT 24
Finished May 26 12:52:03 PM PDT 24
Peak memory 205484 kb
Host smart-50d2d39b-9b68-45c0-afe2-91e0ee601f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802414375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3802414375
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1754350299
Short name T75
Test name
Test status
Simulation time 29815398062 ps
CPU time 25.21 seconds
Started May 26 12:52:00 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 234332 kb
Host smart-bd69c9fc-ce36-4623-ae39-932839c6db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754350299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1754350299
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.586119169
Short name T347
Test name
Test status
Simulation time 14131340 ps
CPU time 0.7 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:07 PM PDT 24
Peak memory 205556 kb
Host smart-b20bba61-c79e-4813-9126-d99ffed7eb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586119169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.586119169
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3837273274
Short name T606
Test name
Test status
Simulation time 473520091 ps
CPU time 3.37 seconds
Started May 26 12:54:08 PM PDT 24
Finished May 26 12:54:12 PM PDT 24
Peak memory 234200 kb
Host smart-da46f9ab-a984-4197-ad92-b2f362e6edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837273274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3837273274
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1191763075
Short name T55
Test name
Test status
Simulation time 16385695 ps
CPU time 0.77 seconds
Started May 26 12:53:55 PM PDT 24
Finished May 26 12:53:57 PM PDT 24
Peak memory 206624 kb
Host smart-f04f23d3-dcb2-40e7-accc-218ec4d890f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191763075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1191763075
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2538642141
Short name T10
Test name
Test status
Simulation time 31171439 ps
CPU time 0.83 seconds
Started May 26 12:54:08 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 215928 kb
Host smart-bff432ba-00fe-4cdf-a4f0-88fdbdbe2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538642141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2538642141
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4220936411
Short name T161
Test name
Test status
Simulation time 2746273345 ps
CPU time 61.68 seconds
Started May 26 12:54:07 PM PDT 24
Finished May 26 12:55:10 PM PDT 24
Peak memory 249004 kb
Host smart-027c67fd-a628-4138-94d6-6902a4633acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220936411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4220936411
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3876303588
Short name T504
Test name
Test status
Simulation time 11082223116 ps
CPU time 34.46 seconds
Started May 26 12:54:07 PM PDT 24
Finished May 26 12:54:43 PM PDT 24
Peak memory 239768 kb
Host smart-195ba3ba-8469-42f9-bf05-9d3294181fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876303588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3876303588
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3040557272
Short name T442
Test name
Test status
Simulation time 421198812 ps
CPU time 5.87 seconds
Started May 26 12:54:09 PM PDT 24
Finished May 26 12:54:15 PM PDT 24
Peak memory 233180 kb
Host smart-b330b5b8-b533-484a-bd04-1904095e7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040557272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3040557272
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1232507785
Short name T616
Test name
Test status
Simulation time 952423034 ps
CPU time 7.89 seconds
Started May 26 12:54:03 PM PDT 24
Finished May 26 12:54:11 PM PDT 24
Peak memory 233916 kb
Host smart-4e22a434-e979-4253-b8c3-37b29937b7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232507785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1232507785
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.442528350
Short name T439
Test name
Test status
Simulation time 23098726885 ps
CPU time 16.64 seconds
Started May 26 12:54:06 PM PDT 24
Finished May 26 12:54:24 PM PDT 24
Peak memory 230092 kb
Host smart-42c5add4-12e1-4aa1-a3ee-6b2be0bd18fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442528350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.442528350
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3089415975
Short name T911
Test name
Test status
Simulation time 7232770959 ps
CPU time 11.59 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:18 PM PDT 24
Peak memory 234028 kb
Host smart-62fcf1e4-c333-48bf-8a14-f9b453ae6a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089415975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3089415975
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.793916105
Short name T463
Test name
Test status
Simulation time 127254021 ps
CPU time 4.51 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:11 PM PDT 24
Peak memory 222744 kb
Host smart-686dcd84-62fa-4a70-89b8-c62c6fad8abc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793916105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.793916105
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1178464450
Short name T593
Test name
Test status
Simulation time 52658533 ps
CPU time 0.96 seconds
Started May 26 12:54:04 PM PDT 24
Finished May 26 12:54:05 PM PDT 24
Peak memory 205424 kb
Host smart-7368fa29-9722-45ec-b32f-772097cb3444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178464450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1178464450
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2659264717
Short name T597
Test name
Test status
Simulation time 2939935247 ps
CPU time 21.99 seconds
Started May 26 12:53:56 PM PDT 24
Finished May 26 12:54:19 PM PDT 24
Peak memory 216212 kb
Host smart-1160678e-fff9-4faf-af46-a2799645862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659264717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2659264717
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2130139153
Short name T397
Test name
Test status
Simulation time 3427114205 ps
CPU time 13.28 seconds
Started May 26 12:53:57 PM PDT 24
Finished May 26 12:54:11 PM PDT 24
Peak memory 216140 kb
Host smart-cef65952-f24b-4a7c-9a0b-50c83ce9979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130139153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2130139153
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2756922432
Short name T733
Test name
Test status
Simulation time 62069863 ps
CPU time 1.2 seconds
Started May 26 12:54:07 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 216048 kb
Host smart-12c3c8a6-add8-42a1-8226-5b7437551389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756922432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2756922432
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2355558728
Short name T761
Test name
Test status
Simulation time 209456735 ps
CPU time 0.87 seconds
Started May 26 12:54:07 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 204456 kb
Host smart-a1fb9b71-9569-4d94-804c-4dfb45ed3f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355558728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2355558728
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4101057739
Short name T570
Test name
Test status
Simulation time 1198409337 ps
CPU time 7.77 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:13 PM PDT 24
Peak memory 234996 kb
Host smart-60118028-ab96-4f19-b1cf-e23a89815807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101057739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4101057739
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2191155939
Short name T626
Test name
Test status
Simulation time 29266494 ps
CPU time 0.74 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:16 PM PDT 24
Peak memory 205256 kb
Host smart-3576edc6-a5a0-4c37-9189-1fb09f4bb866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191155939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2191155939
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3387832129
Short name T4
Test name
Test status
Simulation time 329091261 ps
CPU time 2.43 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:18 PM PDT 24
Peak memory 218272 kb
Host smart-7d5f0209-2ad7-4939-b7f4-ae0c2fd57fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387832129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3387832129
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2291988183
Short name T399
Test name
Test status
Simulation time 49486829 ps
CPU time 0.76 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:06 PM PDT 24
Peak memory 205292 kb
Host smart-efca290e-58f9-48ac-8c1a-33e08a389019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291988183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2291988183
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2110372819
Short name T931
Test name
Test status
Simulation time 1763894602 ps
CPU time 32.97 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:48 PM PDT 24
Peak memory 237872 kb
Host smart-191bac27-583a-42f9-9efb-96fb96752310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110372819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2110372819
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1455689276
Short name T292
Test name
Test status
Simulation time 125185988 ps
CPU time 2.58 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 232488 kb
Host smart-00ab2959-9afa-4b25-af3e-5133daec7103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455689276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1455689276
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.30624700
Short name T667
Test name
Test status
Simulation time 6344454337 ps
CPU time 44.56 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:50 PM PDT 24
Peak memory 240436 kb
Host smart-fd4a8c73-e297-49b8-b102-d793419644bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30624700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.30624700
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1865074675
Short name T892
Test name
Test status
Simulation time 664090859 ps
CPU time 4.21 seconds
Started May 26 12:54:06 PM PDT 24
Finished May 26 12:54:11 PM PDT 24
Peak memory 233604 kb
Host smart-e01d6dee-ac7a-4899-8ece-8fb14beaa907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865074675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1865074675
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3394615262
Short name T555
Test name
Test status
Simulation time 205988753 ps
CPU time 2.79 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:09 PM PDT 24
Peak memory 232908 kb
Host smart-5d395cff-a85b-4c28-96c5-3c0de246be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394615262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3394615262
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2429353944
Short name T144
Test name
Test status
Simulation time 10803473433 ps
CPU time 17.25 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:33 PM PDT 24
Peak memory 219928 kb
Host smart-a5ffe901-e78e-4128-af6c-48669a006c66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429353944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2429353944
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2710857356
Short name T425
Test name
Test status
Simulation time 111692184 ps
CPU time 0.93 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:17 PM PDT 24
Peak memory 206276 kb
Host smart-9162ffd3-98f4-4f8b-be97-b9c9c50bc8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710857356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2710857356
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1910172567
Short name T335
Test name
Test status
Simulation time 1961339392 ps
CPU time 25.48 seconds
Started May 26 12:54:05 PM PDT 24
Finished May 26 12:54:31 PM PDT 24
Peak memory 216076 kb
Host smart-e29e504b-789c-4041-8829-a76885e1a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910172567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1910172567
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1924116307
Short name T730
Test name
Test status
Simulation time 11873642891 ps
CPU time 8.02 seconds
Started May 26 12:54:06 PM PDT 24
Finished May 26 12:54:15 PM PDT 24
Peak memory 216100 kb
Host smart-f0a9e9a9-0dad-4087-bbc0-a670c0565338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924116307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1924116307
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1543957299
Short name T683
Test name
Test status
Simulation time 17308315 ps
CPU time 0.68 seconds
Started May 26 12:54:07 PM PDT 24
Finished May 26 12:54:08 PM PDT 24
Peak memory 205440 kb
Host smart-81d9ea7f-ead2-422b-a739-a8b34adc1787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543957299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1543957299
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1376277041
Short name T858
Test name
Test status
Simulation time 36887136 ps
CPU time 0.67 seconds
Started May 26 12:54:06 PM PDT 24
Finished May 26 12:54:08 PM PDT 24
Peak memory 205432 kb
Host smart-d4b43aed-08bb-4f52-b0c0-c9d7f2b579db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376277041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1376277041
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.263269630
Short name T437
Test name
Test status
Simulation time 3928179867 ps
CPU time 16.02 seconds
Started May 26 12:54:16 PM PDT 24
Finished May 26 12:54:32 PM PDT 24
Peak memory 223156 kb
Host smart-3741a130-e416-4508-bff9-385278587156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263269630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.263269630
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2285558936
Short name T634
Test name
Test status
Simulation time 37338143 ps
CPU time 0.68 seconds
Started May 26 12:54:29 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 205404 kb
Host smart-2da69f1e-249c-48e7-892b-50dc16e1a6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285558936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2285558936
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2980078071
Short name T671
Test name
Test status
Simulation time 1736987570 ps
CPU time 18.19 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:34 PM PDT 24
Peak memory 234080 kb
Host smart-55afef42-74fa-4ba0-aa67-d65a2a127800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980078071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2980078071
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2805660311
Short name T831
Test name
Test status
Simulation time 59250835 ps
CPU time 0.84 seconds
Started May 26 12:54:16 PM PDT 24
Finished May 26 12:54:18 PM PDT 24
Peak memory 206392 kb
Host smart-d26bc478-94e6-4032-a6b8-d0c671936c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805660311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2805660311
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3601277547
Short name T296
Test name
Test status
Simulation time 7294695556 ps
CPU time 90.04 seconds
Started May 26 12:54:28 PM PDT 24
Finished May 26 12:55:59 PM PDT 24
Peak memory 257040 kb
Host smart-55d3344d-cdd2-47ca-87e3-e60d5b0f86f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601277547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3601277547
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2478578997
Short name T259
Test name
Test status
Simulation time 42848043069 ps
CPU time 347.38 seconds
Started May 26 12:54:28 PM PDT 24
Finished May 26 01:00:16 PM PDT 24
Peak memory 256564 kb
Host smart-5002e579-a46f-4e62-992e-7b81b61a582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478578997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2478578997
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2957261530
Short name T599
Test name
Test status
Simulation time 2623489182 ps
CPU time 14.27 seconds
Started May 26 12:54:13 PM PDT 24
Finished May 26 12:54:28 PM PDT 24
Peak memory 235480 kb
Host smart-8142a427-dc83-45b7-84b6-377ffffd89ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957261530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2957261530
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3446598628
Short name T178
Test name
Test status
Simulation time 2904491224 ps
CPU time 15.26 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:32 PM PDT 24
Peak memory 234216 kb
Host smart-3c6bb4d4-6756-4bba-bc6b-c79eaa90dec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446598628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3446598628
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1437783913
Short name T287
Test name
Test status
Simulation time 4533788507 ps
CPU time 16.3 seconds
Started May 26 12:54:13 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 237508 kb
Host smart-1f686fe1-0348-41a0-901e-d47df6df9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437783913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1437783913
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.257421762
Short name T262
Test name
Test status
Simulation time 13199898684 ps
CPU time 12.57 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:29 PM PDT 24
Peak memory 237124 kb
Host smart-792b9a8c-41d4-4fe4-bd52-d01a1b656b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257421762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.257421762
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2542414290
Short name T609
Test name
Test status
Simulation time 1608669732 ps
CPU time 5.77 seconds
Started May 26 12:54:13 PM PDT 24
Finished May 26 12:54:20 PM PDT 24
Peak memory 218544 kb
Host smart-91f32cf6-18b8-4f7c-a47e-6a17056445d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542414290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2542414290
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1692153757
Short name T849
Test name
Test status
Simulation time 190927634 ps
CPU time 5.14 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:20 PM PDT 24
Peak memory 219504 kb
Host smart-36a11c68-f91e-4b67-880c-f5ad16735bfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692153757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1692153757
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1964342279
Short name T787
Test name
Test status
Simulation time 190908355 ps
CPU time 0.97 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:28 PM PDT 24
Peak memory 206676 kb
Host smart-ef8c0c64-bd9a-4428-938f-c7540ed60970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964342279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1964342279
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1979175829
Short name T644
Test name
Test status
Simulation time 3583512633 ps
CPU time 23.75 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 216112 kb
Host smart-e7b8ffb2-2373-440c-a228-ca01cbbb6df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979175829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1979175829
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3703714975
Short name T745
Test name
Test status
Simulation time 1191048657 ps
CPU time 6.9 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:22 PM PDT 24
Peak memory 216120 kb
Host smart-8efe36f7-84bf-4dfe-afb0-cb2e3f1cfc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703714975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3703714975
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.418995398
Short name T427
Test name
Test status
Simulation time 111737155 ps
CPU time 1.03 seconds
Started May 26 12:54:14 PM PDT 24
Finished May 26 12:54:16 PM PDT 24
Peak memory 207300 kb
Host smart-64297517-06b3-43aa-9294-62603cf8fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418995398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.418995398
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3054101404
Short name T532
Test name
Test status
Simulation time 13988780 ps
CPU time 0.7 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:16 PM PDT 24
Peak memory 205412 kb
Host smart-68aca97e-eb41-4b9b-9ca4-282f6a9f82d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054101404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3054101404
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.869243545
Short name T518
Test name
Test status
Simulation time 159237798 ps
CPU time 3.07 seconds
Started May 26 12:54:15 PM PDT 24
Finished May 26 12:54:19 PM PDT 24
Peak memory 218584 kb
Host smart-debb3c8f-6403-4f9d-9c5e-72ada5f0afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869243545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.869243545
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2680803730
Short name T662
Test name
Test status
Simulation time 13626264 ps
CPU time 0.72 seconds
Started May 26 12:54:28 PM PDT 24
Finished May 26 12:54:29 PM PDT 24
Peak memory 204580 kb
Host smart-ea00cc55-6d80-492d-98bc-4a7dbf115612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680803730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2680803730
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1205097419
Short name T497
Test name
Test status
Simulation time 72082871 ps
CPU time 3.14 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 219480 kb
Host smart-d757a023-d70b-4c16-8265-c3ed7c47df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205097419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1205097419
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.970566712
Short name T386
Test name
Test status
Simulation time 37485626 ps
CPU time 0.8 seconds
Started May 26 12:54:24 PM PDT 24
Finished May 26 12:54:25 PM PDT 24
Peak memory 206416 kb
Host smart-422bbe64-f50e-4fc6-99e0-5de4d3752e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970566712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.970566712
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3044314099
Short name T440
Test name
Test status
Simulation time 192026690588 ps
CPU time 215.99 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:58:02 PM PDT 24
Peak memory 248916 kb
Host smart-bcbc4554-65eb-4529-96d0-d0f59ce6fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044314099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3044314099
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3885703175
Short name T201
Test name
Test status
Simulation time 7982274172 ps
CPU time 103.38 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:56:09 PM PDT 24
Peak memory 262748 kb
Host smart-9b723955-da8d-41a8-9092-dd556269e2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885703175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3885703175
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2810996386
Short name T237
Test name
Test status
Simulation time 249302808022 ps
CPU time 368.77 seconds
Started May 26 12:54:27 PM PDT 24
Finished May 26 01:00:36 PM PDT 24
Peak memory 255100 kb
Host smart-2df300c6-68d0-4e9a-9776-2d598ef7fc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810996386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2810996386
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2785106525
Short name T330
Test name
Test status
Simulation time 272430911 ps
CPU time 8.01 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:33 PM PDT 24
Peak memory 224300 kb
Host smart-df96f993-53ce-402b-9181-0ce5bc337cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785106525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2785106525
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1773820482
Short name T758
Test name
Test status
Simulation time 2764746361 ps
CPU time 33.2 seconds
Started May 26 12:54:27 PM PDT 24
Finished May 26 12:55:01 PM PDT 24
Peak memory 219596 kb
Host smart-8c74c32a-5da8-4ca3-a3b2-bc77b8fee5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773820482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1773820482
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3094433772
Short name T820
Test name
Test status
Simulation time 1451399253 ps
CPU time 14.27 seconds
Started May 26 12:54:24 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 228312 kb
Host smart-f1b7a288-db53-41b0-9e14-828d3e481b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094433772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3094433772
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3845418694
Short name T655
Test name
Test status
Simulation time 42633050570 ps
CPU time 26.69 seconds
Started May 26 12:54:27 PM PDT 24
Finished May 26 12:54:55 PM PDT 24
Peak memory 237288 kb
Host smart-ba5de589-8494-4427-8fd5-96d639c97a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845418694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3845418694
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3879245051
Short name T278
Test name
Test status
Simulation time 556090781 ps
CPU time 4.03 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:31 PM PDT 24
Peak memory 233408 kb
Host smart-26bd6290-0be7-47b4-9eaa-d4c37172bb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879245051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3879245051
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.527280577
Short name T375
Test name
Test status
Simulation time 136751467 ps
CPU time 4.45 seconds
Started May 26 12:54:27 PM PDT 24
Finished May 26 12:54:32 PM PDT 24
Peak memory 222912 kb
Host smart-0a5a28ab-2e63-40fb-b85e-9439b7766b22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=527280577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.527280577
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3000316417
Short name T890
Test name
Test status
Simulation time 162338288 ps
CPU time 1.06 seconds
Started May 26 12:54:29 PM PDT 24
Finished May 26 12:54:31 PM PDT 24
Peak memory 207056 kb
Host smart-121a74c0-5ae4-4ef1-b3fe-dd7c1ff28027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000316417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3000316417
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1050732146
Short name T955
Test name
Test status
Simulation time 8802849368 ps
CPU time 47.74 seconds
Started May 26 12:54:27 PM PDT 24
Finished May 26 12:55:15 PM PDT 24
Peak memory 216044 kb
Host smart-93a46ad8-5d89-4c65-8a59-562020c36cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050732146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1050732146
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2391520359
Short name T396
Test name
Test status
Simulation time 2335487579 ps
CPU time 4.5 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 216012 kb
Host smart-17d322b1-d011-4ffd-b10a-6d8abeb93b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391520359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2391520359
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.463956215
Short name T838
Test name
Test status
Simulation time 12147454 ps
CPU time 0.76 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:27 PM PDT 24
Peak memory 205604 kb
Host smart-99fdf4a3-bf3a-4c58-b854-6c831a790eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463956215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.463956215
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2060020219
Short name T651
Test name
Test status
Simulation time 37313115 ps
CPU time 0.85 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:26 PM PDT 24
Peak memory 205612 kb
Host smart-40946648-fd92-4eff-b27f-e342aba68d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060020219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2060020219
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1454988842
Short name T832
Test name
Test status
Simulation time 2657221519 ps
CPU time 6.61 seconds
Started May 26 12:54:28 PM PDT 24
Finished May 26 12:54:35 PM PDT 24
Peak memory 234384 kb
Host smart-b5c244ba-f10b-4b0f-91a3-ca95909a8cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454988842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1454988842
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1719968899
Short name T588
Test name
Test status
Simulation time 51164544 ps
CPU time 0.7 seconds
Started May 26 12:54:37 PM PDT 24
Finished May 26 12:54:40 PM PDT 24
Peak memory 205396 kb
Host smart-1ea17f0c-0da1-42d9-989b-2d81f73e7d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719968899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1719968899
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.447818168
Short name T701
Test name
Test status
Simulation time 130718773 ps
CPU time 2.22 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:54:37 PM PDT 24
Peak memory 218768 kb
Host smart-cf98f46a-d5bd-4256-8bf5-49e30ccb2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447818168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.447818168
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.389301709
Short name T623
Test name
Test status
Simulation time 26331391 ps
CPU time 0.79 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:27 PM PDT 24
Peak memory 206268 kb
Host smart-00b279cb-9b35-4df4-8131-fae30bae1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389301709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.389301709
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3771171383
Short name T257
Test name
Test status
Simulation time 9130618122 ps
CPU time 115.46 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:56:31 PM PDT 24
Peak memory 240684 kb
Host smart-3edd7acd-b5b7-44f9-abf7-18b2d13be8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771171383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3771171383
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.801550133
Short name T863
Test name
Test status
Simulation time 6148890825 ps
CPU time 17.37 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:55:01 PM PDT 24
Peak memory 216992 kb
Host smart-6962dcfc-6004-4f7a-9c49-f1cad699f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801550133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.801550133
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2201402203
Short name T710
Test name
Test status
Simulation time 379655086 ps
CPU time 6.58 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:44 PM PDT 24
Peak memory 232588 kb
Host smart-c545c7f9-c559-4b6f-9346-cdef2baa00db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201402203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2201402203
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.156157315
Short name T285
Test name
Test status
Simulation time 5588902119 ps
CPU time 16.43 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:43 PM PDT 24
Peak memory 218408 kb
Host smart-ba543e98-a18d-4210-8336-95e2d4333483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156157315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.156157315
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2831558744
Short name T586
Test name
Test status
Simulation time 1018982897 ps
CPU time 15.49 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:43 PM PDT 24
Peak memory 227576 kb
Host smart-91737175-ea91-416e-b3ed-b8e9fed1765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831558744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2831558744
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2619296129
Short name T288
Test name
Test status
Simulation time 626783486 ps
CPU time 6.29 seconds
Started May 26 12:54:26 PM PDT 24
Finished May 26 12:54:33 PM PDT 24
Peak memory 233612 kb
Host smart-e51a3434-e6ea-4d1b-ae04-170d4fc8ec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619296129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2619296129
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.485209339
Short name T196
Test name
Test status
Simulation time 633425643 ps
CPU time 4.43 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:30 PM PDT 24
Peak memory 235072 kb
Host smart-9f20d360-88c2-430d-b323-c12427a48d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485209339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.485209339
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1814414263
Short name T373
Test name
Test status
Simulation time 411971645 ps
CPU time 3.72 seconds
Started May 26 12:54:37 PM PDT 24
Finished May 26 12:54:43 PM PDT 24
Peak memory 222712 kb
Host smart-940959b9-f727-4285-b0ed-490bd1aec901
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1814414263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1814414263
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.254857134
Short name T339
Test name
Test status
Simulation time 7088037469 ps
CPU time 43.98 seconds
Started May 26 12:54:29 PM PDT 24
Finished May 26 12:55:14 PM PDT 24
Peak memory 216300 kb
Host smart-2d754cdd-19da-407e-86e5-7b14e82db093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254857134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.254857134
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1352621
Short name T910
Test name
Test status
Simulation time 1324067257 ps
CPU time 3.55 seconds
Started May 26 12:54:29 PM PDT 24
Finished May 26 12:54:33 PM PDT 24
Peak memory 216092 kb
Host smart-503ac053-9e58-4061-8d8d-5c7d50c4ab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1352621
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2567028661
Short name T718
Test name
Test status
Simulation time 175311895 ps
CPU time 1.12 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:27 PM PDT 24
Peak memory 206992 kb
Host smart-c6cc717c-7f13-4cef-a59e-da5801422fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567028661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2567028661
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1146426630
Short name T903
Test name
Test status
Simulation time 106643243 ps
CPU time 0.85 seconds
Started May 26 12:54:25 PM PDT 24
Finished May 26 12:54:27 PM PDT 24
Peak memory 205484 kb
Host smart-4479039c-b4d0-46d5-b319-1be83278fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146426630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1146426630
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.312920379
Short name T862
Test name
Test status
Simulation time 2266826798 ps
CPU time 3.86 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:54:41 PM PDT 24
Peak memory 220024 kb
Host smart-ba85f86e-7f8b-4070-b454-662d7755117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312920379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.312920379
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1193420216
Short name T850
Test name
Test status
Simulation time 24207818 ps
CPU time 0.71 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 205372 kb
Host smart-9b8a8f81-dcf7-4ffa-87a6-e4840c91483d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193420216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1193420216
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2877715548
Short name T826
Test name
Test status
Simulation time 215984890 ps
CPU time 2.61 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:40 PM PDT 24
Peak memory 217580 kb
Host smart-bf34ec34-54d9-452b-95ce-1079469602c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877715548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2877715548
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1196112526
Short name T630
Test name
Test status
Simulation time 18299519 ps
CPU time 0.79 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:54:38 PM PDT 24
Peak memory 206400 kb
Host smart-a5429a44-aba3-48e3-978e-7f9ee222eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196112526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1196112526
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1688864481
Short name T770
Test name
Test status
Simulation time 2120608223 ps
CPU time 16 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:54:51 PM PDT 24
Peak memory 224360 kb
Host smart-e4db4d39-0f16-4532-86fd-c87ba97d6547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688864481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1688864481
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.410805519
Short name T164
Test name
Test status
Simulation time 63090196357 ps
CPU time 74.1 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:55:51 PM PDT 24
Peak memory 240536 kb
Host smart-4b2f2292-71a4-429d-9abe-6e1629bc7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410805519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.410805519
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2021916369
Short name T833
Test name
Test status
Simulation time 2703610143 ps
CPU time 17.58 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:54:54 PM PDT 24
Peak memory 224364 kb
Host smart-04be34ab-45f6-43a6-aef1-f9689603e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021916369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2021916369
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2426387241
Short name T346
Test name
Test status
Simulation time 31191080 ps
CPU time 2.05 seconds
Started May 26 12:54:37 PM PDT 24
Finished May 26 12:54:42 PM PDT 24
Peak memory 215956 kb
Host smart-8ec853c1-bc72-49c3-94e4-e5731851cbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426387241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2426387241
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1004267586
Short name T515
Test name
Test status
Simulation time 3858892451 ps
CPU time 49.12 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 233644 kb
Host smart-68b4fc80-1ff3-456a-b021-84765b446f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004267586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1004267586
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4066330009
Short name T258
Test name
Test status
Simulation time 3228933233 ps
CPU time 8.92 seconds
Started May 26 12:54:37 PM PDT 24
Finished May 26 12:54:48 PM PDT 24
Peak memory 233168 kb
Host smart-ded79080-fc06-4ec6-9da5-7421c7fca630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066330009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4066330009
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2494789717
Short name T937
Test name
Test status
Simulation time 6239493239 ps
CPU time 18.66 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:54:54 PM PDT 24
Peak memory 218740 kb
Host smart-fd0f05f3-61e7-4351-b613-a496a6911b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494789717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2494789717
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.228378097
Short name T739
Test name
Test status
Simulation time 544896392 ps
CPU time 7.02 seconds
Started May 26 12:54:37 PM PDT 24
Finished May 26 12:54:46 PM PDT 24
Peak memory 222820 kb
Host smart-6c6572b7-0c79-4963-85ce-d6653c2c12ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228378097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.228378097
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1204594906
Short name T60
Test name
Test status
Simulation time 54938086 ps
CPU time 1.16 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:54:46 PM PDT 24
Peak memory 206888 kb
Host smart-49f5566b-8dba-4a6f-8821-b7d901866f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204594906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1204594906
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.481305505
Short name T569
Test name
Test status
Simulation time 231210910 ps
CPU time 3.82 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:47 PM PDT 24
Peak memory 218516 kb
Host smart-18fe51cb-98a2-47ab-9dd8-334abbd8239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481305505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.481305505
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.35401411
Short name T765
Test name
Test status
Simulation time 977833226 ps
CPU time 5.58 seconds
Started May 26 12:54:33 PM PDT 24
Finished May 26 12:54:40 PM PDT 24
Peak memory 216012 kb
Host smart-ac84d177-acdf-46d6-a3ad-cf42e90bb852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35401411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.35401411
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2057310902
Short name T447
Test name
Test status
Simulation time 81982876 ps
CPU time 1 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 206964 kb
Host smart-c44c6b7a-ff4f-494a-9c64-39629aaa4a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057310902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2057310902
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3859682121
Short name T426
Test name
Test status
Simulation time 123201832 ps
CPU time 0.78 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:39 PM PDT 24
Peak memory 205476 kb
Host smart-aa155d85-193a-47d3-9f51-30a59695ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859682121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3859682121
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3629405864
Short name T193
Test name
Test status
Simulation time 7922678280 ps
CPU time 14.44 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:54:50 PM PDT 24
Peak memory 231420 kb
Host smart-d3d499c7-bd34-42ab-bd82-f32f1679cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629405864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3629405864
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3411843910
Short name T879
Test name
Test status
Simulation time 42602680 ps
CPU time 0.72 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:44 PM PDT 24
Peak memory 204796 kb
Host smart-ed846bb0-2de5-45de-a2e3-4db206892a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411843910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3411843910
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3534700909
Short name T88
Test name
Test status
Simulation time 891197866 ps
CPU time 5.11 seconds
Started May 26 12:54:44 PM PDT 24
Finished May 26 12:54:50 PM PDT 24
Peak memory 234752 kb
Host smart-f14220a2-78f8-48d0-951a-8c12877a396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534700909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3534700909
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2680466970
Short name T696
Test name
Test status
Simulation time 13869119 ps
CPU time 0.76 seconds
Started May 26 12:54:35 PM PDT 24
Finished May 26 12:54:37 PM PDT 24
Peak memory 205580 kb
Host smart-f3c5d008-a2c1-4c73-8a26-eb6445420eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680466970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2680466970
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1302826388
Short name T323
Test name
Test status
Simulation time 3960244197 ps
CPU time 86.35 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 250988 kb
Host smart-3f3746fa-003c-4e67-b39d-b2ecc73dc2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302826388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1302826388
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4003344535
Short name T234
Test name
Test status
Simulation time 37249129414 ps
CPU time 241.66 seconds
Started May 26 12:54:40 PM PDT 24
Finished May 26 12:58:44 PM PDT 24
Peak memory 249212 kb
Host smart-83a41b1c-2f26-4b54-b43a-c8c0dac7c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003344535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4003344535
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2903145448
Short name T254
Test name
Test status
Simulation time 42458419340 ps
CPU time 402.13 seconds
Started May 26 12:54:39 PM PDT 24
Finished May 26 01:01:24 PM PDT 24
Peak memory 252480 kb
Host smart-8cf843b9-fc53-4580-a533-fbdf928e22b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903145448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2903145448
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.258200068
Short name T445
Test name
Test status
Simulation time 162675199 ps
CPU time 4.49 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:54:49 PM PDT 24
Peak memory 224328 kb
Host smart-c1ba467f-c2d2-4f80-9dea-b8be0a66d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258200068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.258200068
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.711344982
Short name T91
Test name
Test status
Simulation time 453979172 ps
CPU time 7.96 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:54:52 PM PDT 24
Peak memory 233612 kb
Host smart-9b372d16-aebc-49a1-9968-8a3c43c9baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711344982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.711344982
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1425069451
Short name T932
Test name
Test status
Simulation time 552461304 ps
CPU time 8.88 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:53 PM PDT 24
Peak memory 219360 kb
Host smart-3f4ca049-0c1a-47a9-8cca-c27879e620cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425069451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1425069451
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2037090624
Short name T221
Test name
Test status
Simulation time 103620542 ps
CPU time 2.86 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:40 PM PDT 24
Peak memory 218580 kb
Host smart-b3287bb3-ad24-4218-8893-a76bf7b3a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037090624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2037090624
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.535505067
Short name T747
Test name
Test status
Simulation time 1505244575 ps
CPU time 6.16 seconds
Started May 26 12:54:44 PM PDT 24
Finished May 26 12:54:52 PM PDT 24
Peak memory 220004 kb
Host smart-2f583003-fe4f-49e0-b883-9bda39e774ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=535505067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.535505067
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2504720548
Short name T763
Test name
Test status
Simulation time 474681253 ps
CPU time 8.45 seconds
Started May 26 12:54:34 PM PDT 24
Finished May 26 12:54:44 PM PDT 24
Peak memory 216252 kb
Host smart-59c843cc-2b41-4744-8cab-7b42c7eacbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504720548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2504720548
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2029224183
Short name T82
Test name
Test status
Simulation time 1795417256 ps
CPU time 2.25 seconds
Started May 26 12:54:36 PM PDT 24
Finished May 26 12:54:41 PM PDT 24
Peak memory 207704 kb
Host smart-171bea63-1485-492f-97c2-590cf40e78d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029224183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2029224183
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2773467037
Short name T361
Test name
Test status
Simulation time 562304847 ps
CPU time 4.79 seconds
Started May 26 12:54:33 PM PDT 24
Finished May 26 12:54:38 PM PDT 24
Peak memory 216100 kb
Host smart-5a7b7e47-c636-45e7-9501-8be74e6b9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773467037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2773467037
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2789680850
Short name T435
Test name
Test status
Simulation time 133311842 ps
CPU time 0.95 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:45 PM PDT 24
Peak memory 205456 kb
Host smart-85da48fe-d754-4196-a94a-daaf0b3ff71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789680850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2789680850
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.366961783
Short name T896
Test name
Test status
Simulation time 34628775275 ps
CPU time 18.85 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:55:03 PM PDT 24
Peak memory 242392 kb
Host smart-0cab45ce-eaa3-4a7a-b067-e12033117079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366961783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.366961783
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4098155879
Short name T418
Test name
Test status
Simulation time 88079365 ps
CPU time 0.75 seconds
Started May 26 12:54:51 PM PDT 24
Finished May 26 12:54:53 PM PDT 24
Peak memory 205324 kb
Host smart-378b946f-300f-45e6-bf5f-0d9453884e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098155879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4098155879
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3341628975
Short name T749
Test name
Test status
Simulation time 3887295112 ps
CPU time 19.84 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:55:04 PM PDT 24
Peak memory 232568 kb
Host smart-84269a06-0de5-4fcd-90a2-ab7439b9b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341628975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3341628975
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3389458554
Short name T822
Test name
Test status
Simulation time 135574793 ps
CPU time 0.79 seconds
Started May 26 12:54:45 PM PDT 24
Finished May 26 12:54:47 PM PDT 24
Peak memory 206224 kb
Host smart-3eb07e05-a4a2-4343-8ac0-7048920a0183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389458554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3389458554
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1181728848
Short name T750
Test name
Test status
Simulation time 236928261455 ps
CPU time 133.75 seconds
Started May 26 12:54:43 PM PDT 24
Finished May 26 12:56:59 PM PDT 24
Peak memory 254400 kb
Host smart-b31dad82-3272-47c7-8621-426389a60bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181728848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1181728848
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.238003768
Short name T460
Test name
Test status
Simulation time 34731578302 ps
CPU time 96.5 seconds
Started May 26 12:54:40 PM PDT 24
Finished May 26 12:56:19 PM PDT 24
Peak memory 249040 kb
Host smart-ed0f3d5f-4bc1-4fdc-9446-831e6aaa56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238003768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.238003768
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1582608239
Short name T250
Test name
Test status
Simulation time 1122362057 ps
CPU time 26.22 seconds
Started May 26 12:54:43 PM PDT 24
Finished May 26 12:55:12 PM PDT 24
Peak memory 240668 kb
Host smart-31c85dcf-2011-47ad-894c-ad2febe50c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582608239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1582608239
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1693206713
Short name T53
Test name
Test status
Simulation time 9191243512 ps
CPU time 35.74 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:55:20 PM PDT 24
Peak memory 232808 kb
Host smart-ee6b3f49-a8c5-4563-beaf-e9539e541afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693206713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1693206713
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2410734002
Short name T310
Test name
Test status
Simulation time 688741985 ps
CPU time 10.72 seconds
Started May 26 12:54:42 PM PDT 24
Finished May 26 12:54:55 PM PDT 24
Peak memory 233408 kb
Host smart-a44f5483-65e4-453b-8869-32beecdd8c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410734002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2410734002
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.423256969
Short name T50
Test name
Test status
Simulation time 4234139294 ps
CPU time 8.27 seconds
Started May 26 12:54:40 PM PDT 24
Finished May 26 12:54:51 PM PDT 24
Peak memory 237680 kb
Host smart-f6bda12b-c0c6-4881-94de-8edaede94630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423256969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.423256969
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.543923928
Short name T629
Test name
Test status
Simulation time 20981752094 ps
CPU time 8.82 seconds
Started May 26 12:54:45 PM PDT 24
Finished May 26 12:54:56 PM PDT 24
Peak memory 218632 kb
Host smart-a350cca7-f532-4064-b876-8cdf2dbd0132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543923928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.543923928
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2588671669
Short name T195
Test name
Test status
Simulation time 1448161625 ps
CPU time 7.41 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:51 PM PDT 24
Peak memory 233920 kb
Host smart-656ee52b-18db-4249-b753-7d0cd11f1f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588671669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2588671669
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1001782342
Short name T736
Test name
Test status
Simulation time 1820567321 ps
CPU time 10.21 seconds
Started May 26 12:54:45 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 222780 kb
Host smart-ffdda98a-d7ec-47b9-a4db-e67591713ea5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1001782342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1001782342
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1370350268
Short name T722
Test name
Test status
Simulation time 18760690588 ps
CPU time 129.77 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:56:54 PM PDT 24
Peak memory 265316 kb
Host smart-2b9afbce-c3ff-4db9-ae06-6bc1c18528ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370350268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1370350268
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3054698319
Short name T383
Test name
Test status
Simulation time 1008412880 ps
CPU time 5.64 seconds
Started May 26 12:54:45 PM PDT 24
Finished May 26 12:54:52 PM PDT 24
Peak memory 216168 kb
Host smart-c332d0d7-c11e-4166-b94d-e6e9fd124014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054698319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3054698319
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3982189409
Short name T355
Test name
Test status
Simulation time 42670311 ps
CPU time 0.71 seconds
Started May 26 12:54:39 PM PDT 24
Finished May 26 12:54:42 PM PDT 24
Peak memory 205400 kb
Host smart-9579bd75-d338-429a-9704-844e6df3e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982189409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3982189409
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.262369519
Short name T466
Test name
Test status
Simulation time 255221132 ps
CPU time 5.99 seconds
Started May 26 12:54:46 PM PDT 24
Finished May 26 12:54:53 PM PDT 24
Peak memory 216100 kb
Host smart-643be546-5e08-4f76-8e84-68773154bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262369519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.262369519
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.901584528
Short name T430
Test name
Test status
Simulation time 166202648 ps
CPU time 0.83 seconds
Started May 26 12:54:43 PM PDT 24
Finished May 26 12:54:46 PM PDT 24
Peak memory 205560 kb
Host smart-e9a0ba19-cae7-4aa3-92be-5f67f99e7b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901584528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.901584528
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2156718103
Short name T294
Test name
Test status
Simulation time 460153341 ps
CPU time 6.76 seconds
Started May 26 12:54:41 PM PDT 24
Finished May 26 12:54:51 PM PDT 24
Peak memory 233440 kb
Host smart-61a0167d-4757-4f96-a5e4-796fc2303efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156718103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2156718103
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2505999861
Short name T348
Test name
Test status
Simulation time 19709669 ps
CPU time 0.71 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 205280 kb
Host smart-619da7f9-4d7e-42db-a41a-35c3efa57d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505999861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2505999861
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3854468077
Short name T471
Test name
Test status
Simulation time 617975579 ps
CPU time 7.28 seconds
Started May 26 12:54:52 PM PDT 24
Finished May 26 12:55:00 PM PDT 24
Peak memory 219508 kb
Host smart-b40a91a4-453a-4256-baeb-2411ef790b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854468077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3854468077
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4020362493
Short name T367
Test name
Test status
Simulation time 19991825 ps
CPU time 0.82 seconds
Started May 26 12:54:50 PM PDT 24
Finished May 26 12:54:52 PM PDT 24
Peak memory 206608 kb
Host smart-0bca678e-e327-42a3-9ddf-34ddc3fe49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020362493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4020362493
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2708784637
Short name T927
Test name
Test status
Simulation time 4006890795 ps
CPU time 15.94 seconds
Started May 26 12:54:50 PM PDT 24
Finished May 26 12:55:07 PM PDT 24
Peak memory 239856 kb
Host smart-ee7a4b55-d923-4a36-899b-8af3560a4722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708784637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2708784637
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.114752076
Short name T263
Test name
Test status
Simulation time 48188610267 ps
CPU time 122.76 seconds
Started May 26 12:54:52 PM PDT 24
Finished May 26 12:56:56 PM PDT 24
Peak memory 252768 kb
Host smart-0a7cbc1b-7318-4152-a4c2-f5940a31f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114752076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.114752076
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3179765119
Short name T302
Test name
Test status
Simulation time 51203857867 ps
CPU time 56.44 seconds
Started May 26 12:54:52 PM PDT 24
Finished May 26 12:55:50 PM PDT 24
Peak memory 235420 kb
Host smart-52de07de-21fa-47a1-b234-b28fb4eed653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179765119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3179765119
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2579004958
Short name T708
Test name
Test status
Simulation time 394570332 ps
CPU time 9.21 seconds
Started May 26 12:54:51 PM PDT 24
Finished May 26 12:55:02 PM PDT 24
Peak memory 233204 kb
Host smart-54a1f2a7-ae0d-4c5c-878a-ca9088d04d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579004958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2579004958
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.628758635
Short name T408
Test name
Test status
Simulation time 3182665558 ps
CPU time 8.48 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:55:04 PM PDT 24
Peak memory 232624 kb
Host smart-b3bd3f59-4998-4a3f-9818-6c7f9f86937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628758635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.628758635
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1889925646
Short name T76
Test name
Test status
Simulation time 76811597 ps
CPU time 2.45 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:54:58 PM PDT 24
Peak memory 218244 kb
Host smart-bd039a41-55e9-4f5f-9d0d-14e455484892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889925646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1889925646
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4091364110
Short name T306
Test name
Test status
Simulation time 1234234700 ps
CPU time 6.28 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:55:02 PM PDT 24
Peak memory 236084 kb
Host smart-4e3c0d87-3b28-498f-bb67-b8c9ae55956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091364110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4091364110
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2820134175
Short name T889
Test name
Test status
Simulation time 214525605 ps
CPU time 2.59 seconds
Started May 26 12:54:50 PM PDT 24
Finished May 26 12:54:54 PM PDT 24
Peak memory 218412 kb
Host smart-fa750826-0364-457f-a5c0-d4e5a3ffff40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820134175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2820134175
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3124901409
Short name T424
Test name
Test status
Simulation time 5373410273 ps
CPU time 10.47 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:55:07 PM PDT 24
Peak memory 219912 kb
Host smart-0022233d-a183-4ba8-bcbe-4ef3727c09ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3124901409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3124901409
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.214490127
Short name T260
Test name
Test status
Simulation time 20811708339 ps
CPU time 70.68 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:56:07 PM PDT 24
Peak memory 240772 kb
Host smart-c7385faf-db5f-40ca-aa64-22e7f07a58b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214490127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.214490127
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2789761885
Short name T22
Test name
Test status
Simulation time 1232796011 ps
CPU time 4.42 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:54:59 PM PDT 24
Peak memory 216272 kb
Host smart-bcd5daf1-d711-43ff-bbd9-a57006dfe620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789761885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2789761885
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.415027600
Short name T871
Test name
Test status
Simulation time 3910773290 ps
CPU time 11.09 seconds
Started May 26 12:54:53 PM PDT 24
Finished May 26 12:55:05 PM PDT 24
Peak memory 216072 kb
Host smart-f699fc28-e7ef-42d8-8b78-9704a0a53b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415027600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.415027600
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3960314984
Short name T864
Test name
Test status
Simulation time 1427607831 ps
CPU time 1.63 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 216044 kb
Host smart-1bcf3928-1641-4721-8c07-2f8693237a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960314984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3960314984
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2999360212
Short name T368
Test name
Test status
Simulation time 52356034 ps
CPU time 0.72 seconds
Started May 26 12:54:52 PM PDT 24
Finished May 26 12:54:54 PM PDT 24
Peak memory 205584 kb
Host smart-d6ca9572-4a26-4058-b6d2-7ef0fe999fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999360212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2999360212
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2837871530
Short name T457
Test name
Test status
Simulation time 41338249 ps
CPU time 2.78 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:54:58 PM PDT 24
Peak memory 224268 kb
Host smart-e80b741a-3b2a-45f7-9886-db610399f9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837871530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2837871530
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1815224666
Short name T452
Test name
Test status
Simulation time 33096026 ps
CPU time 0.71 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:55:09 PM PDT 24
Peak memory 205288 kb
Host smart-be638f70-e9a6-4ae8-9e6c-2a13bc711636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815224666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1815224666
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3280963361
Short name T698
Test name
Test status
Simulation time 95561519 ps
CPU time 3.86 seconds
Started May 26 12:55:08 PM PDT 24
Finished May 26 12:55:14 PM PDT 24
Peak memory 233924 kb
Host smart-e3202bc1-2c93-48ce-bac7-3f61c498ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280963361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3280963361
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3357706244
Short name T478
Test name
Test status
Simulation time 16466987 ps
CPU time 0.79 seconds
Started May 26 12:54:53 PM PDT 24
Finished May 26 12:54:55 PM PDT 24
Peak memory 206608 kb
Host smart-25e219e7-9046-42ba-a471-6f449056a634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357706244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3357706244
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3023273004
Short name T914
Test name
Test status
Simulation time 33573832867 ps
CPU time 175.26 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:58:04 PM PDT 24
Peak memory 250736 kb
Host smart-43671e34-fcec-48bc-b333-afe77fad97e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023273004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3023273004
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2424051953
Short name T24
Test name
Test status
Simulation time 59678419919 ps
CPU time 121.86 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:57:10 PM PDT 24
Peak memory 249016 kb
Host smart-c7c7f93a-b9af-4302-9664-9f021104e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424051953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2424051953
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3859344015
Short name T54
Test name
Test status
Simulation time 2222447352 ps
CPU time 44.08 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:55 PM PDT 24
Peak memory 232692 kb
Host smart-ba476acd-c5ad-402d-9541-d97d10f95bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859344015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3859344015
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1232377852
Short name T36
Test name
Test status
Simulation time 2872736433 ps
CPU time 26.83 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:55:35 PM PDT 24
Peak memory 232532 kb
Host smart-911b794d-0416-41e9-a046-92b68130273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232377852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1232377852
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.19695611
Short name T92
Test name
Test status
Simulation time 247387789 ps
CPU time 5.32 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:55:01 PM PDT 24
Peak memory 235288 kb
Host smart-2c1fd3b6-a5f0-4991-8f00-afc3fdc5a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19695611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.19695611
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3628567697
Short name T90
Test name
Test status
Simulation time 431728665 ps
CPU time 4.82 seconds
Started May 26 12:55:10 PM PDT 24
Finished May 26 12:55:17 PM PDT 24
Peak memory 233304 kb
Host smart-577fffed-ef49-4e75-a0ef-23c869a2696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628567697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3628567697
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1050932222
Short name T583
Test name
Test status
Simulation time 6852263433 ps
CPU time 18.94 seconds
Started May 26 12:54:52 PM PDT 24
Finished May 26 12:55:12 PM PDT 24
Peak memory 249080 kb
Host smart-1316b11d-5fd5-4b32-90a6-8f3155549509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050932222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1050932222
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2691736300
Short name T720
Test name
Test status
Simulation time 122852975 ps
CPU time 2.71 seconds
Started May 26 12:54:53 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 233112 kb
Host smart-73af7cea-b510-476c-8de8-6d5fb352f9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691736300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2691736300
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.456234473
Short name T411
Test name
Test status
Simulation time 928994939 ps
CPU time 4.64 seconds
Started May 26 12:55:08 PM PDT 24
Finished May 26 12:55:15 PM PDT 24
Peak memory 220484 kb
Host smart-ad9ee27d-5860-4641-8d84-b4b5e2bc954c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=456234473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.456234473
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.127159077
Short name T598
Test name
Test status
Simulation time 17774816430 ps
CPU time 208.79 seconds
Started May 26 12:55:08 PM PDT 24
Finished May 26 12:58:39 PM PDT 24
Peak memory 263588 kb
Host smart-a655b5aa-7f82-4c1d-b118-983932de5dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127159077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.127159077
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2273592690
Short name T633
Test name
Test status
Simulation time 44646026 ps
CPU time 0.69 seconds
Started May 26 12:54:51 PM PDT 24
Finished May 26 12:54:53 PM PDT 24
Peak memory 205440 kb
Host smart-1eccbf18-1054-4e08-9c2a-aae6a3d6bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273592690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2273592690
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1107676389
Short name T848
Test name
Test status
Simulation time 6982357262 ps
CPU time 6.43 seconds
Started May 26 12:54:51 PM PDT 24
Finished May 26 12:54:59 PM PDT 24
Peak memory 216020 kb
Host smart-7a5828f4-9d53-49fc-b74c-b8f9ed41b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107676389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1107676389
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.970150818
Short name T548
Test name
Test status
Simulation time 1020667061 ps
CPU time 1.75 seconds
Started May 26 12:54:55 PM PDT 24
Finished May 26 12:54:58 PM PDT 24
Peak memory 216056 kb
Host smart-ecf5238d-0570-487c-8f81-b39e3c97125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970150818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.970150818
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.798474185
Short name T893
Test name
Test status
Simulation time 52042336 ps
CPU time 0.88 seconds
Started May 26 12:54:54 PM PDT 24
Finished May 26 12:54:57 PM PDT 24
Peak memory 205824 kb
Host smart-0ed1f61c-d455-4802-a18b-266de4e6a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798474185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.798474185
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3653498553
Short name T476
Test name
Test status
Simulation time 338013488 ps
CPU time 4.19 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:16 PM PDT 24
Peak memory 233856 kb
Host smart-cf65eaa0-1b1e-4ce8-b7a1-a5b398c7bf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653498553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3653498553
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.9207690
Short name T587
Test name
Test status
Simulation time 32888420 ps
CPU time 0.73 seconds
Started May 26 12:52:14 PM PDT 24
Finished May 26 12:52:15 PM PDT 24
Peak memory 204620 kb
Host smart-f81f1ab0-46f3-4eec-b7df-cb28842454a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9207690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.9207690
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3480381636
Short name T840
Test name
Test status
Simulation time 1414573646 ps
CPU time 13.1 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:21 PM PDT 24
Peak memory 233240 kb
Host smart-84145e0a-9683-48cc-9af1-52df44e540be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480381636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3480381636
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2289274070
Short name T828
Test name
Test status
Simulation time 114678872 ps
CPU time 0.75 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:08 PM PDT 24
Peak memory 205292 kb
Host smart-09ccb937-d712-4c21-8ab0-651ebb2b8279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289274070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2289274070
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.530570264
Short name T321
Test name
Test status
Simulation time 6274302468 ps
CPU time 6.97 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:15 PM PDT 24
Peak memory 233576 kb
Host smart-0e4896b3-504c-4602-99c8-be742f2958de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530570264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.530570264
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3950145740
Short name T939
Test name
Test status
Simulation time 175599885585 ps
CPU time 153.29 seconds
Started May 26 12:52:08 PM PDT 24
Finished May 26 12:54:42 PM PDT 24
Peak memory 255772 kb
Host smart-05bbccc6-650c-462c-ae3d-36653cbffa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950145740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3950145740
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2608571720
Short name T415
Test name
Test status
Simulation time 24007939534 ps
CPU time 86.13 seconds
Started May 26 12:52:14 PM PDT 24
Finished May 26 12:53:41 PM PDT 24
Peak memory 249408 kb
Host smart-900fc3a6-3095-4b7d-8143-25da86e73af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608571720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2608571720
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2150666963
Short name T308
Test name
Test status
Simulation time 1462398592 ps
CPU time 6.7 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:15 PM PDT 24
Peak memory 248988 kb
Host smart-24935764-ea0b-4197-97cd-d935ae9d2a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150666963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2150666963
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1629679868
Short name T870
Test name
Test status
Simulation time 126944364 ps
CPU time 3.73 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:10 PM PDT 24
Peak memory 232880 kb
Host smart-5cbba9a4-bb3a-40ed-9142-7d7e43020342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629679868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1629679868
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.977356027
Short name T704
Test name
Test status
Simulation time 5315470780 ps
CPU time 9.52 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:16 PM PDT 24
Peak memory 236148 kb
Host smart-5be4f481-a8e4-4cd4-b3ee-c20d9e8869d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977356027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.977356027
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2574978083
Short name T207
Test name
Test status
Simulation time 4804453396 ps
CPU time 6.53 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:14 PM PDT 24
Peak memory 233692 kb
Host smart-86a19d16-cd59-47c9-9f0c-a493881890fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574978083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2574978083
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3839582576
Short name T197
Test name
Test status
Simulation time 1684364091 ps
CPU time 2.59 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:10 PM PDT 24
Peak memory 216536 kb
Host smart-50148fc3-1c49-407f-aaae-fb49890b47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839582576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3839582576
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.489645163
Short name T906
Test name
Test status
Simulation time 550648038 ps
CPU time 4.74 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:12 PM PDT 24
Peak memory 222612 kb
Host smart-0bd31ae6-eaa8-4cf9-ad60-a9d076d19672
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=489645163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.489645163
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1035902511
Short name T67
Test name
Test status
Simulation time 232589722 ps
CPU time 1.09 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:52:18 PM PDT 24
Peak memory 235020 kb
Host smart-626969ad-a250-4af2-921c-bff0b64255d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035902511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1035902511
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.903796795
Short name T873
Test name
Test status
Simulation time 61179086 ps
CPU time 0.74 seconds
Started May 26 12:52:04 PM PDT 24
Finished May 26 12:52:06 PM PDT 24
Peak memory 205700 kb
Host smart-2b790cc1-598e-466f-a35b-26e65a80a47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903796795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.903796795
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.104801051
Short name T813
Test name
Test status
Simulation time 2139946854 ps
CPU time 6.72 seconds
Started May 26 12:52:08 PM PDT 24
Finished May 26 12:52:16 PM PDT 24
Peak memory 216044 kb
Host smart-a7bcb7fa-635a-4d99-bf0d-01766c3ed1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104801051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.104801051
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1357772647
Short name T481
Test name
Test status
Simulation time 36595627 ps
CPU time 0.72 seconds
Started May 26 12:52:07 PM PDT 24
Finished May 26 12:52:09 PM PDT 24
Peak memory 205360 kb
Host smart-213a8461-9b4a-4513-9bc4-5a8cce3f289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357772647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1357772647
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.798473242
Short name T370
Test name
Test status
Simulation time 16789997 ps
CPU time 0.7 seconds
Started May 26 12:52:06 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 205564 kb
Host smart-8a2464ec-19a7-4d40-8a9e-ff6a13aa335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798473242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.798473242
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1028990657
Short name T887
Test name
Test status
Simulation time 1460814661 ps
CPU time 10.87 seconds
Started May 26 12:52:08 PM PDT 24
Finished May 26 12:52:20 PM PDT 24
Peak memory 238716 kb
Host smart-fadce3e5-0868-4966-9f22-9cd73519a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028990657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1028990657
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.845385563
Short name T677
Test name
Test status
Simulation time 26630135 ps
CPU time 0.76 seconds
Started May 26 12:55:15 PM PDT 24
Finished May 26 12:55:18 PM PDT 24
Peak memory 204708 kb
Host smart-5c684950-7346-407b-9ff7-f418a2503432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845385563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.845385563
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3583738534
Short name T559
Test name
Test status
Simulation time 97938612 ps
CPU time 2.31 seconds
Started May 26 12:55:06 PM PDT 24
Finished May 26 12:55:10 PM PDT 24
Peak memory 221284 kb
Host smart-cad5dda7-3da6-4873-a09c-12d0e3907b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583738534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3583738534
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2493027956
Short name T783
Test name
Test status
Simulation time 50746881 ps
CPU time 0.76 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:13 PM PDT 24
Peak memory 205592 kb
Host smart-3ddc554b-9c31-447d-849b-6e0e71c22585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493027956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2493027956
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1231210367
Short name T794
Test name
Test status
Simulation time 105463133276 ps
CPU time 74.35 seconds
Started May 26 12:55:10 PM PDT 24
Finished May 26 12:56:27 PM PDT 24
Peak memory 248932 kb
Host smart-4f9723fa-dfa2-4f18-a2d3-5cbf4c69b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231210367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1231210367
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1636528288
Short name T780
Test name
Test status
Simulation time 8472159633 ps
CPU time 106.22 seconds
Started May 26 12:55:10 PM PDT 24
Finished May 26 12:56:59 PM PDT 24
Peak memory 267184 kb
Host smart-04f6cf67-4d7c-4e6d-8042-2e80f649f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636528288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1636528288
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2353920154
Short name T919
Test name
Test status
Simulation time 34270868661 ps
CPU time 150.91 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:57:42 PM PDT 24
Peak memory 249340 kb
Host smart-bc308f70-5891-47f9-83b2-eb346ba9f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353920154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2353920154
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1298368475
Short name T329
Test name
Test status
Simulation time 158972369 ps
CPU time 8.86 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:55:17 PM PDT 24
Peak memory 240808 kb
Host smart-9b2fb9b5-014c-4034-a7d0-706d4ce796c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298368475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1298368475
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3267286643
Short name T413
Test name
Test status
Simulation time 145866651 ps
CPU time 2.79 seconds
Started May 26 12:55:07 PM PDT 24
Finished May 26 12:55:11 PM PDT 24
Peak memory 224268 kb
Host smart-e2b6e11a-587a-4b9d-bca8-7f461fd785cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267286643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3267286643
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3170701676
Short name T591
Test name
Test status
Simulation time 544864823 ps
CPU time 13.95 seconds
Started May 26 12:55:08 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 220420 kb
Host smart-4734fda6-caaa-40af-a6f5-25c708bca2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170701676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3170701676
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1772948670
Short name T723
Test name
Test status
Simulation time 222382320 ps
CPU time 3.96 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:16 PM PDT 24
Peak memory 233696 kb
Host smart-7bf36c88-41d7-4eb6-a8f8-ad5fbe6c523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772948670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1772948670
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.539924280
Short name T653
Test name
Test status
Simulation time 77267360 ps
CPU time 2.18 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:14 PM PDT 24
Peak memory 215840 kb
Host smart-1c53d9b3-0718-442d-bc57-e0bbc399a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539924280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.539924280
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1659887717
Short name T139
Test name
Test status
Simulation time 841141421 ps
CPU time 7.56 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:18 PM PDT 24
Peak memory 221868 kb
Host smart-3a32d937-104c-42a1-8b4c-06340d2e69c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1659887717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1659887717
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3481348724
Short name T382
Test name
Test status
Simulation time 88588951 ps
CPU time 1.13 seconds
Started May 26 12:55:06 PM PDT 24
Finished May 26 12:55:08 PM PDT 24
Peak memory 206972 kb
Host smart-452b176c-9838-4912-acc3-2e68ad20b4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481348724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3481348724
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1170489838
Short name T480
Test name
Test status
Simulation time 1643694943 ps
CPU time 6.85 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:18 PM PDT 24
Peak memory 216104 kb
Host smart-718820f8-ec2d-4204-a832-e97e9d5922e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170489838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1170489838
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3379526064
Short name T479
Test name
Test status
Simulation time 834576187 ps
CPU time 5.43 seconds
Started May 26 12:55:10 PM PDT 24
Finished May 26 12:55:18 PM PDT 24
Peak memory 216036 kb
Host smart-2722f173-340f-4b28-9a86-ad1448e8021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379526064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3379526064
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1940172591
Short name T622
Test name
Test status
Simulation time 32345732 ps
CPU time 0.68 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:11 PM PDT 24
Peak memory 205444 kb
Host smart-865a17cc-a3d2-4629-ae2f-45e205cdc81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940172591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1940172591
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2159824685
Short name T624
Test name
Test status
Simulation time 17164030 ps
CPU time 0.72 seconds
Started May 26 12:55:09 PM PDT 24
Finished May 26 12:55:12 PM PDT 24
Peak memory 205524 kb
Host smart-4b3301b5-d1d1-4a10-a485-511f1218f644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159824685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2159824685
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3587924605
Short name T611
Test name
Test status
Simulation time 12760513789 ps
CPU time 16.98 seconds
Started May 26 12:55:06 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 238708 kb
Host smart-37032dc1-d17f-49df-a3da-7fa29b9d3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587924605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3587924605
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1370003815
Short name T562
Test name
Test status
Simulation time 160353849 ps
CPU time 0.82 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 204656 kb
Host smart-a4674e0d-5d59-495e-8d9c-14750744398c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370003815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1370003815
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.14033765
Short name T904
Test name
Test status
Simulation time 252962174 ps
CPU time 2.2 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 218636 kb
Host smart-81e6e531-4ecc-43cd-b7b3-08be3baeccc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14033765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.14033765
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3704217933
Short name T579
Test name
Test status
Simulation time 58776062 ps
CPU time 0.84 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 206316 kb
Host smart-12de608e-430c-4580-9e28-4d948ddadc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704217933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3704217933
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2730316232
Short name T773
Test name
Test status
Simulation time 21328667325 ps
CPU time 48.24 seconds
Started May 26 12:55:16 PM PDT 24
Finished May 26 12:56:07 PM PDT 24
Peak memory 240732 kb
Host smart-8765556a-d56a-4698-8768-3acb087bd58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730316232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2730316232
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3452295490
Short name T895
Test name
Test status
Simulation time 3565177173 ps
CPU time 73.32 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 249020 kb
Host smart-ef11ad75-ee56-4932-893a-0475bb5e902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452295490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3452295490
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1976177001
Short name T38
Test name
Test status
Simulation time 32125572984 ps
CPU time 27.45 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 233552 kb
Host smart-5776cb1f-cc6f-4c00-abd2-1313d64916c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976177001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1976177001
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3352477756
Short name T179
Test name
Test status
Simulation time 2487639184 ps
CPU time 10.41 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:34 PM PDT 24
Peak memory 235092 kb
Host smart-9435eb47-55b5-4439-a674-a39b70ae2d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352477756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3352477756
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1777185133
Short name T228
Test name
Test status
Simulation time 913477040 ps
CPU time 6.01 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:29 PM PDT 24
Peak memory 222920 kb
Host smart-0275bab0-5c4c-4925-864e-faf7737aa507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777185133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1777185133
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2550114559
Short name T432
Test name
Test status
Simulation time 2573275050 ps
CPU time 8.83 seconds
Started May 26 12:55:21 PM PDT 24
Finished May 26 12:55:33 PM PDT 24
Peak memory 237228 kb
Host smart-72d3ef18-3a9b-498d-86b7-4b9cc8173cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550114559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2550114559
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3050749365
Short name T954
Test name
Test status
Simulation time 3257519016 ps
CPU time 13.74 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:55:33 PM PDT 24
Peak memory 227928 kb
Host smart-24350646-c9cb-4a46-8620-94d66d921afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050749365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3050749365
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2822641128
Short name T535
Test name
Test status
Simulation time 423834572 ps
CPU time 5.59 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:28 PM PDT 24
Peak memory 222776 kb
Host smart-81fd9e41-015b-4079-adfb-a3e054e15b89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2822641128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2822641128
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1481165051
Short name T940
Test name
Test status
Simulation time 25815115757 ps
CPU time 32.76 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:57 PM PDT 24
Peak memory 222772 kb
Host smart-633ad8fb-89aa-4259-b384-908fa77bfbd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481165051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1481165051
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.339198787
Short name T1
Test name
Test status
Simulation time 3581016412 ps
CPU time 22.37 seconds
Started May 26 12:55:16 PM PDT 24
Finished May 26 12:55:42 PM PDT 24
Peak memory 216232 kb
Host smart-7b97b6a8-0c2f-4a42-a049-09f623b93af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339198787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.339198787
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3998785830
Short name T943
Test name
Test status
Simulation time 4700339584 ps
CPU time 7.41 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:55:28 PM PDT 24
Peak memory 216092 kb
Host smart-c368f19e-3861-4bc5-8753-857d7cbe385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998785830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3998785830
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2065274521
Short name T554
Test name
Test status
Simulation time 66499741 ps
CPU time 0.81 seconds
Started May 26 12:55:21 PM PDT 24
Finished May 26 12:55:25 PM PDT 24
Peak memory 205576 kb
Host smart-715b414a-d7d4-4b45-b1e9-528691bd2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065274521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2065274521
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2258778892
Short name T824
Test name
Test status
Simulation time 395356424 ps
CPU time 0.87 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 205524 kb
Host smart-3b4d612a-f4e7-4e5d-b82a-0350578a21c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258778892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2258778892
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2065333641
Short name T678
Test name
Test status
Simulation time 202106542 ps
CPU time 2.71 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 216024 kb
Host smart-a7e7f5fa-bb2f-439e-b620-de3bba42b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065333641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2065333641
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1921600250
Short name T729
Test name
Test status
Simulation time 17263964 ps
CPU time 0.75 seconds
Started May 26 12:55:21 PM PDT 24
Finished May 26 12:55:25 PM PDT 24
Peak memory 204676 kb
Host smart-1e7d869f-0aef-49ca-98a2-5f353dd9f576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921600250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1921600250
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3266848485
Short name T385
Test name
Test status
Simulation time 53941133 ps
CPU time 2.48 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 233456 kb
Host smart-23660b3a-ccad-410c-b7ed-471a4b2a9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266848485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3266848485
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2980409983
Short name T631
Test name
Test status
Simulation time 16946754 ps
CPU time 0.82 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:55:21 PM PDT 24
Peak memory 206316 kb
Host smart-f45fc788-df53-4698-bfcc-a74972119b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980409983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2980409983
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1934458587
Short name T488
Test name
Test status
Simulation time 5239429297 ps
CPU time 42.71 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 256180 kb
Host smart-2d65413b-06d6-4f0c-a298-53386e7b0bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934458587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1934458587
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1624635203
Short name T192
Test name
Test status
Simulation time 7286808043 ps
CPU time 54.13 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:56:17 PM PDT 24
Peak memory 248992 kb
Host smart-55915dee-5bed-4c75-be3b-3606516acb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624635203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1624635203
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1390970883
Short name T854
Test name
Test status
Simulation time 3507842211 ps
CPU time 10.23 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:34 PM PDT 24
Peak memory 248928 kb
Host smart-964e5426-7968-40f6-88cd-ca21f757c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390970883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1390970883
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2909970918
Short name T799
Test name
Test status
Simulation time 245907892 ps
CPU time 2.33 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:25 PM PDT 24
Peak memory 232488 kb
Host smart-81deff97-47aa-46b2-a199-bd55c0fe8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909970918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2909970918
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3766833710
Short name T475
Test name
Test status
Simulation time 238631201 ps
CPU time 5.78 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:28 PM PDT 24
Peak memory 218228 kb
Host smart-1f459b8e-17e8-484a-b4a7-784b4eaa8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766833710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3766833710
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2952374539
Short name T894
Test name
Test status
Simulation time 4517058735 ps
CPU time 9.12 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:33 PM PDT 24
Peak memory 233480 kb
Host smart-861e0b7a-331f-48d8-a70d-80553314b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952374539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2952374539
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1691360956
Short name T98
Test name
Test status
Simulation time 860252385 ps
CPU time 6.85 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:29 PM PDT 24
Peak memory 219212 kb
Host smart-e068ed13-99ad-4318-8c7e-f8c984b0e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691360956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1691360956
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4231980891
Short name T669
Test name
Test status
Simulation time 8871437809 ps
CPU time 12.75 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:55:33 PM PDT 24
Peak memory 220164 kb
Host smart-5cb44c48-ce04-403a-822b-b30e1cc33c04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4231980891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4231980891
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4071681312
Short name T233
Test name
Test status
Simulation time 101562602778 ps
CPU time 156.72 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:57:58 PM PDT 24
Peak memory 248932 kb
Host smart-59211dd3-e112-4fc2-a765-1d076cd000a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071681312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4071681312
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2940619333
Short name T567
Test name
Test status
Simulation time 3358667567 ps
CPU time 25.73 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 216504 kb
Host smart-cbd2ad48-4fc9-4225-acc9-0bff67502a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940619333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2940619333
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2535345130
Short name T462
Test name
Test status
Simulation time 6934177485 ps
CPU time 20.09 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:44 PM PDT 24
Peak memory 216044 kb
Host smart-b150b91f-3845-49b0-a5bb-a86ade2c92b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535345130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2535345130
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1317977795
Short name T514
Test name
Test status
Simulation time 218082395 ps
CPU time 1.28 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:22 PM PDT 24
Peak memory 215864 kb
Host smart-b531ec9d-3e68-445d-9fba-bd1b0bc59716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317977795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1317977795
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1349740501
Short name T390
Test name
Test status
Simulation time 128072969 ps
CPU time 0.85 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:22 PM PDT 24
Peak memory 206576 kb
Host smart-b7ee573b-7e71-4344-ae66-fbe82e2fa1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349740501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1349740501
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1372992529
Short name T226
Test name
Test status
Simulation time 618407258 ps
CPU time 2.84 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 217120 kb
Host smart-677a1caf-c3e7-4ff6-951a-7eba9cc88577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372992529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1372992529
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2718011128
Short name T564
Test name
Test status
Simulation time 48255917 ps
CPU time 0.71 seconds
Started May 26 12:55:27 PM PDT 24
Finished May 26 12:55:31 PM PDT 24
Peak memory 205376 kb
Host smart-544bd04a-42ea-49dc-a47c-bf843f9c7e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718011128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2718011128
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.752193239
Short name T945
Test name
Test status
Simulation time 254351304 ps
CPU time 3.75 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 219828 kb
Host smart-a0dfd14e-beae-4052-ad73-e4cfdb4021ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752193239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.752193239
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2467082993
Short name T843
Test name
Test status
Simulation time 41793979 ps
CPU time 0.79 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 205600 kb
Host smart-f2ba7724-cff9-4337-ad94-42c74155d314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467082993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2467082993
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1435916313
Short name T78
Test name
Test status
Simulation time 17888785733 ps
CPU time 154.71 seconds
Started May 26 12:55:29 PM PDT 24
Finished May 26 12:58:06 PM PDT 24
Peak memory 262460 kb
Host smart-cd541f7c-db65-4ff6-9bf5-25ac2d9da305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435916313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1435916313
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3810372538
Short name T732
Test name
Test status
Simulation time 9062980438 ps
CPU time 34.71 seconds
Started May 26 12:55:28 PM PDT 24
Finished May 26 12:56:05 PM PDT 24
Peak memory 239292 kb
Host smart-2463fc5e-46e9-4f97-a7ff-2ee46f2ad921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810372538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3810372538
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2505198003
Short name T600
Test name
Test status
Simulation time 241483247 ps
CPU time 2.42 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:25 PM PDT 24
Peak memory 224340 kb
Host smart-8c2e557a-c970-4537-b13d-ff63d4660699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505198003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2505198003
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2071239940
Short name T403
Test name
Test status
Simulation time 1314227724 ps
CPU time 5.92 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:30 PM PDT 24
Peak memory 233920 kb
Host smart-ddf5c7a8-1b69-43a5-b445-832f1902bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071239940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2071239940
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3106609004
Short name T900
Test name
Test status
Simulation time 39818694 ps
CPU time 2.24 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:26 PM PDT 24
Peak memory 224324 kb
Host smart-6d9e7062-be0d-4ce5-9403-7de71cda5c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106609004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3106609004
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3624939002
Short name T320
Test name
Test status
Simulation time 6473029299 ps
CPU time 6.44 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:30 PM PDT 24
Peak memory 236968 kb
Host smart-403f052a-d319-41d3-b829-bed739d978b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624939002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3624939002
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.372906405
Short name T670
Test name
Test status
Simulation time 1802727947 ps
CPU time 9.73 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:32 PM PDT 24
Peak memory 239228 kb
Host smart-5bb85885-57c8-4e54-9f26-4d9be4d33a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372906405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.372906405
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3585817734
Short name T776
Test name
Test status
Simulation time 176572663 ps
CPU time 3.79 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:55:32 PM PDT 24
Peak memory 219776 kb
Host smart-752c0bcc-468a-4713-aba2-5f66374d0416
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585817734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3585817734
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.698487907
Short name T344
Test name
Test status
Simulation time 4875602952 ps
CPU time 30.31 seconds
Started May 26 12:55:18 PM PDT 24
Finished May 26 12:55:52 PM PDT 24
Peak memory 216228 kb
Host smart-5dce88bb-28fe-4b01-8286-d2000f498c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698487907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.698487907
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2185066718
Short name T867
Test name
Test status
Simulation time 156210876 ps
CPU time 1.06 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 206728 kb
Host smart-ff4d4a44-874c-4546-9761-31f8cb5b473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185066718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2185066718
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2442872612
Short name T16
Test name
Test status
Simulation time 49606475 ps
CPU time 1.05 seconds
Started May 26 12:55:19 PM PDT 24
Finished May 26 12:55:24 PM PDT 24
Peak memory 206828 kb
Host smart-6cb8e5d6-ab07-48ec-9e31-33ad5f24989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442872612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2442872612
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1839479002
Short name T362
Test name
Test status
Simulation time 10781769 ps
CPU time 0.74 seconds
Started May 26 12:55:17 PM PDT 24
Finished May 26 12:55:20 PM PDT 24
Peak memory 205324 kb
Host smart-ca1de948-7d8b-4e55-bfe5-81aa47062f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839479002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1839479002
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.403547366
Short name T686
Test name
Test status
Simulation time 81221974724 ps
CPU time 24.36 seconds
Started May 26 12:55:20 PM PDT 24
Finished May 26 12:55:48 PM PDT 24
Peak memory 233896 kb
Host smart-a2eb3cd5-75f7-4dfd-904b-ba41e615c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403547366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.403547366
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3085997832
Short name T814
Test name
Test status
Simulation time 43087996 ps
CPU time 0.72 seconds
Started May 26 12:55:23 PM PDT 24
Finished May 26 12:55:28 PM PDT 24
Peak memory 205380 kb
Host smart-8ed5c842-23b6-4fea-9237-13ccdde8b028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085997832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3085997832
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1367873999
Short name T203
Test name
Test status
Simulation time 20426144523 ps
CPU time 20.39 seconds
Started May 26 12:55:26 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 234576 kb
Host smart-d5ab834b-bf65-4195-977c-ccd5c5a50de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367873999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1367873999
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1979915320
Short name T558
Test name
Test status
Simulation time 15435689 ps
CPU time 0.79 seconds
Started May 26 12:55:26 PM PDT 24
Finished May 26 12:55:30 PM PDT 24
Peak memory 206652 kb
Host smart-cfa446a3-315a-4079-ba17-dad6e50a20b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979915320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1979915320
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3734721357
Short name T303
Test name
Test status
Simulation time 113153992942 ps
CPU time 136.31 seconds
Started May 26 12:55:27 PM PDT 24
Finished May 26 12:57:46 PM PDT 24
Peak memory 250852 kb
Host smart-3558d194-2bc7-4d9c-91c1-a2934cb8a1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734721357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3734721357
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1514821527
Short name T946
Test name
Test status
Simulation time 5814413568 ps
CPU time 31.67 seconds
Started May 26 12:55:29 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 248012 kb
Host smart-21c6eeca-680f-4249-a75b-52acf3b51237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514821527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1514821527
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4095501922
Short name T603
Test name
Test status
Simulation time 8272362873 ps
CPU time 7.71 seconds
Started May 26 12:55:28 PM PDT 24
Finished May 26 12:55:38 PM PDT 24
Peak memory 218500 kb
Host smart-bd0c7e4e-77b9-4274-b82f-d118d903d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095501922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4095501922
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4232505537
Short name T654
Test name
Test status
Simulation time 2106732836 ps
CPU time 18.6 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:55 PM PDT 24
Peak memory 219308 kb
Host smart-4a4f9302-ff83-42d5-b000-5b4702dfb943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232505537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4232505537
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1046567279
Short name T322
Test name
Test status
Simulation time 436420221 ps
CPU time 6.49 seconds
Started May 26 12:55:26 PM PDT 24
Finished May 26 12:55:35 PM PDT 24
Peak memory 237468 kb
Host smart-559c9a05-a683-4ec9-b0f2-bb480693723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046567279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1046567279
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2642265605
Short name T679
Test name
Test status
Simulation time 894508474 ps
CPU time 6.8 seconds
Started May 26 12:55:27 PM PDT 24
Finished May 26 12:55:36 PM PDT 24
Peak memory 238744 kb
Host smart-8e3b054d-650c-4c93-93eb-3b6aeaec476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642265605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2642265605
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3075450152
Short name T648
Test name
Test status
Simulation time 455991391 ps
CPU time 4.7 seconds
Started May 26 12:55:27 PM PDT 24
Finished May 26 12:55:35 PM PDT 24
Peak memory 222008 kb
Host smart-48972a72-552e-4551-9a52-80d66444391a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075450152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3075450152
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1390238173
Short name T888
Test name
Test status
Simulation time 367922235 ps
CPU time 0.94 seconds
Started May 26 12:55:27 PM PDT 24
Finished May 26 12:55:30 PM PDT 24
Peak memory 206304 kb
Host smart-e8d8c896-0dc5-49f1-a7a0-2904d81ca9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390238173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1390238173
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.913327134
Short name T797
Test name
Test status
Simulation time 2355916818 ps
CPU time 36.14 seconds
Started May 26 12:55:24 PM PDT 24
Finished May 26 12:56:04 PM PDT 24
Peak memory 216472 kb
Host smart-7cecde66-49d1-4e8d-8585-704522d576ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913327134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.913327134
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3306594681
Short name T909
Test name
Test status
Simulation time 16035033226 ps
CPU time 11.09 seconds
Started May 26 12:55:29 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 216060 kb
Host smart-769d2567-c9ec-4ba2-8bcf-64469a6b808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306594681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3306594681
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.205561426
Short name T725
Test name
Test status
Simulation time 211443614 ps
CPU time 11.23 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:55:40 PM PDT 24
Peak memory 216224 kb
Host smart-33406979-8404-4292-8935-4be27000a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205561426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.205561426
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.260496438
Short name T455
Test name
Test status
Simulation time 27904597 ps
CPU time 0.76 seconds
Started May 26 12:55:24 PM PDT 24
Finished May 26 12:55:28 PM PDT 24
Peak memory 205540 kb
Host smart-1df2e099-58ce-4d79-9c16-2194503c2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260496438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.260496438
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2650940794
Short name T443
Test name
Test status
Simulation time 2256973829 ps
CPU time 6.86 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 234196 kb
Host smart-eac0d7ea-60a7-49f0-98f6-b804db755cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650940794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2650940794
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1597213087
Short name T366
Test name
Test status
Simulation time 28799437 ps
CPU time 0.77 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:37 PM PDT 24
Peak memory 205948 kb
Host smart-c406679a-60ba-44a6-9dac-f059d712511a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597213087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1597213087
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2078040008
Short name T482
Test name
Test status
Simulation time 831196930 ps
CPU time 11.13 seconds
Started May 26 12:55:33 PM PDT 24
Finished May 26 12:55:46 PM PDT 24
Peak memory 233284 kb
Host smart-c446aaa1-5d09-4f10-8e8a-4d72aeb50b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078040008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2078040008
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.223194423
Short name T699
Test name
Test status
Simulation time 19172255 ps
CPU time 0.8 seconds
Started May 26 12:55:26 PM PDT 24
Finished May 26 12:55:30 PM PDT 24
Peak memory 206324 kb
Host smart-43145830-2188-4b5d-9cfc-1a23cb0bb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223194423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.223194423
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3513352833
Short name T205
Test name
Test status
Simulation time 19104247249 ps
CPU time 66.14 seconds
Started May 26 12:55:40 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 249496 kb
Host smart-d0c92407-48b8-499d-aca9-597a7f74be8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513352833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3513352833
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.294448713
Short name T636
Test name
Test status
Simulation time 12492286181 ps
CPU time 68.99 seconds
Started May 26 12:55:38 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 237176 kb
Host smart-4f7a70ad-eef0-4f49-aab7-593860648cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294448713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.294448713
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.663293156
Short name T160
Test name
Test status
Simulation time 7697582369 ps
CPU time 76.64 seconds
Started May 26 12:55:38 PM PDT 24
Finished May 26 12:56:56 PM PDT 24
Peak memory 250512 kb
Host smart-4673aae4-b921-4cd4-afe8-da70472ad1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663293156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.663293156
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.153010806
Short name T406
Test name
Test status
Simulation time 1156371737 ps
CPU time 6.94 seconds
Started May 26 12:55:38 PM PDT 24
Finished May 26 12:55:46 PM PDT 24
Peak memory 224348 kb
Host smart-bdb9dff0-6f9a-4a5d-b154-0f54f48c7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153010806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.153010806
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.441033432
Short name T186
Test name
Test status
Simulation time 5414326234 ps
CPU time 17.14 seconds
Started May 26 12:55:29 PM PDT 24
Finished May 26 12:55:48 PM PDT 24
Peak memory 219520 kb
Host smart-e9cc9359-608f-4166-9439-914273e60ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441033432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.441033432
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1067814884
Short name T369
Test name
Test status
Simulation time 8861648910 ps
CPU time 36.67 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 235160 kb
Host smart-30fad69a-2cd2-4544-a33d-a6481a0a6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067814884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1067814884
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1201280349
Short name T319
Test name
Test status
Simulation time 11086687798 ps
CPU time 27.81 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:55:56 PM PDT 24
Peak memory 229200 kb
Host smart-9b3aadbb-ebfe-4cc5-b247-933eeda83c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201280349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1201280349
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4147282720
Short name T199
Test name
Test status
Simulation time 13699132010 ps
CPU time 9.69 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:55:38 PM PDT 24
Peak memory 224372 kb
Host smart-a70ff68f-43ad-4dca-9973-7aff0da7f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147282720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4147282720
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.905239347
Short name T451
Test name
Test status
Simulation time 98512034 ps
CPU time 3.76 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 222400 kb
Host smart-c4494cf5-c929-4437-98ce-7a934ccc613d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905239347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.905239347
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2650937445
Short name T922
Test name
Test status
Simulation time 61539782151 ps
CPU time 295.58 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 01:00:33 PM PDT 24
Peak memory 249452 kb
Host smart-a0ef3ee0-4890-4e65-a5eb-0b213ba47bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650937445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2650937445
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.762725373
Short name T658
Test name
Test status
Simulation time 15399083138 ps
CPU time 19.77 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:56 PM PDT 24
Peak memory 216084 kb
Host smart-4f9ee802-0477-4958-944d-4da2a986e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762725373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.762725373
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1851798400
Short name T933
Test name
Test status
Simulation time 5659479279 ps
CPU time 5.03 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:41 PM PDT 24
Peak memory 216020 kb
Host smart-61ba5792-8936-460a-92c7-070245de3c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851798400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1851798400
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1044226657
Short name T664
Test name
Test status
Simulation time 1411452118 ps
CPU time 4.63 seconds
Started May 26 12:55:25 PM PDT 24
Finished May 26 12:55:33 PM PDT 24
Peak memory 216044 kb
Host smart-90b83cf8-82fc-40db-a58a-93f45db193d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044226657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1044226657
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1041665253
Short name T422
Test name
Test status
Simulation time 38613969 ps
CPU time 0.83 seconds
Started May 26 12:55:24 PM PDT 24
Finished May 26 12:55:29 PM PDT 24
Peak memory 205632 kb
Host smart-5a8f0b8f-9217-42cc-9150-35265a33ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041665253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1041665253
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1385599818
Short name T580
Test name
Test status
Simulation time 10153155993 ps
CPU time 14.27 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:55:53 PM PDT 24
Peak memory 232492 kb
Host smart-4bdb10bd-f27f-42c7-9764-8323ddb88f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385599818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1385599818
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1321526067
Short name T573
Test name
Test status
Simulation time 48847169 ps
CPU time 0.73 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:55:40 PM PDT 24
Peak memory 204700 kb
Host smart-ac78754c-7b24-4ae2-89a1-c43ab153ade0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321526067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1321526067
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.514378423
Short name T500
Test name
Test status
Simulation time 2078539293 ps
CPU time 15.37 seconds
Started May 26 12:55:38 PM PDT 24
Finished May 26 12:55:55 PM PDT 24
Peak memory 219668 kb
Host smart-a905f8c0-6a5a-4fe8-8811-b094c6238816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514378423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.514378423
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.772687619
Short name T534
Test name
Test status
Simulation time 16341541 ps
CPU time 0.8 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:55:39 PM PDT 24
Peak memory 206612 kb
Host smart-f7116609-e9a9-4ae4-b120-54d482bac0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772687619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.772687619
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3478663911
Short name T284
Test name
Test status
Simulation time 43015831930 ps
CPU time 69.22 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 224284 kb
Host smart-090bd91d-c22a-4728-8ee0-b0851234c314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478663911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3478663911
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2264408106
Short name T901
Test name
Test status
Simulation time 85013876731 ps
CPU time 185.81 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:58:44 PM PDT 24
Peak memory 250176 kb
Host smart-d93b4610-5f4f-45ad-9da0-89b7a61e9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264408106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2264408106
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.376110032
Short name T875
Test name
Test status
Simulation time 3314848876 ps
CPU time 22.45 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 235644 kb
Host smart-8a2f3ba6-c0f8-45c6-ab4e-540b21e0b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376110032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.376110032
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1913265256
Short name T788
Test name
Test status
Simulation time 154452498 ps
CPU time 8.74 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:45 PM PDT 24
Peak memory 240640 kb
Host smart-c66b3871-1091-4957-9932-e8daa49b4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913265256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1913265256
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3250274756
Short name T880
Test name
Test status
Simulation time 157073628 ps
CPU time 4.42 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:41 PM PDT 24
Peak memory 233472 kb
Host smart-04e78c26-6a43-4728-bfa5-a9ffc22b3526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250274756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3250274756
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1676183756
Short name T902
Test name
Test status
Simulation time 371014231 ps
CPU time 5.36 seconds
Started May 26 12:55:40 PM PDT 24
Finished May 26 12:55:47 PM PDT 24
Peak memory 233796 kb
Host smart-aaa4e456-00fb-40b3-b732-d7d0fb4f0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676183756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1676183756
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3238395278
Short name T354
Test name
Test status
Simulation time 30784256 ps
CPU time 2.28 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:39 PM PDT 24
Peak memory 221236 kb
Host smart-c0bebbbc-54bf-46ad-ab7a-ed43a597086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238395278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3238395278
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.540106906
Short name T601
Test name
Test status
Simulation time 58943213547 ps
CPU time 41.35 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:56:19 PM PDT 24
Peak memory 236188 kb
Host smart-30186149-b98e-45a0-aeac-a2db94b5776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540106906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.540106906
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1951714722
Short name T140
Test name
Test status
Simulation time 509061420 ps
CPU time 9.15 seconds
Started May 26 12:55:38 PM PDT 24
Finished May 26 12:55:48 PM PDT 24
Peak memory 219072 kb
Host smart-3db52f13-f589-44fe-b496-0e4687cc09ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1951714722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1951714722
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2476683968
Short name T546
Test name
Test status
Simulation time 52866311341 ps
CPU time 232.61 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:59:31 PM PDT 24
Peak memory 256384 kb
Host smart-3ab389b0-ab2e-40af-b389-8a21669a0229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476683968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2476683968
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3903039589
Short name T741
Test name
Test status
Simulation time 2482042163 ps
CPU time 5.52 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 216080 kb
Host smart-fd28372a-0cb1-40c5-9d4a-1c6b72e515bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903039589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3903039589
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1336140635
Short name T627
Test name
Test status
Simulation time 20413837442 ps
CPU time 7.97 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:44 PM PDT 24
Peak memory 216100 kb
Host smart-8c6c8a01-433d-4b91-a29a-8e04a736c234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336140635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1336140635
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2371531582
Short name T663
Test name
Test status
Simulation time 70572196 ps
CPU time 0.89 seconds
Started May 26 12:55:36 PM PDT 24
Finished May 26 12:55:39 PM PDT 24
Peak memory 205616 kb
Host smart-ca9fc22a-90f2-478b-b2d9-bd69b29af07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371531582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2371531582
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1243373679
Short name T351
Test name
Test status
Simulation time 74212111 ps
CPU time 0.96 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:38 PM PDT 24
Peak memory 206664 kb
Host smart-164022ae-f2c7-425b-adcb-261e49916943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243373679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1243373679
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.498146630
Short name T592
Test name
Test status
Simulation time 1981283571 ps
CPU time 9.92 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 218468 kb
Host smart-3145dac3-59b5-4760-8dc2-41325bbd3907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498146630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.498146630
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4156046602
Short name T791
Test name
Test status
Simulation time 50815644 ps
CPU time 0.74 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:45 PM PDT 24
Peak memory 205356 kb
Host smart-8fd31bfd-c0b8-4beb-8ca7-6379cc3f2854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156046602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4156046602
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1795633319
Short name T487
Test name
Test status
Simulation time 128339098 ps
CPU time 2.5 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 217612 kb
Host smart-f0903f07-681e-4810-90c7-3702c286f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795633319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1795633319
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1780165832
Short name T565
Test name
Test status
Simulation time 48231469 ps
CPU time 0.73 seconds
Started May 26 12:55:34 PM PDT 24
Finished May 26 12:55:37 PM PDT 24
Peak memory 205392 kb
Host smart-e69ed99f-7829-40f1-afd6-50a6e7d8cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780165832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1780165832
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1851323915
Short name T746
Test name
Test status
Simulation time 113394630390 ps
CPU time 103.28 seconds
Started May 26 12:55:46 PM PDT 24
Finished May 26 12:57:31 PM PDT 24
Peak memory 240752 kb
Host smart-9ee693cc-73df-4c2a-a1e6-d3bce98dfe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851323915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1851323915
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1853657961
Short name T189
Test name
Test status
Simulation time 20588240400 ps
CPU time 31.97 seconds
Started May 26 12:55:49 PM PDT 24
Finished May 26 12:56:23 PM PDT 24
Peak memory 250304 kb
Host smart-c291b3a5-4f95-453b-8245-ed7d18917a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853657961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1853657961
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1586652757
Short name T467
Test name
Test status
Simulation time 17102494188 ps
CPU time 100.87 seconds
Started May 26 12:55:42 PM PDT 24
Finished May 26 12:57:24 PM PDT 24
Peak memory 248984 kb
Host smart-45580135-3d27-4973-a428-cb4b32dbb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586652757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1586652757
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2662376200
Short name T711
Test name
Test status
Simulation time 79502697 ps
CPU time 3.35 seconds
Started May 26 12:55:42 PM PDT 24
Finished May 26 12:55:46 PM PDT 24
Peak memory 232516 kb
Host smart-de5692b2-1496-4bc2-825a-5935d6577c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662376200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2662376200
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3251733172
Short name T305
Test name
Test status
Simulation time 270091555 ps
CPU time 3.28 seconds
Started May 26 12:55:40 PM PDT 24
Finished May 26 12:55:45 PM PDT 24
Peak memory 219476 kb
Host smart-5293f870-248c-46ca-aeca-7073ec1887d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251733172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3251733172
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3868649296
Short name T204
Test name
Test status
Simulation time 2384956997 ps
CPU time 26.87 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:56:11 PM PDT 24
Peak memory 219924 kb
Host smart-f7f34204-79ba-4411-98ec-73024f2ff4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868649296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3868649296
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1550782056
Short name T235
Test name
Test status
Simulation time 25435583323 ps
CPU time 21.55 seconds
Started May 26 12:55:37 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 239344 kb
Host smart-cf4d7d81-3549-49c2-80ef-0136e2607d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550782056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1550782056
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.168300860
Short name T821
Test name
Test status
Simulation time 3615762938 ps
CPU time 6.77 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:44 PM PDT 24
Peak memory 232536 kb
Host smart-49887c57-2748-42f8-b068-27e442d384fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168300860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.168300860
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3862707043
Short name T371
Test name
Test status
Simulation time 349422003 ps
CPU time 4.62 seconds
Started May 26 12:55:44 PM PDT 24
Finished May 26 12:55:50 PM PDT 24
Peak memory 222720 kb
Host smart-ef074cfd-a353-4543-b10a-d0b1c2b7d7b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862707043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3862707043
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2167210648
Short name T907
Test name
Test status
Simulation time 39965631654 ps
CPU time 52.91 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 216148 kb
Host smart-7b805468-4419-42ae-931f-2de668aa310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167210648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2167210648
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3459977678
Short name T539
Test name
Test status
Simulation time 1065530943 ps
CPU time 4.67 seconds
Started May 26 12:55:33 PM PDT 24
Finished May 26 12:55:40 PM PDT 24
Peak memory 215944 kb
Host smart-cb22fdc6-f64a-4d49-8f02-6b5dc326179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459977678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3459977678
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.445089646
Short name T620
Test name
Test status
Simulation time 36408955 ps
CPU time 0.91 seconds
Started May 26 12:55:35 PM PDT 24
Finished May 26 12:55:38 PM PDT 24
Peak memory 206892 kb
Host smart-89e5d499-66df-43a7-a9cb-71f1c1724150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445089646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.445089646
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.670576303
Short name T129
Test name
Test status
Simulation time 45568305 ps
CPU time 0.86 seconds
Started May 26 12:55:40 PM PDT 24
Finished May 26 12:55:43 PM PDT 24
Peak memory 205620 kb
Host smart-09ed638a-3d98-4ea5-8661-7382f8ff1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670576303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.670576303
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3855336141
Short name T172
Test name
Test status
Simulation time 1030017614 ps
CPU time 4.76 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 233196 kb
Host smart-dee330b1-3f09-46eb-a4b2-b706d2939ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855336141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3855336141
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4093977703
Short name T454
Test name
Test status
Simulation time 36546109 ps
CPU time 0.73 seconds
Started May 26 12:55:52 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 205276 kb
Host smart-af2a5330-14cd-45de-b6b4-4536a7061495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093977703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4093977703
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2569614866
Short name T913
Test name
Test status
Simulation time 188798036 ps
CPU time 3.31 seconds
Started May 26 12:55:44 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 234292 kb
Host smart-5b0f0e87-00e0-4ea5-b68b-923548b0133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569614866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2569614866
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3683191201
Short name T790
Test name
Test status
Simulation time 14561803 ps
CPU time 0.73 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:46 PM PDT 24
Peak memory 206580 kb
Host smart-c973ab7e-7c96-46e6-934b-729e26c5aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683191201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3683191201
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1673872641
Short name T738
Test name
Test status
Simulation time 24746838115 ps
CPU time 81.26 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:57:13 PM PDT 24
Peak memory 252424 kb
Host smart-a96e8536-377c-4b3a-83ce-bce1aa6aa52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673872641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1673872641
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3888953160
Short name T874
Test name
Test status
Simulation time 47040782416 ps
CPU time 139.93 seconds
Started May 26 12:55:51 PM PDT 24
Finished May 26 12:58:13 PM PDT 24
Peak memory 249088 kb
Host smart-4b322b81-7c0a-40fe-aab7-85b0fae2a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888953160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3888953160
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4107758559
Short name T876
Test name
Test status
Simulation time 158602615 ps
CPU time 5.04 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:55:57 PM PDT 24
Peak memory 224228 kb
Host smart-02898b46-d18a-4393-8625-db1a4fec0c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107758559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4107758559
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2739291215
Short name T123
Test name
Test status
Simulation time 33312854 ps
CPU time 2.5 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:47 PM PDT 24
Peak memory 220864 kb
Host smart-c4ed3ebf-89bc-4f81-9000-046c38fec1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739291215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2739291215
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.151749509
Short name T581
Test name
Test status
Simulation time 568173409 ps
CPU time 5.65 seconds
Started May 26 12:55:45 PM PDT 24
Finished May 26 12:55:52 PM PDT 24
Peak memory 234056 kb
Host smart-97bcb3ae-9e0a-46a9-9702-84f8f7f9d74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151749509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.151749509
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.511470537
Short name T905
Test name
Test status
Simulation time 4482603328 ps
CPU time 5.63 seconds
Started May 26 12:55:46 PM PDT 24
Finished May 26 12:55:53 PM PDT 24
Peak memory 236176 kb
Host smart-fb864145-899d-48d0-978b-b19ce74cac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511470537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.511470537
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.344877686
Short name T618
Test name
Test status
Simulation time 9134942890 ps
CPU time 6.77 seconds
Started May 26 12:55:45 PM PDT 24
Finished May 26 12:55:53 PM PDT 24
Peak memory 223112 kb
Host smart-f283eacf-98b0-4b4f-bd55-7ab5009d6d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344877686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.344877686
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1971401628
Short name T456
Test name
Test status
Simulation time 160275075 ps
CPU time 3.78 seconds
Started May 26 12:55:55 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 219148 kb
Host smart-1b91e75f-ffc0-4fe5-82b4-3a74627b9372
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1971401628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1971401628
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.686850251
Short name T645
Test name
Test status
Simulation time 2594875828 ps
CPU time 24.74 seconds
Started May 26 12:55:49 PM PDT 24
Finished May 26 12:56:16 PM PDT 24
Peak memory 216104 kb
Host smart-5e5b4b80-c52e-4be5-a8e0-0316692797c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686850251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.686850251
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.829411032
Short name T84
Test name
Test status
Simulation time 1054943061 ps
CPU time 2.58 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:46 PM PDT 24
Peak memory 207572 kb
Host smart-ef3e857c-afbe-4f91-9747-0d9d5305fcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829411032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.829411032
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1159299530
Short name T530
Test name
Test status
Simulation time 1338090720 ps
CPU time 8.04 seconds
Started May 26 12:55:44 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 216116 kb
Host smart-d9fc7c10-9437-4c2a-a1d8-d0c52276bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159299530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1159299530
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.190190732
Short name T392
Test name
Test status
Simulation time 46187096 ps
CPU time 0.8 seconds
Started May 26 12:55:43 PM PDT 24
Finished May 26 12:55:45 PM PDT 24
Peak memory 205524 kb
Host smart-b199c84b-498b-49c8-bfe2-1157383befe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190190732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.190190732
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2907239756
Short name T469
Test name
Test status
Simulation time 10804372985 ps
CPU time 16.28 seconds
Started May 26 12:55:42 PM PDT 24
Finished May 26 12:55:59 PM PDT 24
Peak memory 234748 kb
Host smart-1361c3ea-dfc3-425c-8214-c1f0f6f6a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907239756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2907239756
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1430012927
Short name T753
Test name
Test status
Simulation time 17932405 ps
CPU time 0.77 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 205648 kb
Host smart-efba6b60-be87-4a77-8a63-80d168baea29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430012927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1430012927
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2463551504
Short name T501
Test name
Test status
Simulation time 127924999 ps
CPU time 2.08 seconds
Started May 26 12:55:53 PM PDT 24
Finished May 26 12:55:57 PM PDT 24
Peak memory 216052 kb
Host smart-2f56a2ed-7e0a-4e26-b402-49a0475fc135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463551504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2463551504
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.698876511
Short name T388
Test name
Test status
Simulation time 19922259 ps
CPU time 0.74 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:55:53 PM PDT 24
Peak memory 205296 kb
Host smart-3d8de50a-812b-44df-b5e8-8ec7be480d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698876511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.698876511
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2875119765
Short name T785
Test name
Test status
Simulation time 53395731392 ps
CPU time 186.1 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:59:07 PM PDT 24
Peak memory 250748 kb
Host smart-9b28239e-e3c7-4dc4-ad9c-ed7ea01c7754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875119765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2875119765
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.9140080
Short name T185
Test name
Test status
Simulation time 104239447558 ps
CPU time 247.84 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 01:00:10 PM PDT 24
Peak memory 249036 kb
Host smart-31ead304-cb19-4513-8afb-84f7e9b51b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9140080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.9140080
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1135932499
Short name T131
Test name
Test status
Simulation time 5186506574 ps
CPU time 42.94 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:56:46 PM PDT 24
Peak memory 249004 kb
Host smart-0982bbb6-3485-40b3-b7f2-a62b50342a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135932499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1135932499
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3623887297
Short name T547
Test name
Test status
Simulation time 4307246050 ps
CPU time 13.94 seconds
Started May 26 12:55:52 PM PDT 24
Finished May 26 12:56:07 PM PDT 24
Peak memory 224428 kb
Host smart-fa57cdbc-3ea9-47b1-94f4-e5cbc1e9bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623887297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3623887297
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1053225740
Short name T291
Test name
Test status
Simulation time 256208589 ps
CPU time 6.06 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:55:58 PM PDT 24
Peak memory 219316 kb
Host smart-d7117fd8-db2b-440d-8cbb-229cfc44676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053225740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1053225740
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4190724817
Short name T407
Test name
Test status
Simulation time 11079574845 ps
CPU time 68.2 seconds
Started May 26 12:55:51 PM PDT 24
Finished May 26 12:57:01 PM PDT 24
Peak memory 239024 kb
Host smart-9f1acbee-5776-42ca-bffc-d5f5695de444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190724817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4190724817
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1044501603
Short name T225
Test name
Test status
Simulation time 2817801073 ps
CPU time 5.9 seconds
Started May 26 12:55:51 PM PDT 24
Finished May 26 12:55:58 PM PDT 24
Peak memory 233120 kb
Host smart-93ac5bb9-0d36-4f71-93d5-fab3a2facf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044501603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1044501603
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3054201580
Short name T709
Test name
Test status
Simulation time 116089218 ps
CPU time 2.49 seconds
Started May 26 12:55:52 PM PDT 24
Finished May 26 12:55:56 PM PDT 24
Peak memory 221284 kb
Host smart-24865206-c9ec-4342-a04a-3b8059a4b87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054201580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3054201580
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3280839828
Short name T857
Test name
Test status
Simulation time 1970192619 ps
CPU time 7 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 220120 kb
Host smart-5ed95bbf-2767-4a35-be1d-3a1221f6276c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280839828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3280839828
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3419606401
Short name T685
Test name
Test status
Simulation time 1951684097 ps
CPU time 29.14 seconds
Started May 26 12:56:02 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 234876 kb
Host smart-6866beb3-e33c-4b09-87eb-61db60b38f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419606401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3419606401
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2524530922
Short name T590
Test name
Test status
Simulation time 890322792 ps
CPU time 7.03 seconds
Started May 26 12:55:49 PM PDT 24
Finished May 26 12:55:58 PM PDT 24
Peak memory 216128 kb
Host smart-f721bb1d-a214-4c91-9d23-117462ea6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524530922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2524530922
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2848070671
Short name T540
Test name
Test status
Simulation time 8372439541 ps
CPU time 25.33 seconds
Started May 26 12:55:55 PM PDT 24
Finished May 26 12:56:22 PM PDT 24
Peak memory 216132 kb
Host smart-0f1c7242-677d-40fd-a68b-fa5bdbcaa32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848070671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2848070671
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3330288482
Short name T15
Test name
Test status
Simulation time 864109765 ps
CPU time 6.68 seconds
Started May 26 12:55:53 PM PDT 24
Finished May 26 12:56:01 PM PDT 24
Peak memory 216240 kb
Host smart-2eee32ac-8163-4e7f-a6a9-23be691a761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330288482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3330288482
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3954257853
Short name T400
Test name
Test status
Simulation time 17684750 ps
CPU time 0.76 seconds
Started May 26 12:55:50 PM PDT 24
Finished May 26 12:55:53 PM PDT 24
Peak memory 205504 kb
Host smart-e083899f-023c-47a6-963c-9fc58457a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954257853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3954257853
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.864183685
Short name T286
Test name
Test status
Simulation time 466075514 ps
CPU time 2.78 seconds
Started May 26 12:55:51 PM PDT 24
Finished May 26 12:55:55 PM PDT 24
Peak memory 224188 kb
Host smart-b3bf2802-1bbb-49f8-882a-1e72f3232772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864183685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.864183685
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.835322842
Short name T59
Test name
Test status
Simulation time 14745688 ps
CPU time 0.73 seconds
Started May 26 12:52:25 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 204728 kb
Host smart-f95daaed-a334-45ed-bc47-97042240e575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835322842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.835322842
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2971543030
Short name T417
Test name
Test status
Simulation time 77672035 ps
CPU time 2.68 seconds
Started May 26 12:52:14 PM PDT 24
Finished May 26 12:52:17 PM PDT 24
Peak memory 218476 kb
Host smart-3e5a858c-9fed-4850-a72b-d158258b0634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971543030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2971543030
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3403513115
Short name T657
Test name
Test status
Simulation time 20376994 ps
CPU time 0.79 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:17 PM PDT 24
Peak memory 205388 kb
Host smart-6c6eb7df-54d0-4903-b71f-48b25c450e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403513115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3403513115
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2578482790
Short name T166
Test name
Test status
Simulation time 3926265715 ps
CPU time 16.12 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:52:33 PM PDT 24
Peak memory 239960 kb
Host smart-d005e66d-1fd5-4c2c-9f86-aad17ac46c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578482790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2578482790
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3303790834
Short name T267
Test name
Test status
Simulation time 7893124215 ps
CPU time 88.11 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:53:44 PM PDT 24
Peak memory 257152 kb
Host smart-11e35c2c-8927-4349-9395-a6eeb9e24715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303790834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3303790834
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3458887979
Short name T681
Test name
Test status
Simulation time 3386103896 ps
CPU time 48.61 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 232552 kb
Host smart-112f3eab-d74f-424e-9dc6-b10255fa7159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458887979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3458887979
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.146657946
Short name T703
Test name
Test status
Simulation time 1613640760 ps
CPU time 3.98 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:20 PM PDT 24
Peak memory 235568 kb
Host smart-856df2fd-8bdf-46b1-a5bb-08c8c1de799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146657946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.146657946
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3822733948
Short name T948
Test name
Test status
Simulation time 1790287194 ps
CPU time 14.05 seconds
Started May 26 12:52:14 PM PDT 24
Finished May 26 12:52:29 PM PDT 24
Peak memory 218460 kb
Host smart-02fc59a2-26db-4d1a-b7bb-3d3644ed3f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822733948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3822733948
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4052279758
Short name T713
Test name
Test status
Simulation time 2131525274 ps
CPU time 12.14 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:52:29 PM PDT 24
Peak memory 218556 kb
Host smart-c279af0b-366c-4a87-8620-82366b7d8be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052279758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4052279758
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3730041516
Short name T775
Test name
Test status
Simulation time 1857171536 ps
CPU time 11.9 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:28 PM PDT 24
Peak memory 235900 kb
Host smart-4ea5d3ab-c6b7-4eff-9325-522cb652db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730041516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3730041516
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1190171352
Short name T398
Test name
Test status
Simulation time 798635480 ps
CPU time 9.18 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 222676 kb
Host smart-0cf5fe64-dc68-47d9-a3d7-b475f8e56144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1190171352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1190171352
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3415182375
Short name T68
Test name
Test status
Simulation time 117290035 ps
CPU time 1 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 235024 kb
Host smart-4be096a7-12f2-4237-9cef-3f1682ae1f80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415182375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3415182375
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3824724532
Short name T70
Test name
Test status
Simulation time 162016116 ps
CPU time 0.89 seconds
Started May 26 12:52:26 PM PDT 24
Finished May 26 12:52:27 PM PDT 24
Peak memory 206708 kb
Host smart-687e6ecd-1a07-4e1b-b091-e423b9bed487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824724532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3824724532
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.979069600
Short name T792
Test name
Test status
Simulation time 18979663673 ps
CPU time 56.35 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:53:13 PM PDT 24
Peak memory 216140 kb
Host smart-a649d6b7-96d2-40ce-bd51-f9dd83496bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979069600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.979069600
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.304756816
Short name T571
Test name
Test status
Simulation time 13100962772 ps
CPU time 20.83 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:37 PM PDT 24
Peak memory 216088 kb
Host smart-8161df10-6cdb-4f92-97dd-5418d006a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304756816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.304756816
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1043340102
Short name T393
Test name
Test status
Simulation time 139911861 ps
CPU time 2.61 seconds
Started May 26 12:52:15 PM PDT 24
Finished May 26 12:52:19 PM PDT 24
Peak memory 216128 kb
Host smart-98593e51-07af-47fc-9705-4c7a0b59daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043340102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1043340102
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.554592954
Short name T952
Test name
Test status
Simulation time 68289578 ps
CPU time 0.93 seconds
Started May 26 12:52:16 PM PDT 24
Finished May 26 12:52:18 PM PDT 24
Peak memory 206564 kb
Host smart-84731cf2-ca17-467e-adbe-94752997477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554592954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.554592954
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3154908127
Short name T938
Test name
Test status
Simulation time 302544425 ps
CPU time 5.56 seconds
Started May 26 12:52:14 PM PDT 24
Finished May 26 12:52:21 PM PDT 24
Peak memory 233736 kb
Host smart-926355a9-4504-40aa-91f0-27d26c067ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154908127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3154908127
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2425395141
Short name T760
Test name
Test status
Simulation time 12735753 ps
CPU time 0.75 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:14 PM PDT 24
Peak memory 204812 kb
Host smart-cc9223b1-a039-4fa5-a19c-f526297395af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425395141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2425395141
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2673519556
Short name T431
Test name
Test status
Simulation time 4391665170 ps
CPU time 13.02 seconds
Started May 26 12:56:02 PM PDT 24
Finished May 26 12:56:16 PM PDT 24
Peak memory 235180 kb
Host smart-669db182-82f9-4d4c-991b-5702b9809cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673519556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2673519556
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1362107225
Short name T511
Test name
Test status
Simulation time 13145552 ps
CPU time 0.78 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:56:03 PM PDT 24
Peak memory 205216 kb
Host smart-8a144fec-a7c3-4869-b520-87c582298fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362107225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1362107225
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.35032801
Short name T191
Test name
Test status
Simulation time 87809440209 ps
CPU time 334.24 seconds
Started May 26 12:55:58 PM PDT 24
Finished May 26 01:01:33 PM PDT 24
Peak memory 266160 kb
Host smart-8f81d30b-4590-4a26-b4fa-6f1b5c3fee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35032801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.35032801
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4153765530
Short name T572
Test name
Test status
Simulation time 4416984234 ps
CPU time 16.81 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:56:20 PM PDT 24
Peak memory 217156 kb
Host smart-7d17202c-1425-4f47-b421-c4602d4c6347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153765530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4153765530
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2527187409
Short name T326
Test name
Test status
Simulation time 2064088266 ps
CPU time 30.43 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 224380 kb
Host smart-9acbddb7-b74c-44d0-a5e2-508d7175ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527187409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2527187409
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.84974710
Short name T842
Test name
Test status
Simulation time 32173316 ps
CPU time 2.1 seconds
Started May 26 12:55:59 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 215908 kb
Host smart-683f55a1-c8c6-48ca-bfd0-7aa5a4e35bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84974710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.84974710
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4191164856
Short name T513
Test name
Test status
Simulation time 1128319256 ps
CPU time 4.76 seconds
Started May 26 12:55:59 PM PDT 24
Finished May 26 12:56:05 PM PDT 24
Peak memory 218148 kb
Host smart-563c9ccb-6e2e-4101-8aaa-40d6f18eddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191164856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4191164856
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3118111171
Short name T642
Test name
Test status
Simulation time 33153461 ps
CPU time 2.42 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:56:05 PM PDT 24
Peak memory 220988 kb
Host smart-2e1dfdfe-6c8c-4427-9ab1-7c1010faf245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118111171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3118111171
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3272358317
Short name T661
Test name
Test status
Simulation time 480035381 ps
CPU time 4.33 seconds
Started May 26 12:56:02 PM PDT 24
Finished May 26 12:56:08 PM PDT 24
Peak memory 232500 kb
Host smart-5f6907c6-d87c-4e73-8e70-8e6c863bc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272358317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3272358317
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2343271079
Short name T533
Test name
Test status
Simulation time 621344264 ps
CPU time 4.52 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:56:07 PM PDT 24
Peak memory 219980 kb
Host smart-e25c9753-8499-439f-a565-184076f37deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343271079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2343271079
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2594453152
Short name T224
Test name
Test status
Simulation time 945846240504 ps
CPU time 491.51 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 01:04:14 PM PDT 24
Peak memory 256284 kb
Host smart-525793f6-597e-4112-bc93-b0434b8d60f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594453152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2594453152
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1059429350
Short name T674
Test name
Test status
Simulation time 2834589299 ps
CPU time 10.21 seconds
Started May 26 12:55:59 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 216132 kb
Host smart-e126d10f-4146-4e78-9061-02e6b4ceb4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059429350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1059429350
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1392492089
Short name T605
Test name
Test status
Simulation time 224341506 ps
CPU time 2.09 seconds
Started May 26 12:55:58 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 216116 kb
Host smart-155f1ea2-cc62-414f-abcd-22ecf3e0417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392492089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1392492089
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1415160652
Short name T766
Test name
Test status
Simulation time 58025452 ps
CPU time 1.82 seconds
Started May 26 12:56:01 PM PDT 24
Finished May 26 12:56:05 PM PDT 24
Peak memory 216084 kb
Host smart-429b5af1-e134-43ad-a398-1546f4fe64cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415160652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1415160652
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3768706353
Short name T853
Test name
Test status
Simulation time 19361120 ps
CPU time 0.76 seconds
Started May 26 12:56:00 PM PDT 24
Finished May 26 12:56:02 PM PDT 24
Peak memory 205540 kb
Host smart-81daa6e2-bbb1-4801-a7c7-ed887352b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768706353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3768706353
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3260356673
Short name T317
Test name
Test status
Simulation time 1128435501 ps
CPU time 6.66 seconds
Started May 26 12:56:02 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 216416 kb
Host smart-3fdecc20-e33b-4eec-99a5-ca28bdb0778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260356673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3260356673
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2632976643
Short name T816
Test name
Test status
Simulation time 21174014 ps
CPU time 0.72 seconds
Started May 26 12:56:08 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 204680 kb
Host smart-5f35ad01-a652-4893-8d96-5504ca1358a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632976643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2632976643
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3220135966
Short name T208
Test name
Test status
Simulation time 290988132 ps
CPU time 2.36 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:13 PM PDT 24
Peak memory 218400 kb
Host smart-d8d3ccf9-53e2-4957-b729-0cb4973801ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220135966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3220135966
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1235681197
Short name T628
Test name
Test status
Simulation time 67489281 ps
CPU time 0.76 seconds
Started May 26 12:56:15 PM PDT 24
Finished May 26 12:56:16 PM PDT 24
Peak memory 206588 kb
Host smart-7d88c36b-8e7e-45e8-8cbf-4ff47a1f0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235681197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1235681197
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.760299278
Short name T847
Test name
Test status
Simulation time 191174409852 ps
CPU time 240.91 seconds
Started May 26 12:56:16 PM PDT 24
Finished May 26 01:00:18 PM PDT 24
Peak memory 239868 kb
Host smart-952704b4-610d-44c4-ae0f-ebe4eaa9c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760299278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.760299278
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1604274161
Short name T687
Test name
Test status
Simulation time 49482324982 ps
CPU time 26.95 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:39 PM PDT 24
Peak memory 217400 kb
Host smart-b6e4923a-0a73-4799-8c20-222b939e2b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604274161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1604274161
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.942507295
Short name T545
Test name
Test status
Simulation time 1246495834 ps
CPU time 30.12 seconds
Started May 26 12:56:16 PM PDT 24
Finished May 26 12:56:47 PM PDT 24
Peak memory 256716 kb
Host smart-2d17b2ea-5f42-4cf6-90f0-0eae7c94174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942507295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.942507295
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3913576180
Short name T332
Test name
Test status
Simulation time 490425566 ps
CPU time 4.83 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 224388 kb
Host smart-baeb974c-0e31-487b-8735-590c62d4cc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913576180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3913576180
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.957399005
Short name T594
Test name
Test status
Simulation time 150724143 ps
CPU time 3.69 seconds
Started May 26 12:56:08 PM PDT 24
Finished May 26 12:56:12 PM PDT 24
Peak memory 233988 kb
Host smart-5c00a938-2d69-4acf-8d58-9886ef7a8abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957399005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.957399005
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.388801974
Short name T819
Test name
Test status
Simulation time 310107450 ps
CPU time 3.8 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 234956 kb
Host smart-f3e818cf-4e7d-46ea-972d-330bd2f27705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388801974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.388801974
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3797275096
Short name T883
Test name
Test status
Simulation time 4823893268 ps
CPU time 7.67 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:19 PM PDT 24
Peak memory 233344 kb
Host smart-04a18f5c-70d8-4586-b713-7a2b62b3bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797275096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3797275096
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4047399438
Short name T477
Test name
Test status
Simulation time 4669296451 ps
CPU time 17.41 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:31 PM PDT 24
Peak memory 218244 kb
Host smart-1b647000-3574-4928-961f-c5827a54c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047399438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4047399438
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.765758101
Short name T556
Test name
Test status
Simulation time 3544081825 ps
CPU time 6.63 seconds
Started May 26 12:56:16 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 222372 kb
Host smart-b858f9a8-69d7-4f9c-8425-ccd936e6176d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=765758101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.765758101
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3870854151
Short name T151
Test name
Test status
Simulation time 53855619 ps
CPU time 1.05 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:12 PM PDT 24
Peak memory 206668 kb
Host smart-8c259f14-9bb3-415f-82e7-38bc222881d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870854151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3870854151
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.67568655
Short name T925
Test name
Test status
Simulation time 999888199 ps
CPU time 5.78 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:18 PM PDT 24
Peak memory 216068 kb
Host smart-beedede4-4591-4192-a034-b9998e635b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67568655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.67568655
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.185665337
Short name T803
Test name
Test status
Simulation time 432158944 ps
CPU time 1.76 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 207556 kb
Host smart-5a0c17e3-e29b-4414-8aab-5dfd11a350cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185665337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.185665337
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3348323133
Short name T14
Test name
Test status
Simulation time 179009063 ps
CPU time 1.42 seconds
Started May 26 12:56:08 PM PDT 24
Finished May 26 12:56:11 PM PDT 24
Peak memory 216228 kb
Host smart-daf482b7-7d46-45d6-840a-34e311f48a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348323133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3348323133
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3557283950
Short name T374
Test name
Test status
Simulation time 26516850 ps
CPU time 0.76 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:13 PM PDT 24
Peak memory 205552 kb
Host smart-6ba38db6-5bda-4754-9121-811cc05d5bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557283950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3557283950
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.302377230
Short name T541
Test name
Test status
Simulation time 992926074 ps
CPU time 5.82 seconds
Started May 26 12:56:08 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 219536 kb
Host smart-5a63f4ae-3d1b-47c7-9bb0-ec5640a98934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302377230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.302377230
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1333493444
Short name T391
Test name
Test status
Simulation time 41102033 ps
CPU time 0.71 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:13 PM PDT 24
Peak memory 205324 kb
Host smart-225fe3c7-e9bd-4601-9ea3-1348d32da2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333493444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1333493444
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4139671681
Short name T872
Test name
Test status
Simulation time 513949363 ps
CPU time 6.53 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:17 PM PDT 24
Peak memory 218436 kb
Host smart-3c5ead9e-6906-461d-b176-ec73ef4abdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139671681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4139671681
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4263929700
Short name T706
Test name
Test status
Simulation time 64460483 ps
CPU time 0.77 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:14 PM PDT 24
Peak memory 205540 kb
Host smart-23f73f0e-8999-411e-8f88-0c4abda46fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263929700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4263929700
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1103463433
Short name T238
Test name
Test status
Simulation time 9816820001 ps
CPU time 89.51 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:57:40 PM PDT 24
Peak memory 248960 kb
Host smart-6f9bfcc0-26e7-4ed7-8a0d-183d68449581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103463433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1103463433
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3311634111
Short name T27
Test name
Test status
Simulation time 21594491352 ps
CPU time 124.14 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:58:18 PM PDT 24
Peak memory 250884 kb
Host smart-fad5f236-3e02-4c2e-9504-89512dbfa337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311634111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3311634111
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1088403417
Short name T23
Test name
Test status
Simulation time 18986587974 ps
CPU time 101.57 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:57:55 PM PDT 24
Peak memory 249308 kb
Host smart-39389518-a702-4646-b190-ce5e0a4c6eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088403417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1088403417
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.99663246
Short name T328
Test name
Test status
Simulation time 4465871133 ps
CPU time 27.03 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:40 PM PDT 24
Peak memory 248940 kb
Host smart-b1e98094-ac61-4066-9da4-4b4869719c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99663246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.99663246
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3647097898
Short name T212
Test name
Test status
Simulation time 1253416433 ps
CPU time 5.54 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:18 PM PDT 24
Peak memory 219636 kb
Host smart-21173819-22fb-4770-b68a-8909029518ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647097898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3647097898
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1102686428
Short name T13
Test name
Test status
Simulation time 1675045504 ps
CPU time 19.99 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 228340 kb
Host smart-0f5993ff-f4e1-44fb-aaae-cbd48ba5f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102686428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1102686428
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4047641374
Short name T731
Test name
Test status
Simulation time 1067595309 ps
CPU time 7.14 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:19 PM PDT 24
Peak memory 216580 kb
Host smart-ff6c5f30-24cc-4184-b2ca-e35fdcf01c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047641374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4047641374
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.874530613
Short name T177
Test name
Test status
Simulation time 253994906 ps
CPU time 4.32 seconds
Started May 26 12:56:15 PM PDT 24
Finished May 26 12:56:20 PM PDT 24
Peak memory 232996 kb
Host smart-f3cf8840-1241-48d6-82ca-ed7725030729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874530613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.874530613
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3213421170
Short name T472
Test name
Test status
Simulation time 1049040524 ps
CPU time 13.5 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 221364 kb
Host smart-47a2d636-146c-494b-b526-880f30a69021
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3213421170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3213421170
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2174332219
Short name T41
Test name
Test status
Simulation time 12481425600 ps
CPU time 78.12 seconds
Started May 26 12:56:08 PM PDT 24
Finished May 26 12:57:26 PM PDT 24
Peak memory 249020 kb
Host smart-ca50f4b0-7347-475a-b3d8-20dcd420d4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174332219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2174332219
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3302155578
Short name T818
Test name
Test status
Simulation time 16125280750 ps
CPU time 41.23 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:51 PM PDT 24
Peak memory 216144 kb
Host smart-afada60a-dd07-4c56-9c11-3d1ec9354168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302155578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3302155578
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4114421464
Short name T625
Test name
Test status
Simulation time 4917590029 ps
CPU time 14.09 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:27 PM PDT 24
Peak memory 215992 kb
Host smart-9ab366cb-d42e-4656-8534-edd40d435901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114421464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4114421464
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3474414485
Short name T523
Test name
Test status
Simulation time 90355102 ps
CPU time 0.91 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:14 PM PDT 24
Peak memory 207648 kb
Host smart-67f6dbff-d28e-41da-97dd-32e2b77a0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474414485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3474414485
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.112061019
Short name T389
Test name
Test status
Simulation time 63496081 ps
CPU time 0.72 seconds
Started May 26 12:56:16 PM PDT 24
Finished May 26 12:56:18 PM PDT 24
Peak memory 205476 kb
Host smart-1da4b800-d013-4c2f-ad26-30113f9927f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112061019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.112061019
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2144511138
Short name T11
Test name
Test status
Simulation time 2531656340 ps
CPU time 4.31 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:17 PM PDT 24
Peak memory 218884 kb
Host smart-84a05bb5-0881-47a1-8b1c-eeee16dbb611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144511138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2144511138
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3280459833
Short name T353
Test name
Test status
Simulation time 12687149 ps
CPU time 0.72 seconds
Started May 26 12:56:17 PM PDT 24
Finished May 26 12:56:19 PM PDT 24
Peak memory 204688 kb
Host smart-2a41ac3f-3a7f-4ae3-9c00-c77667a06f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280459833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3280459833
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2705174827
Short name T851
Test name
Test status
Simulation time 4301361508 ps
CPU time 15.61 seconds
Started May 26 12:56:19 PM PDT 24
Finished May 26 12:56:36 PM PDT 24
Peak memory 221188 kb
Host smart-653dee6c-8e99-4490-8491-5e74425053dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705174827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2705174827
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1881716990
Short name T752
Test name
Test status
Simulation time 16399447 ps
CPU time 0.78 seconds
Started May 26 12:56:10 PM PDT 24
Finished May 26 12:56:12 PM PDT 24
Peak memory 205308 kb
Host smart-992165a0-ae26-4331-8fc9-1040372a671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881716990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1881716990
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.6433120
Short name T859
Test name
Test status
Simulation time 90342744681 ps
CPU time 93.41 seconds
Started May 26 12:56:20 PM PDT 24
Finished May 26 12:57:55 PM PDT 24
Peak memory 236984 kb
Host smart-669fa119-46e5-43c2-93e3-c9e072dead16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6433120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.6433120
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1250829127
Short name T950
Test name
Test status
Simulation time 1977085383 ps
CPU time 19.79 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 221252 kb
Host smart-7d8ba1c6-dc4a-486b-a909-d6f0a1f8cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250829127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1250829127
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1357576387
Short name T133
Test name
Test status
Simulation time 161983505893 ps
CPU time 305.45 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 252008 kb
Host smart-41100bc5-6d70-450f-b435-232b10a2fc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357576387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1357576387
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3562449152
Short name T740
Test name
Test status
Simulation time 1875095532 ps
CPU time 8.96 seconds
Started May 26 12:56:24 PM PDT 24
Finished May 26 12:56:35 PM PDT 24
Peak memory 233536 kb
Host smart-5e80ebc8-8ee6-4272-9ac3-62023fe22045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562449152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3562449152
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1269010694
Short name T866
Test name
Test status
Simulation time 2423808457 ps
CPU time 8.26 seconds
Started May 26 12:56:17 PM PDT 24
Finished May 26 12:56:27 PM PDT 24
Peak memory 234720 kb
Host smart-9ecc5072-4565-4536-ad53-703566ea46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269010694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1269010694
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3588383456
Short name T714
Test name
Test status
Simulation time 18162425022 ps
CPU time 27.21 seconds
Started May 26 12:56:22 PM PDT 24
Finished May 26 12:56:51 PM PDT 24
Peak memory 218440 kb
Host smart-fe30bc21-70ef-4e23-a636-6a6dbc6a2e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588383456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3588383456
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1652736503
Short name T293
Test name
Test status
Simulation time 7551020753 ps
CPU time 8.15 seconds
Started May 26 12:56:18 PM PDT 24
Finished May 26 12:56:28 PM PDT 24
Peak memory 229220 kb
Host smart-6b8bbb0b-1a6b-4c80-b206-36d836ee12db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652736503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1652736503
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4066638203
Short name T214
Test name
Test status
Simulation time 455559859 ps
CPU time 4.25 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:18 PM PDT 24
Peak memory 218224 kb
Host smart-abffb9d0-0af4-4e65-b3c3-e00684664f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066638203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4066638203
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1506402173
Short name T491
Test name
Test status
Simulation time 607402281 ps
CPU time 3.85 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 12:56:28 PM PDT 24
Peak memory 218828 kb
Host smart-ef9d8c4a-9421-45bc-88d2-8c2618750ca9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1506402173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1506402173
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1080941615
Short name T473
Test name
Test status
Simulation time 92708332 ps
CPU time 1.06 seconds
Started May 26 12:56:18 PM PDT 24
Finished May 26 12:56:20 PM PDT 24
Peak memory 206944 kb
Host smart-7f623e36-866f-484d-80f5-8e11d743ae3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080941615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1080941615
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3676932614
Short name T795
Test name
Test status
Simulation time 6065659013 ps
CPU time 26.7 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:37 PM PDT 24
Peak memory 219904 kb
Host smart-45bf135e-8144-47ff-9598-075f5a867075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676932614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3676932614
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1835418080
Short name T789
Test name
Test status
Simulation time 16559666447 ps
CPU time 5.78 seconds
Started May 26 12:56:11 PM PDT 24
Finished May 26 12:56:18 PM PDT 24
Peak memory 216044 kb
Host smart-0a8b8547-9674-4745-bb04-da5ee4f562c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835418080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1835418080
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1517028086
Short name T365
Test name
Test status
Simulation time 75663832 ps
CPU time 0.96 seconds
Started May 26 12:56:12 PM PDT 24
Finished May 26 12:56:15 PM PDT 24
Peak memory 207640 kb
Host smart-2696faf7-4077-44bf-91a6-7e2fe5464f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517028086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1517028086
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3567748285
Short name T350
Test name
Test status
Simulation time 91298389 ps
CPU time 0.88 seconds
Started May 26 12:56:09 PM PDT 24
Finished May 26 12:56:10 PM PDT 24
Peak memory 205520 kb
Host smart-e95596f5-1de5-4bc1-9ecb-17fbb05c57b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567748285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3567748285
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.220183191
Short name T508
Test name
Test status
Simulation time 48039312231 ps
CPU time 35.22 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 12:57:00 PM PDT 24
Peak memory 218592 kb
Host smart-9747008f-5c45-41db-a8be-b5e0a76be73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220183191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.220183191
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2986038697
Short name T464
Test name
Test status
Simulation time 47204924 ps
CPU time 0.71 seconds
Started May 26 12:56:22 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 205576 kb
Host smart-58366455-903f-4d90-938d-7f4f562a08b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986038697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2986038697
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1690907006
Short name T89
Test name
Test status
Simulation time 520832166 ps
CPU time 2.75 seconds
Started May 26 12:56:17 PM PDT 24
Finished May 26 12:56:21 PM PDT 24
Peak memory 218416 kb
Host smart-d43965c0-31a1-43df-aecb-380c5eb3a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690907006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1690907006
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2970109312
Short name T72
Test name
Test status
Simulation time 65985966 ps
CPU time 0.79 seconds
Started May 26 12:56:22 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 206688 kb
Host smart-f60d5698-08bf-4691-8a23-d9728bbc7873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970109312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2970109312
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2568964752
Short name T802
Test name
Test status
Simulation time 94145618618 ps
CPU time 84.78 seconds
Started May 26 12:56:20 PM PDT 24
Finished May 26 12:57:46 PM PDT 24
Peak memory 235436 kb
Host smart-59738ce5-4d4e-4346-93eb-60423bc9ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568964752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2568964752
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2984827828
Short name T74
Test name
Test status
Simulation time 12025877044 ps
CPU time 41.55 seconds
Started May 26 12:56:24 PM PDT 24
Finished May 26 12:57:07 PM PDT 24
Peak memory 248944 kb
Host smart-a1bde5e6-6c78-464b-9d25-80c89692efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984827828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2984827828
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.28355975
Short name T20
Test name
Test status
Simulation time 113573448766 ps
CPU time 289.61 seconds
Started May 26 12:56:20 PM PDT 24
Finished May 26 01:01:11 PM PDT 24
Peak memory 253496 kb
Host smart-09c5f4f5-84ab-4c99-aa94-8751849d4b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28355975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.28355975
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2796766124
Short name T142
Test name
Test status
Simulation time 1539756567 ps
CPU time 12.32 seconds
Started May 26 12:56:22 PM PDT 24
Finished May 26 12:56:36 PM PDT 24
Peak memory 224248 kb
Host smart-58dbfef8-27df-4523-910e-fd7fe3973acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796766124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2796766124
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1371477941
Short name T762
Test name
Test status
Simulation time 278685802 ps
CPU time 5.13 seconds
Started May 26 12:56:24 PM PDT 24
Finished May 26 12:56:31 PM PDT 24
Peak memory 218932 kb
Host smart-bb05e62f-0228-4b46-8529-37fc14cd1b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371477941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1371477941
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3553783403
Short name T652
Test name
Test status
Simulation time 27439615856 ps
CPU time 89.73 seconds
Started May 26 12:56:21 PM PDT 24
Finished May 26 12:57:52 PM PDT 24
Peak memory 242020 kb
Host smart-45689212-c059-4934-8737-fe6959d0d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553783403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3553783403
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1869354000
Short name T507
Test name
Test status
Simulation time 112038203 ps
CPU time 2.92 seconds
Started May 26 12:56:19 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 233592 kb
Host smart-449ddf68-3212-4723-abf9-5d63ee965363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869354000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1869354000
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3761285299
Short name T218
Test name
Test status
Simulation time 1016806600 ps
CPU time 7.49 seconds
Started May 26 12:56:22 PM PDT 24
Finished May 26 12:56:31 PM PDT 24
Peak memory 240688 kb
Host smart-75605643-d280-42f2-8044-ab8ce0e77b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761285299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3761285299
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1886280562
Short name T582
Test name
Test status
Simulation time 228726536 ps
CPU time 4.41 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 219520 kb
Host smart-80a3e05c-0827-40e2-b604-a8d3dcdd6385
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1886280562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1886280562
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.888910604
Short name T861
Test name
Test status
Simulation time 738655332 ps
CPU time 0.96 seconds
Started May 26 12:56:19 PM PDT 24
Finished May 26 12:56:22 PM PDT 24
Peak memory 206292 kb
Host smart-f2d397a1-00c4-4c3c-b4b7-0652903d2714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888910604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.888910604
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.391436796
Short name T337
Test name
Test status
Simulation time 9523646856 ps
CPU time 17.74 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 216120 kb
Host smart-288800d0-371f-46a0-ab12-e81c408cc7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391436796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.391436796
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2362471415
Short name T566
Test name
Test status
Simulation time 3891640531 ps
CPU time 6.65 seconds
Started May 26 12:56:18 PM PDT 24
Finished May 26 12:56:26 PM PDT 24
Peak memory 216132 kb
Host smart-b2caddd6-98a3-4953-8aa6-a37e76995333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362471415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2362471415
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2512457552
Short name T379
Test name
Test status
Simulation time 718198409 ps
CPU time 4.13 seconds
Started May 26 12:56:18 PM PDT 24
Finished May 26 12:56:24 PM PDT 24
Peak memory 216120 kb
Host smart-d8957fc5-30c2-441e-879c-10f5e55399cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512457552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2512457552
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2358882816
Short name T483
Test name
Test status
Simulation time 86730249 ps
CPU time 0.86 seconds
Started May 26 12:56:23 PM PDT 24
Finished May 26 12:56:26 PM PDT 24
Peak memory 205548 kb
Host smart-d0fab4b2-473a-49d0-b47e-b9abb98e5750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358882816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2358882816
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2257672955
Short name T756
Test name
Test status
Simulation time 2105600095 ps
CPU time 8.56 seconds
Started May 26 12:56:17 PM PDT 24
Finished May 26 12:56:27 PM PDT 24
Peak memory 229420 kb
Host smart-1a237191-e393-42bd-a35c-0be043602bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257672955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2257672955
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3093016041
Short name T810
Test name
Test status
Simulation time 11498425 ps
CPU time 0.71 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:29 PM PDT 24
Peak memory 204700 kb
Host smart-f03b895f-bbd1-49c5-a447-2bfc0d4cab22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093016041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3093016041
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.910499705
Short name T99
Test name
Test status
Simulation time 834237316 ps
CPU time 4.85 seconds
Started May 26 12:56:28 PM PDT 24
Finished May 26 12:56:35 PM PDT 24
Peak memory 221276 kb
Host smart-1ffa83fe-7f37-4b89-b2f1-fde1d089c17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910499705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.910499705
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2258407916
Short name T577
Test name
Test status
Simulation time 14650869 ps
CPU time 0.8 seconds
Started May 26 12:56:28 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 206328 kb
Host smart-dce7b90b-2ca9-4a02-bec1-f3c2b79f6ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258407916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2258407916
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.668923021
Short name T777
Test name
Test status
Simulation time 11000608103 ps
CPU time 75.46 seconds
Started May 26 12:56:28 PM PDT 24
Finished May 26 12:57:45 PM PDT 24
Peak memory 249064 kb
Host smart-fe6c538d-8101-4c90-824c-0efd2e188aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668923021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.668923021
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3381516772
Short name T334
Test name
Test status
Simulation time 2981243143 ps
CPU time 18.81 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 217036 kb
Host smart-97f6c5ee-ec9d-40ab-88fd-038934e2d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381516772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3381516772
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1967297949
Short name T37
Test name
Test status
Simulation time 996998262 ps
CPU time 9.84 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:56:41 PM PDT 24
Peak memory 240760 kb
Host smart-fe7be947-c3cb-452f-abe3-2d7c1d076db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967297949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1967297949
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.278916342
Short name T73
Test name
Test status
Simulation time 93068118 ps
CPU time 2.88 seconds
Started May 26 12:56:30 PM PDT 24
Finished May 26 12:56:34 PM PDT 24
Peak memory 218512 kb
Host smart-631cbcf7-159d-44e9-83e7-9047e1b25f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278916342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.278916342
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3973209442
Short name T769
Test name
Test status
Simulation time 1929388417 ps
CPU time 4.55 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 218704 kb
Host smart-23f11a14-7cf1-4eeb-9b85-85c2a7c3ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973209442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3973209442
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.220167455
Short name T222
Test name
Test status
Simulation time 47597076431 ps
CPU time 13.8 seconds
Started May 26 12:56:28 PM PDT 24
Finished May 26 12:56:43 PM PDT 24
Peak memory 233816 kb
Host smart-753cd0ac-ff20-4362-b74d-9b0d82edcf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220167455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.220167455
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1560161818
Short name T526
Test name
Test status
Simulation time 394495996 ps
CPU time 3.94 seconds
Started May 26 12:56:31 PM PDT 24
Finished May 26 12:56:36 PM PDT 24
Peak memory 220428 kb
Host smart-e8bc3983-1167-4f5d-adb8-59362836f7d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1560161818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1560161818
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.990892559
Short name T610
Test name
Test status
Simulation time 4816168858 ps
CPU time 26.83 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:55 PM PDT 24
Peak memory 216148 kb
Host smart-e53027b2-67d2-42f4-bbbf-92b1028fa83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990892559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.990892559
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2850095929
Short name T524
Test name
Test status
Simulation time 85302745 ps
CPU time 0.93 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:29 PM PDT 24
Peak memory 205644 kb
Host smart-4c221702-1e5d-4ef9-b98a-3c4b9df2cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850095929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2850095929
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3972197921
Short name T419
Test name
Test status
Simulation time 537658250 ps
CPU time 1.84 seconds
Started May 26 12:56:30 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 216096 kb
Host smart-6254e221-8eba-4129-96f1-0a31eb4c71b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972197921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3972197921
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1947572044
Short name T8
Test name
Test status
Simulation time 177612191 ps
CPU time 0.85 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 205628 kb
Host smart-a9a13fd5-a4c6-4d29-b780-9fa9a1eb7344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947572044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1947572044
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1407976559
Short name T835
Test name
Test status
Simulation time 748003945 ps
CPU time 3.19 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 233784 kb
Host smart-81429f95-6dd7-49cf-b97e-73757c611663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407976559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1407976559
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.332766926
Short name T837
Test name
Test status
Simulation time 11728746 ps
CPU time 0.72 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:38 PM PDT 24
Peak memory 205308 kb
Host smart-e1687431-1698-49cb-b5f3-c5502dbaf383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332766926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.332766926
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1898602382
Short name T181
Test name
Test status
Simulation time 77150808 ps
CPU time 2.13 seconds
Started May 26 12:56:30 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 218564 kb
Host smart-ffd16a5b-4d5c-406e-8163-c59fe4a85e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898602382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1898602382
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.437730824
Short name T517
Test name
Test status
Simulation time 71694687 ps
CPU time 0.8 seconds
Started May 26 12:56:30 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 206400 kb
Host smart-6c5bae6d-ebd6-4536-aa6f-d8e240921c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437730824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.437730824
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1889589070
Short name T465
Test name
Test status
Simulation time 24423102091 ps
CPU time 88.48 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:58:05 PM PDT 24
Peak memory 237788 kb
Host smart-615aba92-3dad-4777-96a5-318f5d0c6a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889589070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1889589070
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.909155279
Short name T125
Test name
Test status
Simulation time 79718227622 ps
CPU time 151.7 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:59:11 PM PDT 24
Peak memory 239492 kb
Host smart-27ae9354-7aea-4921-a77d-f6daaf99ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909155279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.909155279
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3398862881
Short name T689
Test name
Test status
Simulation time 25096417718 ps
CPU time 214 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 01:00:13 PM PDT 24
Peak memory 249064 kb
Host smart-dc48bead-a98f-4f50-9d1e-948edf5a259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398862881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3398862881
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.759905808
Short name T691
Test name
Test status
Simulation time 3694345875 ps
CPU time 10.24 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:39 PM PDT 24
Peak memory 224272 kb
Host smart-56295603-34ed-4d30-afc7-b9f4aca9f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759905808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.759905808
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.173216000
Short name T649
Test name
Test status
Simulation time 4672906457 ps
CPU time 4.92 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:33 PM PDT 24
Peak memory 233596 kb
Host smart-730605df-d2c1-4a4d-a211-86cf0cbfcb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173216000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.173216000
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3859695891
Short name T215
Test name
Test status
Simulation time 208192118 ps
CPU time 3.53 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:56:34 PM PDT 24
Peak memory 233868 kb
Host smart-5d1e0b48-9ec9-45f4-9392-280b3420fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859695891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3859695891
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2560552273
Short name T659
Test name
Test status
Simulation time 230073735 ps
CPU time 2.59 seconds
Started May 26 12:56:30 PM PDT 24
Finished May 26 12:56:34 PM PDT 24
Peak memory 216568 kb
Host smart-88deb7ee-b761-4eed-9229-ca92831ebb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560552273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2560552273
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.468819057
Short name T936
Test name
Test status
Simulation time 29836669 ps
CPU time 2.1 seconds
Started May 26 12:56:29 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 218352 kb
Host smart-07e3fdd5-90d9-4a58-9838-b223a6b8d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468819057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.468819057
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4133709289
Short name T915
Test name
Test status
Simulation time 95840434 ps
CPU time 3.52 seconds
Started May 26 12:56:31 PM PDT 24
Finished May 26 12:56:35 PM PDT 24
Peak memory 220320 kb
Host smart-8e8edb3a-70f7-49dc-ae1f-105214628d8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4133709289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4133709289
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2420725392
Short name T647
Test name
Test status
Simulation time 183857216 ps
CPU time 1.02 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:39 PM PDT 24
Peak memory 206696 kb
Host smart-2e8a3ef0-3deb-4bd4-98b1-2090531dbdb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420725392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2420725392
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4152963900
Short name T716
Test name
Test status
Simulation time 2010436396 ps
CPU time 5.8 seconds
Started May 26 12:56:26 PM PDT 24
Finished May 26 12:56:34 PM PDT 24
Peak memory 216260 kb
Host smart-2e615c0e-c20e-4d0d-9b24-15586902732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152963900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4152963900
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.911374357
Short name T509
Test name
Test status
Simulation time 189869544 ps
CPU time 2.23 seconds
Started May 26 12:56:28 PM PDT 24
Finished May 26 12:56:32 PM PDT 24
Peak memory 215992 kb
Host smart-35ab78f0-62f0-4a01-8cb9-80e003c1f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911374357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.911374357
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3968516176
Short name T459
Test name
Test status
Simulation time 60989311 ps
CPU time 1.08 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 206728 kb
Host smart-6d0ee8f7-e84b-4696-a6b9-f4278b27e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968516176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3968516176
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1056794606
Short name T846
Test name
Test status
Simulation time 82511904 ps
CPU time 0.71 seconds
Started May 26 12:56:27 PM PDT 24
Finished May 26 12:56:30 PM PDT 24
Peak memory 205476 kb
Host smart-f5ca66a1-8e5d-4688-83a1-474aa2b87517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056794606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1056794606
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2235652960
Short name T43
Test name
Test status
Simulation time 11267660189 ps
CPU time 8.9 seconds
Started May 26 12:56:32 PM PDT 24
Finished May 26 12:56:41 PM PDT 24
Peak memory 233852 kb
Host smart-cd46a736-bdcd-4396-8580-b6c562be0e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235652960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2235652960
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1805397841
Short name T380
Test name
Test status
Simulation time 15008591 ps
CPU time 0.77 seconds
Started May 26 12:56:39 PM PDT 24
Finished May 26 12:56:41 PM PDT 24
Peak memory 204728 kb
Host smart-8e420204-36fa-4c30-88fc-92362efce8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805397841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1805397841
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3973608758
Short name T312
Test name
Test status
Simulation time 1977943705 ps
CPU time 4.31 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:41 PM PDT 24
Peak memory 218616 kb
Host smart-a40027a5-2e5a-4b5e-909d-1394946dd543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973608758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3973608758
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.310092078
Short name T56
Test name
Test status
Simulation time 23378362 ps
CPU time 0.78 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:37 PM PDT 24
Peak memory 206636 kb
Host smart-7662eaac-d21c-4df9-9766-e4d90c68cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310092078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.310092078
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4241629168
Short name T715
Test name
Test status
Simulation time 3920860152 ps
CPU time 42.77 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:57:22 PM PDT 24
Peak memory 252056 kb
Host smart-5f3f27cc-5773-4a51-bb7c-40a366b5b71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241629168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4241629168
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3057583691
Short name T134
Test name
Test status
Simulation time 12310800580 ps
CPU time 36.39 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:57:15 PM PDT 24
Peak memory 239088 kb
Host smart-737e27aa-6a3e-45b4-b781-d70859bcb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057583691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3057583691
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4195929673
Short name T180
Test name
Test status
Simulation time 43787448234 ps
CPU time 91.52 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:58:09 PM PDT 24
Peak memory 256184 kb
Host smart-2d823420-84c9-476e-bfab-74a753d9837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195929673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4195929673
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2210337712
Short name T324
Test name
Test status
Simulation time 486779508 ps
CPU time 13.57 seconds
Started May 26 12:56:39 PM PDT 24
Finished May 26 12:56:54 PM PDT 24
Peak memory 235500 kb
Host smart-f8cd791b-f3b3-44f4-9302-2f221d122039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210337712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2210337712
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3140188951
Short name T194
Test name
Test status
Simulation time 888705957 ps
CPU time 5.62 seconds
Started May 26 12:56:41 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 233676 kb
Host smart-108d91d9-e8e6-4f56-8fdd-efd028281403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140188951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3140188951
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.886994620
Short name T174
Test name
Test status
Simulation time 1984443232 ps
CPU time 17.8 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:56:55 PM PDT 24
Peak memory 234172 kb
Host smart-c6fed986-1dab-45d5-a961-5a4b8a65993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886994620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.886994620
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3774831109
Short name T213
Test name
Test status
Simulation time 1480229409 ps
CPU time 9.82 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:56:47 PM PDT 24
Peak memory 232480 kb
Host smart-c2625732-594d-4d17-896a-24b3082c2efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774831109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3774831109
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2748998548
Short name T772
Test name
Test status
Simulation time 218363125 ps
CPU time 3.65 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:42 PM PDT 24
Peak memory 232904 kb
Host smart-a4b37498-7981-4da9-a6e2-9c5b5499f8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748998548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2748998548
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1746391771
Short name T898
Test name
Test status
Simulation time 979237102 ps
CPU time 10.3 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 222084 kb
Host smart-0e3d5f0c-62c0-4167-90d8-7be407ecba7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1746391771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1746391771
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.575675839
Short name T416
Test name
Test status
Simulation time 10052422576 ps
CPU time 67.83 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:57:45 PM PDT 24
Peak memory 249080 kb
Host smart-a7331bcd-7fb8-48fd-8a68-b116cdaa0343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575675839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.575675839
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3875303515
Short name T672
Test name
Test status
Simulation time 7667740099 ps
CPU time 20.48 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:56:58 PM PDT 24
Peak memory 216140 kb
Host smart-5d956959-0901-4c14-ac11-128cda4439a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875303515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3875303515
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2839674087
Short name T845
Test name
Test status
Simulation time 1941592547 ps
CPU time 5.65 seconds
Started May 26 12:56:41 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 216096 kb
Host smart-931fde4e-d753-46dc-bb9d-9574245ca2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839674087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2839674087
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1478118521
Short name T641
Test name
Test status
Simulation time 80480389 ps
CPU time 1.18 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:40 PM PDT 24
Peak memory 215936 kb
Host smart-93528a8b-28b8-4100-8585-77635908762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478118521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1478118521
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2027132943
Short name T83
Test name
Test status
Simulation time 106879716 ps
CPU time 0.97 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:56:39 PM PDT 24
Peak memory 205516 kb
Host smart-9103e033-4f80-4568-8d53-cb88a4583bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027132943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2027132943
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3134149419
Short name T198
Test name
Test status
Simulation time 3949420085 ps
CPU time 7.87 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 218696 kb
Host smart-566673e2-567f-419e-84f9-51151ae1f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134149419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3134149419
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2807623063
Short name T495
Test name
Test status
Simulation time 14871142 ps
CPU time 0.76 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 12:56:49 PM PDT 24
Peak memory 205708 kb
Host smart-1533024e-abb1-4a0c-9bec-293be526dbc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807623063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2807623063
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4264362869
Short name T782
Test name
Test status
Simulation time 107304475 ps
CPU time 2.78 seconds
Started May 26 12:56:41 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 218408 kb
Host smart-b4557694-ea40-46b2-ae59-c03bc6757842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264362869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4264362869
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4276355593
Short name T363
Test name
Test status
Simulation time 51507041 ps
CPU time 0.83 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:39 PM PDT 24
Peak memory 206392 kb
Host smart-b606d791-f5b0-4596-aff8-9c97740a31eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276355593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4276355593
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3727403938
Short name T251
Test name
Test status
Simulation time 14953779502 ps
CPU time 116.02 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:58:35 PM PDT 24
Peak memory 255752 kb
Host smart-8e18e73d-a59b-4f84-a6d6-1f1df2839438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727403938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3727403938
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1778454871
Short name T290
Test name
Test status
Simulation time 27320012633 ps
CPU time 26.82 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 12:57:15 PM PDT 24
Peak memory 232576 kb
Host smart-09f84b97-8a1b-48a1-90ea-195f1f49c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778454871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1778454871
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3830244920
Short name T951
Test name
Test status
Simulation time 4804486056 ps
CPU time 18.82 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:57 PM PDT 24
Peak memory 240072 kb
Host smart-46cf845e-d93e-48f9-a8c7-5f438556746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830244920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3830244920
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2944425054
Short name T3
Test name
Test status
Simulation time 393892929 ps
CPU time 4.3 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:56:43 PM PDT 24
Peak memory 234496 kb
Host smart-029d2379-778c-4002-a6fb-6fe3e58d5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944425054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2944425054
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1448602742
Short name T279
Test name
Test status
Simulation time 2342409047 ps
CPU time 12.46 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:56:51 PM PDT 24
Peak memory 224288 kb
Host smart-fae6236e-c0b1-4568-b4e8-db4e92c31186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448602742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1448602742
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2637150585
Short name T612
Test name
Test status
Simulation time 1779457028 ps
CPU time 9.06 seconds
Started May 26 12:56:34 PM PDT 24
Finished May 26 12:56:44 PM PDT 24
Peak memory 236248 kb
Host smart-74a92f1b-ec1e-467a-9423-c42757108c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637150585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2637150585
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.189219998
Short name T917
Test name
Test status
Simulation time 34274734 ps
CPU time 2.52 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:41 PM PDT 24
Peak memory 221340 kb
Host smart-9f427402-b849-43a3-af14-3bd371d331d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189219998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.189219998
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.136694427
Short name T829
Test name
Test status
Simulation time 7729022625 ps
CPU time 5.55 seconds
Started May 26 12:56:36 PM PDT 24
Finished May 26 12:56:42 PM PDT 24
Peak memory 219036 kb
Host smart-b4b87dfe-c3ac-4231-b2dc-ecd11c5495db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=136694427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.136694427
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.177025813
Short name T154
Test name
Test status
Simulation time 113421133958 ps
CPU time 286.75 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 01:01:35 PM PDT 24
Peak memory 259080 kb
Host smart-da073dd2-c994-4522-ba2b-5e8e60358f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177025813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.177025813
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3996472018
Short name T340
Test name
Test status
Simulation time 9215792809 ps
CPU time 48.06 seconds
Started May 26 12:56:38 PM PDT 24
Finished May 26 12:57:28 PM PDT 24
Peak memory 216116 kb
Host smart-8a0ecf1c-0736-423d-9755-bb42527bafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996472018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3996472018
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3115564748
Short name T130
Test name
Test status
Simulation time 537925344 ps
CPU time 1.92 seconds
Started May 26 12:56:37 PM PDT 24
Finished May 26 12:56:40 PM PDT 24
Peak memory 215764 kb
Host smart-a93d35c3-8ee2-46f7-aae1-5a53414d9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115564748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3115564748
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.927685721
Short name T700
Test name
Test status
Simulation time 178093496 ps
CPU time 0.89 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:37 PM PDT 24
Peak memory 206224 kb
Host smart-3777bcc9-2746-4b19-a27c-6f3c4e19df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927685721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.927685721
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2482125820
Short name T34
Test name
Test status
Simulation time 27476406 ps
CPU time 0.7 seconds
Started May 26 12:56:34 PM PDT 24
Finished May 26 12:56:36 PM PDT 24
Peak memory 205496 kb
Host smart-f828d362-edd6-412a-800a-3a634e112953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482125820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2482125820
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2063140328
Short name T673
Test name
Test status
Simulation time 1756993451 ps
CPU time 8.13 seconds
Started May 26 12:56:35 PM PDT 24
Finished May 26 12:56:45 PM PDT 24
Peak memory 229128 kb
Host smart-e17ee672-f250-455b-8a3b-2932e3db084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063140328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2063140328
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3371500210
Short name T394
Test name
Test status
Simulation time 14897296 ps
CPU time 0.73 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:46 PM PDT 24
Peak memory 204728 kb
Host smart-9afdc7f7-9e42-4b47-9a90-c2d46292904c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371500210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3371500210
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3043672269
Short name T705
Test name
Test status
Simulation time 182575853 ps
CPU time 2.11 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:47 PM PDT 24
Peak memory 216008 kb
Host smart-bb9472fb-2f59-4bb7-b56e-06ffc7db6d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043672269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3043672269
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2336560650
Short name T494
Test name
Test status
Simulation time 66199847 ps
CPU time 0.79 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:46 PM PDT 24
Peak memory 206324 kb
Host smart-245b8e82-9b54-4949-8332-e4d653976eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336560650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2336560650
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1143422075
Short name T299
Test name
Test status
Simulation time 1611186086 ps
CPU time 15.04 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:57:00 PM PDT 24
Peak memory 240732 kb
Host smart-bc409972-24b4-47b0-a41e-edcc023514a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143422075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1143422075
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1051471285
Short name T261
Test name
Test status
Simulation time 14061195273 ps
CPU time 215.62 seconds
Started May 26 12:56:46 PM PDT 24
Finished May 26 01:00:23 PM PDT 24
Peak memory 256460 kb
Host smart-ec3a62d0-3335-4fea-8763-b2b25e9bf86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051471285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1051471285
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.504110489
Short name T165
Test name
Test status
Simulation time 7830997509 ps
CPU time 44.93 seconds
Started May 26 12:56:46 PM PDT 24
Finished May 26 12:57:31 PM PDT 24
Peak memory 257164 kb
Host smart-438764e2-04e4-4d6e-a74f-45ba9c0e1b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504110489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.504110489
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1219105304
Short name T563
Test name
Test status
Simulation time 8694966543 ps
CPU time 18.04 seconds
Started May 26 12:56:45 PM PDT 24
Finished May 26 12:57:04 PM PDT 24
Peak memory 228640 kb
Host smart-61f29370-0f3f-459e-baaa-2343adda13b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219105304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1219105304
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4011775668
Short name T690
Test name
Test status
Simulation time 1628527600 ps
CPU time 14.54 seconds
Started May 26 12:56:45 PM PDT 24
Finished May 26 12:57:00 PM PDT 24
Peak memory 234004 kb
Host smart-767b60f6-599a-4f1c-a0c3-d75310ba93a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011775668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4011775668
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1200530599
Short name T621
Test name
Test status
Simulation time 3393699558 ps
CPU time 22.72 seconds
Started May 26 12:56:46 PM PDT 24
Finished May 26 12:57:09 PM PDT 24
Peak memory 238904 kb
Host smart-ee5bc333-7203-42ec-af0f-8d551373f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200530599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1200530599
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1863738381
Short name T157
Test name
Test status
Simulation time 13559355495 ps
CPU time 21.59 seconds
Started May 26 12:56:43 PM PDT 24
Finished May 26 12:57:05 PM PDT 24
Peak memory 221228 kb
Host smart-6668d60c-8bb7-484e-8bc2-9624fb41e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863738381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1863738381
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.581824253
Short name T759
Test name
Test status
Simulation time 7588926659 ps
CPU time 12.85 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:57 PM PDT 24
Peak memory 232428 kb
Host smart-224cde6c-69bc-4d1e-92cf-82045bd5fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581824253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.581824253
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.772450952
Short name T71
Test name
Test status
Simulation time 6524909489 ps
CPU time 13.69 seconds
Started May 26 12:56:46 PM PDT 24
Finished May 26 12:57:01 PM PDT 24
Peak memory 219112 kb
Host smart-c1f089bf-e133-453e-938e-afedfbe89da8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=772450952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.772450952
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3685631398
Short name T304
Test name
Test status
Simulation time 41939634374 ps
CPU time 190.11 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:59:55 PM PDT 24
Peak memory 265476 kb
Host smart-01fb9ef0-fcb8-45fb-8886-1c68d118b81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685631398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3685631398
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1605146650
Short name T897
Test name
Test status
Simulation time 2516255035 ps
CPU time 15.73 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 12:57:03 PM PDT 24
Peak memory 216188 kb
Host smart-9f384eba-06b7-4558-bb63-2c8dad38dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605146650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1605146650
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.228691160
Short name T928
Test name
Test status
Simulation time 106185148 ps
CPU time 1.29 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:47 PM PDT 24
Peak memory 207596 kb
Host smart-7eb17f6d-80b5-41be-a9db-2145ac13c4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228691160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.228691160
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1802259645
Short name T757
Test name
Test status
Simulation time 34239817 ps
CPU time 0.87 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 12:56:49 PM PDT 24
Peak memory 206436 kb
Host smart-b6241936-8edc-4bdf-a377-1b89aabb3b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802259645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1802259645
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.547988671
Short name T823
Test name
Test status
Simulation time 15135819 ps
CPU time 0.73 seconds
Started May 26 12:56:47 PM PDT 24
Finished May 26 12:56:48 PM PDT 24
Peak memory 205452 kb
Host smart-f3f17e6d-c2f7-40a9-8ba0-4b6f0db6bfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547988671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.547988671
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2555460095
Short name T156
Test name
Test status
Simulation time 419685960 ps
CPU time 4.59 seconds
Started May 26 12:56:44 PM PDT 24
Finished May 26 12:56:50 PM PDT 24
Peak memory 220500 kb
Host smart-f923339c-6cbc-4a02-ba03-1b9425ec7871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555460095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2555460095
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.781771098
Short name T128
Test name
Test status
Simulation time 41025651 ps
CPU time 0.74 seconds
Started May 26 12:52:25 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 204728 kb
Host smart-566e5a00-0381-46c7-b3fd-0c2a194ed4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781771098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.781771098
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2555971122
Short name T223
Test name
Test status
Simulation time 898585373 ps
CPU time 5.09 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:30 PM PDT 24
Peak memory 218512 kb
Host smart-c10eda65-509e-4c3d-a427-29524ac351cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555971122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2555971122
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3276305475
Short name T421
Test name
Test status
Simulation time 19994812 ps
CPU time 0.79 seconds
Started May 26 12:52:25 PM PDT 24
Finished May 26 12:52:27 PM PDT 24
Peak memory 206344 kb
Host smart-3fba0443-b634-49f2-93b0-55930b194f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276305475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3276305475
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1542543836
Short name T953
Test name
Test status
Simulation time 13557088440 ps
CPU time 57.31 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:53:21 PM PDT 24
Peak memory 248916 kb
Host smart-e05a52e0-a6f4-413a-957b-37d9d7a8bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542543836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1542543836
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1091674590
Short name T395
Test name
Test status
Simulation time 9155005498 ps
CPU time 90.53 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:53:55 PM PDT 24
Peak memory 249024 kb
Host smart-f953e7df-7683-433f-8bd1-49c8178a93d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091674590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1091674590
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1468656226
Short name T253
Test name
Test status
Simulation time 11591415757 ps
CPU time 142.94 seconds
Started May 26 12:52:25 PM PDT 24
Finished May 26 12:54:49 PM PDT 24
Peak memory 253780 kb
Host smart-41e78c0b-e040-4417-b709-36ea2c4b10cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468656226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1468656226
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1757637881
Short name T878
Test name
Test status
Simulation time 274243232 ps
CPU time 7.86 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:33 PM PDT 24
Peak memory 232432 kb
Host smart-c39be0c6-4db8-4491-b793-d6355e534f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757637881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1757637881
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3894294016
Short name T743
Test name
Test status
Simulation time 329352743 ps
CPU time 5.87 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:52:29 PM PDT 24
Peak memory 234212 kb
Host smart-59772d18-0072-4321-8fd2-a28f1b0ca10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894294016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3894294016
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3773560069
Short name T216
Test name
Test status
Simulation time 9292219489 ps
CPU time 8.54 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:33 PM PDT 24
Peak memory 219048 kb
Host smart-923da6bc-1bd1-4146-83a4-765651908f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773560069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3773560069
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3309929381
Short name T184
Test name
Test status
Simulation time 7015220279 ps
CPU time 15.4 seconds
Started May 26 12:52:27 PM PDT 24
Finished May 26 12:52:43 PM PDT 24
Peak memory 240784 kb
Host smart-18ceff30-cb8b-47b1-be73-8dc9b307c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309929381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3309929381
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.386074231
Short name T712
Test name
Test status
Simulation time 142286489 ps
CPU time 3.76 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:28 PM PDT 24
Peak memory 218592 kb
Host smart-93315976-b467-4576-a7dc-503fcadccb66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386074231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.386074231
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2748766864
Short name T934
Test name
Test status
Simulation time 19042985077 ps
CPU time 170.9 seconds
Started May 26 12:52:26 PM PDT 24
Finished May 26 12:55:17 PM PDT 24
Peak memory 255072 kb
Host smart-559b2e00-4b1d-44ab-8cba-62c06e05cb0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748766864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2748766864
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2894990101
Short name T808
Test name
Test status
Simulation time 5972405447 ps
CPU time 28.5 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:52:52 PM PDT 24
Peak memory 216252 kb
Host smart-981ceb8e-7df1-4eff-8d6e-9de85d9d53d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894990101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2894990101
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1182456662
Short name T812
Test name
Test status
Simulation time 20355619369 ps
CPU time 12.94 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:52:37 PM PDT 24
Peak memory 216032 kb
Host smart-52ad907d-1baa-4da2-8da5-1d9979c93417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182456662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1182456662
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2591823681
Short name T18
Test name
Test status
Simulation time 142456819 ps
CPU time 1.81 seconds
Started May 26 12:52:25 PM PDT 24
Finished May 26 12:52:27 PM PDT 24
Peak memory 216096 kb
Host smart-850e6337-e6f9-4098-9277-eccb908f25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591823681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2591823681
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1453467369
Short name T697
Test name
Test status
Simulation time 33320599 ps
CPU time 0.78 seconds
Started May 26 12:52:23 PM PDT 24
Finished May 26 12:52:24 PM PDT 24
Peak memory 205548 kb
Host smart-a3eefe60-28a6-4f88-87e1-51607d7f8215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453467369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1453467369
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1955248836
Short name T42
Test name
Test status
Simulation time 3264198977 ps
CPU time 6.58 seconds
Started May 26 12:52:24 PM PDT 24
Finished May 26 12:52:31 PM PDT 24
Peak memory 216460 kb
Host smart-972a8e93-fb0f-44ee-b4a8-49d0d6cf9b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955248836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1955248836
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3247911773
Short name T516
Test name
Test status
Simulation time 112437003 ps
CPU time 0.75 seconds
Started May 26 12:52:36 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 205592 kb
Host smart-451efdeb-1dd4-4ce7-bf17-e64f061f58fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247911773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
247911773
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4142940364
Short name T544
Test name
Test status
Simulation time 202917770 ps
CPU time 2.51 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:37 PM PDT 24
Peak memory 218392 kb
Host smart-ed4362f4-a2cf-47fb-ad35-b2bc2dd93568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142940364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4142940364
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2627236493
Short name T924
Test name
Test status
Simulation time 13717956 ps
CPU time 0.76 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:35 PM PDT 24
Peak memory 205396 kb
Host smart-b8139d50-f07d-4524-be85-d5eb8c1c78f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627236493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2627236493
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.323246039
Short name T231
Test name
Test status
Simulation time 113373098812 ps
CPU time 192.22 seconds
Started May 26 12:52:36 PM PDT 24
Finished May 26 12:55:49 PM PDT 24
Peak memory 255844 kb
Host smart-db20295c-9ed1-4299-9ec6-c84252c66eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323246039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.323246039
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1654028615
Short name T170
Test name
Test status
Simulation time 2733025772 ps
CPU time 70.95 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:53:44 PM PDT 24
Peak memory 249620 kb
Host smart-f795d970-0fd3-431c-9dc8-232e63e534a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654028615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1654028615
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2903380545
Short name T578
Test name
Test status
Simulation time 387034684411 ps
CPU time 221.54 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:56:16 PM PDT 24
Peak memory 256316 kb
Host smart-b127c7fc-0d12-4207-96af-eb402b82f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903380545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2903380545
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.322415520
Short name T489
Test name
Test status
Simulation time 3271720477 ps
CPU time 10.1 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 224284 kb
Host smart-00ad7648-4f54-47be-b22f-1a54b86bf589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322415520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.322415520
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.492534406
Short name T496
Test name
Test status
Simulation time 118690555 ps
CPU time 4.1 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 233616 kb
Host smart-38210cf8-6da7-4fd0-b73a-7c011aa0d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492534406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.492534406
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.213813809
Short name T525
Test name
Test status
Simulation time 16145718280 ps
CPU time 79.91 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:53:54 PM PDT 24
Peak memory 237272 kb
Host smart-9ecf80ee-026f-4f03-aaa8-c1e71c3d7bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213813809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.213813809
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.956681311
Short name T409
Test name
Test status
Simulation time 1755270480 ps
CPU time 5.56 seconds
Started May 26 12:52:35 PM PDT 24
Finished May 26 12:52:42 PM PDT 24
Peak memory 221520 kb
Host smart-b2b621a1-eded-4dd2-adf0-2c26ae43a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956681311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
956681311
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4194648717
Short name T402
Test name
Test status
Simulation time 20707626563 ps
CPU time 16.98 seconds
Started May 26 12:52:36 PM PDT 24
Finished May 26 12:52:54 PM PDT 24
Peak memory 218452 kb
Host smart-387a8f75-fabc-428c-b873-188336e3c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194648717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4194648717
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2844014800
Short name T632
Test name
Test status
Simulation time 316921734 ps
CPU time 3.76 seconds
Started May 26 12:52:32 PM PDT 24
Finished May 26 12:52:36 PM PDT 24
Peak memory 219812 kb
Host smart-385a79e3-618a-4d7b-9ccc-d96120208436
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2844014800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2844014800
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2435765677
Short name T211
Test name
Test status
Simulation time 573596939594 ps
CPU time 575.22 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 01:02:10 PM PDT 24
Peak memory 269484 kb
Host smart-793eb223-a834-4bd7-90dc-1ab58a72afe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435765677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2435765677
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1238940716
Short name T512
Test name
Test status
Simulation time 3323974796 ps
CPU time 25.17 seconds
Started May 26 12:52:32 PM PDT 24
Finished May 26 12:52:58 PM PDT 24
Peak memory 216348 kb
Host smart-8afbd891-9975-4dad-b94e-d938c010a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238940716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1238940716
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2213961942
Short name T613
Test name
Test status
Simulation time 239636907 ps
CPU time 1.72 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:52:37 PM PDT 24
Peak memory 207560 kb
Host smart-8c5f1dd0-e0cd-44c0-9925-b8193a7615f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213961942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2213961942
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2725594958
Short name T865
Test name
Test status
Simulation time 1281160965 ps
CPU time 8.08 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:42 PM PDT 24
Peak memory 216236 kb
Host smart-d7d953af-8e08-4ec6-b99d-4d7fd7d5d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725594958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2725594958
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.470509758
Short name T384
Test name
Test status
Simulation time 255614361 ps
CPU time 0.95 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:35 PM PDT 24
Peak memory 205572 kb
Host smart-f6cbcde9-ad8c-44f3-ac11-759311737131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470509758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.470509758
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1850796253
Short name T314
Test name
Test status
Simulation time 355596927 ps
CPU time 3.51 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 235128 kb
Host smart-847386b4-06d8-4669-838f-14ad881e0451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850796253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1850796253
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3607981782
Short name T58
Test name
Test status
Simulation time 58424779 ps
CPU time 0.73 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:52:42 PM PDT 24
Peak memory 205408 kb
Host smart-97f468d6-ec8b-4f88-9c65-30885f9d3979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607981782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
607981782
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1018102764
Short name T568
Test name
Test status
Simulation time 1719879788 ps
CPU time 18.95 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:53:02 PM PDT 24
Peak memory 233976 kb
Host smart-be2e96c6-eeb0-4a2f-a8f2-b0d98837d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018102764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1018102764
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3602451298
Short name T404
Test name
Test status
Simulation time 41027972 ps
CPU time 0.82 seconds
Started May 26 12:52:37 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 206620 kb
Host smart-77118205-9d9f-403f-906e-30d6ef60e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602451298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3602451298
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.445797467
Short name T239
Test name
Test status
Simulation time 32476717410 ps
CPU time 235.13 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:56:38 PM PDT 24
Peak memory 254796 kb
Host smart-44557136-b237-4174-88cf-d3af1a9d42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445797467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.445797467
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4048051239
Short name T132
Test name
Test status
Simulation time 150260670206 ps
CPU time 682.9 seconds
Started May 26 12:52:43 PM PDT 24
Finished May 26 01:04:07 PM PDT 24
Peak memory 261128 kb
Host smart-8310084d-90d9-4c7d-9a87-fd44a2309c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048051239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4048051239
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3767552478
Short name T549
Test name
Test status
Simulation time 7588968844 ps
CPU time 76.07 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 250284 kb
Host smart-eda6d4e1-4feb-4426-9897-6a1367585909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767552478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3767552478
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3382982809
Short name T331
Test name
Test status
Simulation time 537888415 ps
CPU time 6.59 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:50 PM PDT 24
Peak memory 232532 kb
Host smart-02963a21-e6a7-4ced-ab58-018f3c792efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382982809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3382982809
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3732635711
Short name T503
Test name
Test status
Simulation time 412607211 ps
CPU time 6.7 seconds
Started May 26 12:52:32 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 233288 kb
Host smart-63a33ec1-3ce4-4c00-9368-32fdb6f7dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732635711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3732635711
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1641631130
Short name T553
Test name
Test status
Simulation time 8199779613 ps
CPU time 96.43 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:54:19 PM PDT 24
Peak memory 233044 kb
Host smart-6e8197c5-50f3-4182-902e-68815e01b54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641631130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1641631130
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1677914272
Short name T412
Test name
Test status
Simulation time 172991987 ps
CPU time 3.52 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 232460 kb
Host smart-ba181030-216a-4c25-8a35-fc16b9856429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677914272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1677914272
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.795210947
Short name T585
Test name
Test status
Simulation time 1536805779 ps
CPU time 10.67 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:52:46 PM PDT 24
Peak memory 229736 kb
Host smart-690b6255-945d-4752-80e4-64c774706b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795210947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.795210947
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3243924381
Short name T635
Test name
Test status
Simulation time 942736800 ps
CPU time 10.98 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:54 PM PDT 24
Peak memory 221560 kb
Host smart-4ed19533-13fe-4d4c-a180-9596be9e59f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243924381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3243924381
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.125169974
Short name T45
Test name
Test status
Simulation time 35985170451 ps
CPU time 96.37 seconds
Started May 26 12:52:40 PM PDT 24
Finished May 26 12:54:17 PM PDT 24
Peak memory 249032 kb
Host smart-41e6a328-8b3e-4749-9593-7b7087a07794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125169974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.125169974
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3322670925
Short name T52
Test name
Test status
Simulation time 7372119569 ps
CPU time 19.72 seconds
Started May 26 12:52:35 PM PDT 24
Finished May 26 12:52:55 PM PDT 24
Peak memory 216108 kb
Host smart-7f2e6f6e-78d7-485b-bb47-03a9fe4621b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322670925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3322670925
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3502564878
Short name T809
Test name
Test status
Simulation time 123556738 ps
CPU time 1.08 seconds
Started May 26 12:52:33 PM PDT 24
Finished May 26 12:52:34 PM PDT 24
Peak memory 207404 kb
Host smart-474f2352-02a9-4045-8a15-af78e821049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502564878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3502564878
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3896006474
Short name T868
Test name
Test status
Simulation time 548669840 ps
CPU time 6.83 seconds
Started May 26 12:52:34 PM PDT 24
Finished May 26 12:52:42 PM PDT 24
Peak memory 216192 kb
Host smart-cc2262cb-820d-4ebc-ab0d-a821ebb4dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896006474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3896006474
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2791388376
Short name T619
Test name
Test status
Simulation time 21483317 ps
CPU time 0.78 seconds
Started May 26 12:52:32 PM PDT 24
Finished May 26 12:52:34 PM PDT 24
Peak memory 205516 kb
Host smart-6450d14c-de1d-43dc-b6b9-b149bb176bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791388376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2791388376
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2199796422
Short name T551
Test name
Test status
Simulation time 1610500678 ps
CPU time 5.38 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:49 PM PDT 24
Peak memory 234144 kb
Host smart-cf641c3c-4002-46b8-8f6e-ef1e954bdcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199796422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2199796422
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1407283337
Short name T433
Test name
Test status
Simulation time 13239736 ps
CPU time 0.73 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:52:55 PM PDT 24
Peak memory 204760 kb
Host smart-ff938eeb-5d35-43ce-b7b9-d0a827d18f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407283337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
407283337
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1016074388
Short name T754
Test name
Test status
Simulation time 160197440 ps
CPU time 5.08 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:52:46 PM PDT 24
Peak memory 234852 kb
Host smart-f2b8fd73-b679-4e1c-8b86-5f8b7c79c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016074388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1016074388
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.939136518
Short name T376
Test name
Test status
Simulation time 14383461 ps
CPU time 0.75 seconds
Started May 26 12:52:44 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 206684 kb
Host smart-38cc39e7-07e6-424b-a21c-2605d551376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939136518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.939136518
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2814000614
Short name T25
Test name
Test status
Simulation time 24675533142 ps
CPU time 84.04 seconds
Started May 26 12:52:40 PM PDT 24
Finished May 26 12:54:04 PM PDT 24
Peak memory 256084 kb
Host smart-418230f6-f490-46af-b780-b4357c343170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814000614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2814000614
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.733502630
Short name T230
Test name
Test status
Simulation time 19502620008 ps
CPU time 237.51 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:56:40 PM PDT 24
Peak memory 264348 kb
Host smart-d04082a4-7a03-47ee-8c9e-95f5b12ad67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733502630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.733502630
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3414107139
Short name T124
Test name
Test status
Simulation time 22368874218 ps
CPU time 178.86 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 250772 kb
Host smart-05a33e01-0400-45a3-bf10-98ddc4012649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414107139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3414107139
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3000907585
Short name T484
Test name
Test status
Simulation time 4394264760 ps
CPU time 20.43 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:53:03 PM PDT 24
Peak memory 236020 kb
Host smart-7cd490f6-e9f3-4eb6-bdeb-01e5499cc4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000907585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3000907585
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.760619171
Short name T935
Test name
Test status
Simulation time 270131262 ps
CPU time 2.27 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 215880 kb
Host smart-6aeddcf3-5ada-4f2d-9b69-19a586daa8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760619171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.760619171
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3669116235
Short name T461
Test name
Test status
Simulation time 26508430314 ps
CPU time 108.87 seconds
Started May 26 12:52:43 PM PDT 24
Finished May 26 12:54:33 PM PDT 24
Peak memory 233508 kb
Host smart-549d6501-e1ac-47a2-aea7-b41c79f842ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669116235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3669116235
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1638788430
Short name T734
Test name
Test status
Simulation time 393153478 ps
CPU time 6.96 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:50 PM PDT 24
Peak memory 236540 kb
Host smart-cabb9864-666b-4830-8c5c-35f928c65f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638788430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1638788430
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.603202827
Short name T49
Test name
Test status
Simulation time 1891202021 ps
CPU time 9.29 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:52:51 PM PDT 24
Peak memory 237972 kb
Host smart-27546bf2-53d4-41e1-a407-232eddfe1e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603202827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.603202827
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1120933656
Short name T646
Test name
Test status
Simulation time 1064600971 ps
CPU time 9.84 seconds
Started May 26 12:52:43 PM PDT 24
Finished May 26 12:52:54 PM PDT 24
Peak memory 222764 kb
Host smart-b56f5fd2-292b-472a-8a3f-8a0cae1ff390
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1120933656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1120933656
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2587180752
Short name T48
Test name
Test status
Simulation time 2606624922 ps
CPU time 25.5 seconds
Started May 26 12:52:56 PM PDT 24
Finished May 26 12:53:23 PM PDT 24
Peak memory 240764 kb
Host smart-30c2c00f-1998-481b-ac91-7f597bba2ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587180752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2587180752
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1503449701
Short name T617
Test name
Test status
Simulation time 1590368009 ps
CPU time 11.72 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:52:54 PM PDT 24
Peak memory 216164 kb
Host smart-24779726-6a29-4d58-a0c6-16ba3a4b7352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503449701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1503449701
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3051826409
Short name T378
Test name
Test status
Simulation time 12627193515 ps
CPU time 9.62 seconds
Started May 26 12:52:41 PM PDT 24
Finished May 26 12:52:52 PM PDT 24
Peak memory 216104 kb
Host smart-6cc76e4c-93f3-4278-842a-bf9d8825bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051826409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3051826409
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.461109154
Short name T529
Test name
Test status
Simulation time 73781035 ps
CPU time 0.79 seconds
Started May 26 12:52:43 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 205576 kb
Host smart-8f3953e2-0d52-4de6-82de-41ae9e13b4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461109154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.461109154
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3841285359
Short name T359
Test name
Test status
Simulation time 144238393 ps
CPU time 0.89 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:44 PM PDT 24
Peak memory 205548 kb
Host smart-e8abd086-7757-44cd-a627-fd0d46073a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841285359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3841285359
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.633606293
Short name T316
Test name
Test status
Simulation time 981889043 ps
CPU time 2.85 seconds
Started May 26 12:52:42 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 224196 kb
Host smart-f4f5ba93-0fe1-4d06-ba7d-33fe4c559832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633606293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.633606293
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.574082974
Short name T947
Test name
Test status
Simulation time 58237213 ps
CPU time 0.69 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:52:57 PM PDT 24
Peak memory 205268 kb
Host smart-4bc9c653-ae5d-4898-a60d-ba1f03b03095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574082974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.574082974
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2285398729
Short name T434
Test name
Test status
Simulation time 53444952 ps
CPU time 2.07 seconds
Started May 26 12:52:56 PM PDT 24
Finished May 26 12:52:59 PM PDT 24
Peak memory 216012 kb
Host smart-e94f9997-6f5a-430f-812e-8aacf53c4687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285398729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2285398729
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4131171208
Short name T485
Test name
Test status
Simulation time 64850893 ps
CPU time 0.79 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:52:57 PM PDT 24
Peak memory 206324 kb
Host smart-3443fdf7-19ad-4c84-a196-01888d5a4e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131171208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4131171208
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2069999841
Short name T307
Test name
Test status
Simulation time 4676025528 ps
CPU time 75.1 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:54:11 PM PDT 24
Peak memory 248976 kb
Host smart-534350d9-4006-4362-9b77-98535855ed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069999841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2069999841
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1576951370
Short name T327
Test name
Test status
Simulation time 495404744 ps
CPU time 7.56 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:53:03 PM PDT 24
Peak memory 232440 kb
Host smart-ad8c480a-92f9-4e54-9d26-a8f19c382818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576951370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1576951370
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.19443938
Short name T944
Test name
Test status
Simulation time 952591216 ps
CPU time 7.79 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:53:04 PM PDT 24
Peak memory 233716 kb
Host smart-e4509353-1f57-468d-8b66-dad73cd71b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19443938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.19443938
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.792748842
Short name T318
Test name
Test status
Simulation time 612898768 ps
CPU time 7.33 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:53:03 PM PDT 24
Peak memory 217648 kb
Host smart-90faba6d-1cb7-4473-bc63-9db93a10e24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792748842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.792748842
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2486485478
Short name T33
Test name
Test status
Simulation time 3073357796 ps
CPU time 3.82 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:52:59 PM PDT 24
Peak memory 218488 kb
Host smart-e45dcb0d-76bc-4a2c-9fa3-b29a2f173f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486485478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2486485478
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1121669329
Short name T836
Test name
Test status
Simulation time 7453325606 ps
CPU time 7.4 seconds
Started May 26 12:53:00 PM PDT 24
Finished May 26 12:53:09 PM PDT 24
Peak memory 233484 kb
Host smart-14db8853-fafa-43ed-801b-2ab515d8a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121669329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1121669329
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1004934985
Short name T584
Test name
Test status
Simulation time 213011877 ps
CPU time 4.99 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:53:01 PM PDT 24
Peak memory 222984 kb
Host smart-88d37233-58fb-41f2-80bc-fd2856be6844
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1004934985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1004934985
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.818357832
Short name T77
Test name
Test status
Simulation time 8854470556 ps
CPU time 92.47 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:54:28 PM PDT 24
Peak memory 251508 kb
Host smart-ba01af0b-27b9-4ef8-9b53-a574f7546f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818357832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.818357832
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.32314549
Short name T721
Test name
Test status
Simulation time 15542829 ps
CPU time 0.71 seconds
Started May 26 12:52:56 PM PDT 24
Finished May 26 12:52:58 PM PDT 24
Peak memory 205440 kb
Host smart-a61b6df2-f184-4afb-8353-4d4fc69242e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32314549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.32314549
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.318107485
Short name T920
Test name
Test status
Simulation time 5983574738 ps
CPU time 13.04 seconds
Started May 26 12:52:53 PM PDT 24
Finished May 26 12:53:06 PM PDT 24
Peak memory 216180 kb
Host smart-f9a39aa1-8da7-41f6-a116-462dbdfe5670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318107485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.318107485
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4155365395
Short name T929
Test name
Test status
Simulation time 394324639 ps
CPU time 1.56 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:52:57 PM PDT 24
Peak memory 216156 kb
Host smart-55352d5a-3087-4749-b54e-edbba5301391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155365395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4155365395
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.521829280
Short name T85
Test name
Test status
Simulation time 62922082 ps
CPU time 0.85 seconds
Started May 26 12:52:55 PM PDT 24
Finished May 26 12:52:57 PM PDT 24
Peak memory 205464 kb
Host smart-8191567c-56c3-4a9c-8c0c-80718f1eda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521829280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.521829280
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3652523945
Short name T311
Test name
Test status
Simulation time 813970156 ps
CPU time 5.83 seconds
Started May 26 12:52:54 PM PDT 24
Finished May 26 12:53:01 PM PDT 24
Peak memory 218776 kb
Host smart-ec9fb75c-ec53-46e4-b44c-a7d120055c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652523945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3652523945
Directory /workspace/9.spi_device_upload/latest
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