Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	99.31	100.00	100.00			97.22	100.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	97.83			98.63	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sck2csb_status	100.00	100.00				100.00
u_stage_to_commit	100.00	100.00				100.00
u_sw_status_update_sync	99.00	100.00	96.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	162	6	6	100.00
ALWAYS	173	8	8	100.00
ALWAYS	186	4	4	100.00
ALWAYS	198	7	7	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
ALWAYS	260	3	3	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	297	4	4	100.00
ALWAYS	310	5	5	100.00
ALWAYS	324	3	3	100.00
ALWAYS	332	6	6	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	353	3	3	100.00
ALWAYS	358	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
91	1	1
94	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
			MISSING_ELSE
186	1	1
187	1	1
188	1	1
189	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
			MISSING_ELSE
204	1	1
205	1	1
			MISSING_ELSE
220	1	1
221	1	1
222	1	1
237	1	1
260	1	1
261	1	1
263	1	1
266	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			MISSING_ELSE
310	1	1
311	1	1
312	1	1
314	1	1
315	1	1
324	1	1
325	1	1
327	1	1
332	1	1
334	1	1
336	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
			MISSING_ELSE
346	1	1
353	2	2
354	1	1
358	1	1
360	1	1
362	1	1
364	1	1
366	1	1
367	1	1
369	1	1
370	1	1
			MISSING_ELSE
375	1	1

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       166
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T14
1	1	Covered	T8,T14,T15

 LINE       166
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T7,T8,T14
1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
             ----1----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T15
1	1	Covered	T7,T8,T14

 LINE       179
 SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T7,T8,T15
1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (sys_rst_ni & status_fifo_clr_n)
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       339
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T5,T8,T15
1	Covered	T5,T8,T15

 LINE       346
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Covered	T5,T8,T15
1	Covered	T1,T2,T3

 LINE       346
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       366
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T15

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		36	35	97.22
TERNARY	346	2	2	100.00
IF	162	4	4	100.00
IF	173	5	5	100.00
IF	186	3	3	100.00
IF	199	3	3	100.00
IF	204	2	2	100.00
IF	260	2	2	100.00
IF	297	3	3	100.00
IF	310	2	2	100.00
IF	324	2	2	100.00
IF	334	2	2	100.00
IF	353	2	2	100.00
CASE	364	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	346	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T15

	LineNo.	Expression
-1-:	162	if ((!sys_rst_ni))
-2-:	164	if (inclk_busy_set_i)
-3-:	166	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T15,T17
0	0	1	Covered	T8,T14,T15
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	173	if ((!sys_rst_ni))
-2-:	175	if (inclk_we_set_i)
-3-:	177	if (inclk_we_clr_i)
-4-:	179	if ((sck_sw_we && (sck_sw_status[BitWe] == 1'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T8,T15,T17
0	0	1	-	Covered	T8,T15,T17
0	0	0	1	Covered	T7,T8,T14
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	if ((!sys_rst_ni))
-2-:	188	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	if (inclk_we_set_i)
-2-:	201	if (inclk_we_clr_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T15,T17
0	1	Covered	T8,T15,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if (inclk_busy_set_i)

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	if ((!sys_rst_ni))
-2-:	299	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	310	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	324	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	334	if (byte_sel_update)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	364	case (st_q)
-2-:	366	if ((sel_dp_i == DpReadStatus))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Covered	T5,T8,T15
StIdle	0	Covered	T1,T2,T3
StActive	-	Covered	T5,T8,T15
default	-	Not Covered

---

Assert Coverage for Module : spid_status

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusyBitZero_A	906	906	0	0

BusyBitZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0