Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.62	93.89	84.31	96.94		87.50	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.62	93.89	84.31	96.94		87.50	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.62	93.89	84.31	96.94		87.50	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.56	98.30	94.10	98.61	89.36	97.14	95.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.71	100.00	87.64		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	85.98	100.00	71.43			72.50	100.00
u_passthrough	89.62	92.20	89.22		75.00	91.67	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_intercept_pipe_stg1	100.00	100.00				100.00
u_read_intercept_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.30	93.62	90.32		87.50	84.15	90.91
u_reg	99.64	99.53	99.33	100.00		99.35	100.00
u_rst_spi_out_sync	100.00	100.00				100.00
u_s2p	89.38	100.00	78.57			78.95	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.81	99.28	85.25		91.67	95.68	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	93.75	100.00	75.00			100.00	100.00
u_spid_status	99.11	100.00	97.83			98.63	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	89.65	100.00	76.47			96.43	85.71
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.45	82.04	59.19			63.33	81.25
u_tlul2sram_ingress	83.98	85.71	71.32			78.89	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tpm_rst_out_sync	100.00	100.00				100.00
u_upload	90.79	98.60	71.95		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		229	215	93.89
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	539	4	4	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
ALWAYS	569	0	0
ALWAYS	569	2	2	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	583	0	0
ALWAYS	583	12	12	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	810	3	3	100.00
ALWAYS	816	8	8	100.00
ALWAYS	854	9	9	100.00
ALWAYS	878	24	24	100.00
CONT_ASSIGN	946	1	1	100.00
CONT_ASSIGN	947	1	1	100.00
ALWAYS	1010	7	4	57.14
ALWAYS	1023	13	13	100.00
ALWAYS	1060	3	3	100.00
CONT_ASSIGN	1199	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1262	1	0	0.00
CONT_ASSIGN	1293	1	0	0.00
CONT_ASSIGN	1376	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
CONT_ASSIGN	1378	1	1	100.00
CONT_ASSIGN	1379	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1382	1	1	100.00
CONT_ASSIGN	1386	1	1	100.00
CONT_ASSIGN	1393	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1400	1	1	100.00
CONT_ASSIGN	1403	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1409	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1415	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1462	1	1	100.00
CONT_ASSIGN	1565	1	0	0.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1580	1	1	100.00
CONT_ASSIGN	1587	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1598	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1602	1	1	100.00
CONT_ASSIGN	1604	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1610	1	1	100.00
CONT_ASSIGN	1611	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
CONT_ASSIGN	1632	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1696	1	1	100.00
CONT_ASSIGN	1698	1	1	100.00
ALWAYS	1703	4	4	100.00
ALWAYS	1712	0	0
ALWAYS	1712	9	9	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	1	100.00
CONT_ASSIGN	1730	1	0	0.00
CONT_ASSIGN	1730	1	0	0.00
CONT_ASSIGN	1730	1	0	0.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1731	1	0	0.00
CONT_ASSIGN	1731	1	0	0.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1732	1	0	0.00
CONT_ASSIGN	1732	1	0	0.00
CONT_ASSIGN	1732	1	0	0.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1735	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1781	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1783	1	1	100.00
CONT_ASSIGN	1785	1	1	100.00
CONT_ASSIGN	1786	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
309	1	1
372	1	1
373	1	1
376	1	1
377	1	1
379	1	1
394	1	1
527	1	1
534	1	1
536	1	1
539	1	1
540	1	1
541	1	1
542	1	1
			MISSING_ELSE
547	1	1
553	1	1
554	1	1
559	1	1
560	1	1
564	1	1
569	1	1
570	1	1
574	1	1
575	1	1
583	1	1
584	1	1
603	1	1
604	1	1
608	1	1
609	1	1
611	1	1
612	1	1
614	1	1
615	1	1
617	1	1
618	1	1
647	1	1
648	1	1
649	1	1
710	1	1
810	2	2
811	1	1
816	1	1
818	1	1
819	1	1
826	1	1
830	1	1
831	1	1
835	1	1
836	1	1
854	1	1
856	1	1
861	1	1
867	1	1
868	1	1
869	1	1
870	1	1
871	1	1
872	1	1
			MISSING_ELSE
878	1	1
879	1	1
880	1	1
881	1	1
883	1	1
885	1	1
887	1	1
889	1	1
893	1	1
895	1	1
896	1	1
897	1	1
900	1	1
902	1	1
903	1	1
904	1	1
909	1	1
911	1	1
912	1	1
913	1	1
917	1	1
919	1	1
920	1	1
921	1	1
946	1	1
947	1	1
1010	1	1
1011	0	1
1012	0	1
1013	0	1
1015	1	1
1016	1	1
1017	1	1
1023	1	1
1024	1	1
1026	1	1
1028	1	1
1029	1	1
1033	1	1
1035	1	1
1036	1	1
1040	1	1
1041	1	1
1042	1	1
1044	1	1
1045	1	1
1060	2	2
1061	1	1
1199	1	1
1202	1	1
1206	1	1
1207	1	1
1208	1	1
1210	1	1
1211	1	1
1214	1	1
1262	0	1
1293	0	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1382	1	1
1386	1	1
1393	1	1
1394	1	1
1396	1	1
1400	1	1
1403	1	1
1406	1	1
1409	1	1
1412	1	1
1415	1	1
1422	1	1
1423	1	1
1462	1	1
1565	0	1
1573	1	1
1574	1	1
1575	1	1
1576	1	1
1577	1	1
1580	1	1
1587	1	1
1594	5	5
1597	1	1
1598	1	1
1599	1	1
1600	1	1
1601	1	1
1602	1	1
1604	1	1
1608	1	1
1610	1	1
1611	1	1
1618	1	1
1620	1	1
1621	1	1
1630	1	1
1631	1	1
1632	1	1
1633	1	1
1696	1	1
1698	1	1
1703	1	1
1704	1	1
1705	1	1
1706	1	1
			MISSING_ELSE
1712	1	1
1713	1	1
1715	1	1
1718	1	1
1719	1	1
1720	1	1
1721	1	1
1723	1	1
1724	1	1
1729	5	5
1730	2	5
1731	3	5
1732	2	5
1734	5	5
1735	5	5
1736	5	5
1777	1	1
1779	1	1
1780	1	1
1781	1	1
1782	1	1
1783	1	1
1785	1	1
1786	1	1
1787	1	1
1843	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T18

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       727
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       840
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       867
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       867
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       867
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       867
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       1026
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1199
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T14

 LINE       1210
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       1211
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       1422
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T27

 LINE       1423
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       1587
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T15

 LINE       1705
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1705
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1705
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1777
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       1843
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T9,T55,T56
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T55,T56

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T57	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T14	Yes	T10,T11,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T58,T59,T60	Yes	T58,T59,T60	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T55,T56	Yes	T9,T55,T56	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T55,T56	Yes	T9,T55,T56	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cio_sd_o[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T5,*T6,*T8	Yes	T5,T6,T8	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T8,T18,T19	Yes	T5,T6,T8	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T18,T31,T61	Yes	T18,T31,T61	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T18,T31,T23	Yes	T18,T31,T23	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T62	Yes	T62	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T62	Yes	T62	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	28	87.50
IF	539	3	3	100.00
IF	810	2	2	100.00
CASE	826	4	4	100.00
IF	867	3	3	100.00
CASE	883	7	5	71.43
IF	1010	2	1	50.00
IF	1026	5	4	80.00
IF	1060	2	2	100.00
IF	1705	2	2	100.00
IF	1715	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	539	if ((!rst_ni))
-2-:	541	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	810	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	826	case (cmd_dp_sel)
-2-:	840	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T6,T7,T8
DpUpload	-	Covered	T8,T15,T17
default	1	Covered	T8,T15,T17
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	867	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	870	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	883	case (spi_mode)
-2-:	885	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T6,T7,T8
FlashMode PassThrough	DpReadStatus	Covered	T5,T8,T15
FlashMode PassThrough	DpReadJEDEC	Covered	T15,T18,T19
FlashMode PassThrough	DpUpload	Covered	T8,T15,T17
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1010	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1026	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1033	case (spi_mode)
-3-:	1040	if (intercept_en_out)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T5,T8,T18
0	PassThrough	0	Covered	T5,T6,T8
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1060	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	1705	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1715	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	341249657	341165273	0	0
CioSdoEnOKnown	341249657	341165273	0	0
CioSdoEnOffWhenInactive	341249657	341165273	0	0
FpvSecCmRegWeOnehotCheck_A	341249657	130	0	0
InterceptLevel_M	120387164	0	0	0
IntrReadbufFlipOKnown	341249657	341165273	0	0
IntrReadbufWatermarkOKnown	341249657	341165273	0	0
IntrTpmHeaderNotEmptyOKnown	341249657	341165273	0	0
IntrTpmRdfifoCmdEndOKnown	341249657	341165273	0	0
IntrTpmRdfifoDropOKnown	341249657	341165273	0	0
IntrUploadCmdfifoNotEmptyOKnown	341249657	341165273	0	0
IntrUploadPayloadNotEmptyOKnown	341249657	341165273	0	0
IntrUploadPayloadOverflowOKnown	341249657	341165273	0	0
PayloadStartIdxWidthMatch_A	906	906	0	0
SpiModeKnown_A	341249657	341165273	0	0
TpmEnableWhenTpmCsbIdle_M	341249657	332	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	341249657	1518528	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	341249657	136743	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	341249657	1539	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	341249657	1150	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	341249657	177561	0	0
scanmodeKnown	341249657	341249657	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	130	0	0
T22	445626	0	0	0
T57	5584	20	0	0
T63	0	30	0	0
T64	0	30	0	0
T65	0	20	0	0
T66	0	30	0	0
T67	78392	0	0	0
T68	33735	0	0	0
T69	18661	0	0	0
T70	15020	0	0	0
T71	193632	0	0	0
T72	40760	0	0	0
T73	1608	0	0	0
T74	764	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	120387164	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	332	0	0
T1	996	1	0	0
T2	2412	1	0	0
T3	234058	1	0	0
T4	2180	0	0	0
T5	36423	0	0	0
T6	232158	0	0	0
T7	153080	0	0	0
T8	183747	0	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T36	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1518528	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	81849	832	0	0
T13	322473	832	0	0
T14	10672	832	0	0
T15	0	9984	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	136743	0	0
T2	2412	2	0	0
T3	234058	185	0	0
T4	2180	0	0	0
T5	36423	0	0	0
T6	232158	0	0	0
T7	153080	0	0	0
T8	183747	128	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T15	0	471	0	0
T16	0	2	0	0
T17	0	296	0	0
T18	0	1521	0	0
T19	0	500	0	0
T25	0	603	0	0
T26	0	64	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1539	0	0
T8	183747	3	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T12	81849	0	0	0
T13	322473	0	0	0
T14	10672	0	0	0
T15	371367	7	0	0
T16	3900	0	0	0
T17	0	1	0	0
T18	0	27	0	0
T19	0	5	0	0
T25	0	10	0	0
T26	0	4	0	0
T27	2879	0	0	0
T28	0	10	0	0
T29	0	7	0	0
T44	0	4	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1150	0	0
T8	183747	2	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T12	81849	0	0	0
T13	322473	0	0	0
T14	10672	0	0	0
T15	371367	5	0	0
T16	3900	0	0	0
T17	0	1	0	0
T18	0	24	0	0
T19	0	1	0	0
T25	0	5	0	0
T26	0	3	0	0
T27	2879	0	0	0
T28	0	6	0	0
T29	0	3	0	0
T44	0	4	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	177561	0	0
T2	2412	27	0	0
T3	234058	454	0	0
T4	2180	0	0	0
T5	36423	0	0	0
T6	232158	0	0	0
T7	153080	0	0	0
T8	183747	0	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T15	0	504	0	0
T16	0	10	0	0
T17	0	358	0	0
T18	0	1289	0	0
T19	0	745	0	0
T25	0	923	0	0
T38	0	1545	0	0
T43	0	1879	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341249657	0	0
T1	996	996	0	0
T2	2412	2412	0	0
T3	234058	234058	0	0
T4	2180	2180	0	0
T5	36423	36423	0	0
T6	232158	232158	0	0
T7	153080	153080	0	0
T8	183747	183747	0	0
T9	1064	1064	0	0
T10	930418	930418	0	0