Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3461 |
0 |
0 |
T58 |
3602 |
8 |
0 |
0 |
T59 |
2315 |
95 |
0 |
0 |
T60 |
12028 |
3 |
0 |
0 |
T91 |
8482 |
135 |
0 |
0 |
T92 |
82623 |
1 |
0 |
0 |
T103 |
16413 |
7 |
0 |
0 |
T104 |
4568 |
5 |
0 |
0 |
T109 |
4453 |
2 |
0 |
0 |
T110 |
13191 |
5 |
0 |
0 |
T111 |
9074 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2953 |
0 |
0 |
T80 |
4814 |
9 |
0 |
0 |
T81 |
4982 |
12 |
0 |
0 |
T103 |
16413 |
18 |
0 |
0 |
T112 |
10109 |
10 |
0 |
0 |
T113 |
90362 |
198 |
0 |
0 |
T120 |
181112 |
464 |
0 |
0 |
T142 |
18572 |
6 |
0 |
0 |
T143 |
6011 |
5 |
0 |
0 |
T144 |
33683 |
37 |
0 |
0 |
T145 |
70075 |
63 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2866 |
0 |
0 |
T80 |
4814 |
19 |
0 |
0 |
T81 |
4982 |
15 |
0 |
0 |
T103 |
16413 |
33 |
0 |
0 |
T112 |
10109 |
16 |
0 |
0 |
T113 |
90362 |
206 |
0 |
0 |
T120 |
181112 |
432 |
0 |
0 |
T142 |
18572 |
43 |
0 |
0 |
T143 |
6011 |
1 |
0 |
0 |
T144 |
33683 |
35 |
0 |
0 |
T145 |
70075 |
79 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3192 |
0 |
0 |
T80 |
4814 |
9 |
0 |
0 |
T81 |
4982 |
18 |
0 |
0 |
T103 |
16413 |
38 |
0 |
0 |
T112 |
10109 |
11 |
0 |
0 |
T113 |
90362 |
253 |
0 |
0 |
T120 |
181112 |
407 |
0 |
0 |
T142 |
18572 |
11 |
0 |
0 |
T143 |
6011 |
15 |
0 |
0 |
T144 |
33683 |
87 |
0 |
0 |
T145 |
70075 |
177 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9905 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
16 |
0 |
0 |
T103 |
16413 |
258 |
0 |
0 |
T112 |
10109 |
7 |
0 |
0 |
T113 |
90362 |
223 |
0 |
0 |
T120 |
181112 |
444 |
0 |
0 |
T142 |
18572 |
27 |
0 |
0 |
T143 |
6011 |
123 |
0 |
0 |
T144 |
33683 |
703 |
0 |
0 |
T145 |
70075 |
1648 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9553 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
253 |
0 |
0 |
T112 |
10109 |
142 |
0 |
0 |
T113 |
90362 |
227 |
0 |
0 |
T120 |
181112 |
388 |
0 |
0 |
T142 |
18572 |
51 |
0 |
0 |
T143 |
6011 |
140 |
0 |
0 |
T144 |
33683 |
1016 |
0 |
0 |
T145 |
70075 |
1354 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
10286 |
0 |
0 |
T80 |
4814 |
16 |
0 |
0 |
T81 |
4982 |
14 |
0 |
0 |
T103 |
16413 |
122 |
0 |
0 |
T112 |
10109 |
113 |
0 |
0 |
T113 |
90362 |
193 |
0 |
0 |
T120 |
181112 |
435 |
0 |
0 |
T142 |
18572 |
46 |
0 |
0 |
T143 |
6011 |
11 |
0 |
0 |
T144 |
33683 |
401 |
0 |
0 |
T145 |
70075 |
1610 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
10538 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
5 |
0 |
0 |
T103 |
16413 |
129 |
0 |
0 |
T112 |
10109 |
166 |
0 |
0 |
T113 |
90362 |
232 |
0 |
0 |
T120 |
181112 |
489 |
0 |
0 |
T142 |
18572 |
19 |
0 |
0 |
T143 |
6011 |
113 |
0 |
0 |
T144 |
33683 |
761 |
0 |
0 |
T145 |
70075 |
1956 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9588 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
16 |
0 |
0 |
T103 |
16413 |
385 |
0 |
0 |
T112 |
10109 |
112 |
0 |
0 |
T113 |
90362 |
226 |
0 |
0 |
T120 |
181112 |
442 |
0 |
0 |
T142 |
18572 |
29 |
0 |
0 |
T143 |
6011 |
103 |
0 |
0 |
T144 |
33683 |
509 |
0 |
0 |
T145 |
70075 |
1315 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9423 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
6 |
0 |
0 |
T103 |
16413 |
120 |
0 |
0 |
T112 |
10109 |
247 |
0 |
0 |
T113 |
90362 |
266 |
0 |
0 |
T120 |
181112 |
445 |
0 |
0 |
T142 |
18572 |
49 |
0 |
0 |
T143 |
6011 |
8 |
0 |
0 |
T144 |
33683 |
398 |
0 |
0 |
T145 |
70075 |
1191 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9116 |
0 |
0 |
T80 |
4814 |
17 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T103 |
16413 |
22 |
0 |
0 |
T112 |
10109 |
230 |
0 |
0 |
T113 |
90362 |
227 |
0 |
0 |
T120 |
181112 |
488 |
0 |
0 |
T142 |
18572 |
26 |
0 |
0 |
T143 |
6011 |
130 |
0 |
0 |
T144 |
33683 |
718 |
0 |
0 |
T145 |
70075 |
1267 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
9454 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
20 |
0 |
0 |
T103 |
16413 |
370 |
0 |
0 |
T112 |
10109 |
263 |
0 |
0 |
T113 |
90362 |
199 |
0 |
0 |
T120 |
181112 |
461 |
0 |
0 |
T142 |
18572 |
41 |
0 |
0 |
T143 |
6011 |
131 |
0 |
0 |
T144 |
33683 |
428 |
0 |
0 |
T145 |
70075 |
1246 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5450 |
0 |
0 |
T80 |
4814 |
8 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T103 |
16413 |
67 |
0 |
0 |
T112 |
10109 |
11 |
0 |
0 |
T113 |
90362 |
218 |
0 |
0 |
T120 |
181112 |
441 |
0 |
0 |
T142 |
18572 |
37 |
0 |
0 |
T143 |
6011 |
36 |
0 |
0 |
T144 |
33683 |
224 |
0 |
0 |
T145 |
70075 |
351 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5983 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
16 |
0 |
0 |
T103 |
16413 |
195 |
0 |
0 |
T112 |
10109 |
61 |
0 |
0 |
T113 |
90362 |
222 |
0 |
0 |
T120 |
181112 |
431 |
0 |
0 |
T142 |
18572 |
27 |
0 |
0 |
T143 |
6011 |
50 |
0 |
0 |
T144 |
33683 |
441 |
0 |
0 |
T145 |
70075 |
534 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5645 |
0 |
0 |
T80 |
4814 |
3 |
0 |
0 |
T81 |
4982 |
10 |
0 |
0 |
T103 |
16413 |
72 |
0 |
0 |
T112 |
10109 |
94 |
0 |
0 |
T113 |
90362 |
223 |
0 |
0 |
T120 |
181112 |
446 |
0 |
0 |
T142 |
18572 |
67 |
0 |
0 |
T143 |
6011 |
8 |
0 |
0 |
T144 |
33683 |
40 |
0 |
0 |
T145 |
70075 |
392 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5414 |
0 |
0 |
T80 |
4814 |
17 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
149 |
0 |
0 |
T112 |
10109 |
58 |
0 |
0 |
T113 |
90362 |
221 |
0 |
0 |
T120 |
181112 |
414 |
0 |
0 |
T142 |
18572 |
49 |
0 |
0 |
T143 |
6011 |
47 |
0 |
0 |
T144 |
33683 |
272 |
0 |
0 |
T145 |
70075 |
457 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5624 |
0 |
0 |
T80 |
4814 |
16 |
0 |
0 |
T81 |
4982 |
10 |
0 |
0 |
T103 |
16413 |
164 |
0 |
0 |
T112 |
10109 |
114 |
0 |
0 |
T113 |
90362 |
238 |
0 |
0 |
T120 |
181112 |
433 |
0 |
0 |
T142 |
18572 |
21 |
0 |
0 |
T143 |
6011 |
15 |
0 |
0 |
T144 |
33683 |
297 |
0 |
0 |
T145 |
70075 |
589 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5012 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
5 |
0 |
0 |
T103 |
16413 |
114 |
0 |
0 |
T112 |
10109 |
86 |
0 |
0 |
T113 |
90362 |
242 |
0 |
0 |
T120 |
181112 |
438 |
0 |
0 |
T142 |
18572 |
43 |
0 |
0 |
T143 |
6011 |
3 |
0 |
0 |
T144 |
33683 |
286 |
0 |
0 |
T145 |
70075 |
500 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5525 |
0 |
0 |
T80 |
4814 |
6 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
124 |
0 |
0 |
T112 |
10109 |
61 |
0 |
0 |
T113 |
90362 |
203 |
0 |
0 |
T120 |
181112 |
444 |
0 |
0 |
T142 |
18572 |
41 |
0 |
0 |
T143 |
6011 |
33 |
0 |
0 |
T144 |
33683 |
297 |
0 |
0 |
T145 |
70075 |
601 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5761 |
0 |
0 |
T80 |
4814 |
9 |
0 |
0 |
T81 |
4982 |
18 |
0 |
0 |
T103 |
16413 |
76 |
0 |
0 |
T112 |
10109 |
45 |
0 |
0 |
T113 |
90362 |
264 |
0 |
0 |
T120 |
181112 |
405 |
0 |
0 |
T142 |
18572 |
66 |
0 |
0 |
T143 |
6011 |
9 |
0 |
0 |
T144 |
33683 |
331 |
0 |
0 |
T145 |
70075 |
479 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5981 |
0 |
0 |
T80 |
4814 |
6 |
0 |
0 |
T81 |
4982 |
8 |
0 |
0 |
T103 |
16413 |
52 |
0 |
0 |
T112 |
10109 |
89 |
0 |
0 |
T113 |
90362 |
246 |
0 |
0 |
T120 |
181112 |
433 |
0 |
0 |
T142 |
18572 |
54 |
0 |
0 |
T143 |
6011 |
56 |
0 |
0 |
T144 |
33683 |
300 |
0 |
0 |
T145 |
70075 |
958 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5654 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
68 |
0 |
0 |
T112 |
10109 |
68 |
0 |
0 |
T113 |
90362 |
209 |
0 |
0 |
T120 |
181112 |
458 |
0 |
0 |
T142 |
18572 |
48 |
0 |
0 |
T143 |
6011 |
12 |
0 |
0 |
T144 |
33683 |
37 |
0 |
0 |
T145 |
70075 |
686 |
0 |
0 |
T146 |
8038 |
20 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5425 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
10 |
0 |
0 |
T103 |
16413 |
100 |
0 |
0 |
T112 |
10109 |
60 |
0 |
0 |
T113 |
90362 |
234 |
0 |
0 |
T120 |
181112 |
474 |
0 |
0 |
T142 |
18572 |
16 |
0 |
0 |
T143 |
6011 |
5 |
0 |
0 |
T144 |
33683 |
174 |
0 |
0 |
T145 |
70075 |
631 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5491 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T103 |
16413 |
52 |
0 |
0 |
T112 |
10109 |
57 |
0 |
0 |
T113 |
90362 |
180 |
0 |
0 |
T120 |
181112 |
412 |
0 |
0 |
T142 |
18572 |
33 |
0 |
0 |
T143 |
6011 |
49 |
0 |
0 |
T144 |
33683 |
328 |
0 |
0 |
T145 |
70075 |
610 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5260 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
4 |
0 |
0 |
T98 |
21320 |
8 |
0 |
0 |
T103 |
16413 |
157 |
0 |
0 |
T112 |
10109 |
104 |
0 |
0 |
T113 |
90362 |
256 |
0 |
0 |
T120 |
181112 |
430 |
0 |
0 |
T142 |
18572 |
26 |
0 |
0 |
T143 |
6011 |
67 |
0 |
0 |
T144 |
33683 |
153 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5935 |
0 |
0 |
T80 |
4814 |
9 |
0 |
0 |
T81 |
4982 |
15 |
0 |
0 |
T103 |
16413 |
114 |
0 |
0 |
T112 |
10109 |
71 |
0 |
0 |
T113 |
90362 |
210 |
0 |
0 |
T120 |
181112 |
504 |
0 |
0 |
T142 |
18572 |
40 |
0 |
0 |
T143 |
6011 |
55 |
0 |
0 |
T144 |
33683 |
335 |
0 |
0 |
T145 |
70075 |
739 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5429 |
0 |
0 |
T80 |
4814 |
4 |
0 |
0 |
T81 |
4982 |
10 |
0 |
0 |
T103 |
16413 |
16 |
0 |
0 |
T112 |
10109 |
107 |
0 |
0 |
T113 |
90362 |
241 |
0 |
0 |
T120 |
181112 |
487 |
0 |
0 |
T142 |
18572 |
32 |
0 |
0 |
T143 |
6011 |
3 |
0 |
0 |
T144 |
33683 |
215 |
0 |
0 |
T145 |
70075 |
608 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5681 |
0 |
0 |
T80 |
4814 |
4 |
0 |
0 |
T81 |
4982 |
15 |
0 |
0 |
T103 |
16413 |
63 |
0 |
0 |
T112 |
10109 |
107 |
0 |
0 |
T113 |
90362 |
188 |
0 |
0 |
T120 |
181112 |
458 |
0 |
0 |
T142 |
18572 |
33 |
0 |
0 |
T143 |
6011 |
30 |
0 |
0 |
T144 |
33683 |
90 |
0 |
0 |
T145 |
70075 |
752 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5641 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
8 |
0 |
0 |
T103 |
16413 |
56 |
0 |
0 |
T112 |
10109 |
94 |
0 |
0 |
T113 |
90362 |
222 |
0 |
0 |
T120 |
181112 |
456 |
0 |
0 |
T142 |
18572 |
36 |
0 |
0 |
T143 |
6011 |
49 |
0 |
0 |
T144 |
33683 |
351 |
0 |
0 |
T145 |
70075 |
609 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5356 |
0 |
0 |
T80 |
4814 |
19 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T103 |
16413 |
82 |
0 |
0 |
T112 |
10109 |
79 |
0 |
0 |
T113 |
90362 |
177 |
0 |
0 |
T120 |
181112 |
468 |
0 |
0 |
T142 |
18572 |
15 |
0 |
0 |
T143 |
6011 |
48 |
0 |
0 |
T144 |
33683 |
177 |
0 |
0 |
T145 |
70075 |
502 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5669 |
0 |
0 |
T80 |
4814 |
15 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
122 |
0 |
0 |
T112 |
10109 |
6 |
0 |
0 |
T113 |
90362 |
242 |
0 |
0 |
T120 |
181112 |
457 |
0 |
0 |
T142 |
18572 |
49 |
0 |
0 |
T143 |
6011 |
54 |
0 |
0 |
T144 |
33683 |
338 |
0 |
0 |
T145 |
70075 |
777 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5275 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
15 |
0 |
0 |
T103 |
16413 |
156 |
0 |
0 |
T112 |
10109 |
6 |
0 |
0 |
T113 |
90362 |
245 |
0 |
0 |
T120 |
181112 |
471 |
0 |
0 |
T142 |
18572 |
18 |
0 |
0 |
T143 |
6011 |
11 |
0 |
0 |
T144 |
33683 |
382 |
0 |
0 |
T145 |
70075 |
369 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5163 |
0 |
0 |
T80 |
4814 |
15 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
33 |
0 |
0 |
T112 |
10109 |
173 |
0 |
0 |
T113 |
90362 |
237 |
0 |
0 |
T120 |
181112 |
463 |
0 |
0 |
T142 |
18572 |
28 |
0 |
0 |
T143 |
6011 |
51 |
0 |
0 |
T144 |
33683 |
283 |
0 |
0 |
T145 |
70075 |
391 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5772 |
0 |
0 |
T80 |
4814 |
18 |
0 |
0 |
T81 |
4982 |
4 |
0 |
0 |
T103 |
16413 |
178 |
0 |
0 |
T112 |
10109 |
113 |
0 |
0 |
T113 |
90362 |
168 |
0 |
0 |
T120 |
181112 |
496 |
0 |
0 |
T142 |
18572 |
21 |
0 |
0 |
T143 |
6011 |
60 |
0 |
0 |
T144 |
33683 |
336 |
0 |
0 |
T145 |
70075 |
481 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5421 |
0 |
0 |
T80 |
4814 |
5 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
74 |
0 |
0 |
T112 |
10109 |
169 |
0 |
0 |
T113 |
90362 |
189 |
0 |
0 |
T120 |
181112 |
478 |
0 |
0 |
T142 |
18572 |
52 |
0 |
0 |
T143 |
6011 |
48 |
0 |
0 |
T144 |
33683 |
283 |
0 |
0 |
T145 |
70075 |
446 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
5903 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
14 |
0 |
0 |
T103 |
16413 |
90 |
0 |
0 |
T112 |
10109 |
52 |
0 |
0 |
T113 |
90362 |
239 |
0 |
0 |
T120 |
181112 |
472 |
0 |
0 |
T142 |
18572 |
27 |
0 |
0 |
T143 |
6011 |
79 |
0 |
0 |
T144 |
33683 |
289 |
0 |
0 |
T145 |
70075 |
596 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2890 |
0 |
0 |
T80 |
4814 |
5 |
0 |
0 |
T81 |
4982 |
2 |
0 |
0 |
T103 |
16413 |
26 |
0 |
0 |
T112 |
10109 |
8 |
0 |
0 |
T113 |
90362 |
232 |
0 |
0 |
T120 |
181112 |
390 |
0 |
0 |
T142 |
18572 |
28 |
0 |
0 |
T143 |
6011 |
10 |
0 |
0 |
T144 |
33683 |
56 |
0 |
0 |
T145 |
70075 |
103 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3246 |
0 |
0 |
T80 |
4814 |
13 |
0 |
0 |
T81 |
4982 |
7 |
0 |
0 |
T103 |
16413 |
20 |
0 |
0 |
T112 |
10109 |
29 |
0 |
0 |
T113 |
90362 |
249 |
0 |
0 |
T120 |
181112 |
474 |
0 |
0 |
T142 |
18572 |
60 |
0 |
0 |
T143 |
6011 |
12 |
0 |
0 |
T144 |
33683 |
66 |
0 |
0 |
T145 |
70075 |
136 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2942 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
8 |
0 |
0 |
T103 |
16413 |
25 |
0 |
0 |
T112 |
10109 |
13 |
0 |
0 |
T113 |
90362 |
233 |
0 |
0 |
T120 |
181112 |
441 |
0 |
0 |
T142 |
18572 |
35 |
0 |
0 |
T143 |
6011 |
9 |
0 |
0 |
T144 |
33683 |
72 |
0 |
0 |
T145 |
70075 |
139 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3086 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
34 |
0 |
0 |
T112 |
10109 |
20 |
0 |
0 |
T113 |
90362 |
236 |
0 |
0 |
T120 |
181112 |
454 |
0 |
0 |
T142 |
18572 |
50 |
0 |
0 |
T143 |
6011 |
11 |
0 |
0 |
T144 |
33683 |
71 |
0 |
0 |
T145 |
70075 |
140 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3482 |
0 |
0 |
T80 |
4814 |
21 |
0 |
0 |
T81 |
4982 |
7 |
0 |
0 |
T103 |
16413 |
37 |
0 |
0 |
T112 |
10109 |
45 |
0 |
0 |
T113 |
90362 |
239 |
0 |
0 |
T120 |
181112 |
455 |
0 |
0 |
T142 |
18572 |
13 |
0 |
0 |
T143 |
6011 |
16 |
0 |
0 |
T144 |
33683 |
117 |
0 |
0 |
T145 |
70075 |
211 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
4719 |
0 |
0 |
T23 |
275690 |
22 |
0 |
0 |
T87 |
238542 |
0 |
0 |
0 |
T147 |
0 |
1 |
0 |
0 |
T148 |
0 |
23 |
0 |
0 |
T149 |
0 |
20 |
0 |
0 |
T150 |
0 |
20 |
0 |
0 |
T151 |
0 |
27 |
0 |
0 |
T152 |
0 |
23 |
0 |
0 |
T153 |
0 |
40 |
0 |
0 |
T154 |
0 |
4 |
0 |
0 |
T155 |
0 |
48 |
0 |
0 |
T156 |
684174 |
0 |
0 |
0 |
T157 |
200131 |
0 |
0 |
0 |
T158 |
383450 |
0 |
0 |
0 |
T159 |
2664 |
0 |
0 |
0 |
T160 |
34108 |
0 |
0 |
0 |
T161 |
1304 |
0 |
0 |
0 |
T162 |
55106 |
0 |
0 |
0 |
T163 |
1937 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3067 |
0 |
0 |
T80 |
4814 |
17 |
0 |
0 |
T81 |
4982 |
18 |
0 |
0 |
T103 |
16413 |
34 |
0 |
0 |
T112 |
10109 |
8 |
0 |
0 |
T113 |
90362 |
215 |
0 |
0 |
T120 |
181112 |
460 |
0 |
0 |
T142 |
18572 |
25 |
0 |
0 |
T143 |
6011 |
10 |
0 |
0 |
T144 |
33683 |
58 |
0 |
0 |
T145 |
70075 |
103 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3009 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T98 |
21320 |
7 |
0 |
0 |
T103 |
16413 |
31 |
0 |
0 |
T112 |
10109 |
15 |
0 |
0 |
T113 |
90362 |
229 |
0 |
0 |
T120 |
181112 |
398 |
0 |
0 |
T142 |
18572 |
22 |
0 |
0 |
T143 |
6011 |
5 |
0 |
0 |
T144 |
33683 |
36 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2875 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
6 |
0 |
0 |
T103 |
16413 |
16 |
0 |
0 |
T112 |
10109 |
14 |
0 |
0 |
T113 |
90362 |
256 |
0 |
0 |
T120 |
181112 |
449 |
0 |
0 |
T142 |
18572 |
22 |
0 |
0 |
T143 |
6011 |
16 |
0 |
0 |
T144 |
33683 |
47 |
0 |
0 |
T145 |
70075 |
72 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2771 |
0 |
0 |
T80 |
4814 |
8 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T98 |
21320 |
3 |
0 |
0 |
T103 |
16413 |
19 |
0 |
0 |
T112 |
10109 |
18 |
0 |
0 |
T113 |
90362 |
216 |
0 |
0 |
T120 |
181112 |
447 |
0 |
0 |
T142 |
18572 |
51 |
0 |
0 |
T143 |
6011 |
8 |
0 |
0 |
T144 |
33683 |
49 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2767 |
0 |
0 |
T80 |
4814 |
17 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
36 |
0 |
0 |
T112 |
10109 |
12 |
0 |
0 |
T113 |
90362 |
228 |
0 |
0 |
T120 |
181112 |
470 |
0 |
0 |
T142 |
18572 |
13 |
0 |
0 |
T143 |
6011 |
5 |
0 |
0 |
T144 |
33683 |
33 |
0 |
0 |
T145 |
70075 |
92 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2886 |
0 |
0 |
T80 |
4814 |
11 |
0 |
0 |
T81 |
4982 |
4 |
0 |
0 |
T103 |
16413 |
27 |
0 |
0 |
T112 |
10109 |
18 |
0 |
0 |
T113 |
90362 |
235 |
0 |
0 |
T120 |
181112 |
478 |
0 |
0 |
T142 |
18572 |
32 |
0 |
0 |
T143 |
6011 |
13 |
0 |
0 |
T144 |
33683 |
46 |
0 |
0 |
T145 |
70075 |
71 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3401 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
8 |
0 |
0 |
T103 |
16413 |
48 |
0 |
0 |
T112 |
10109 |
18 |
0 |
0 |
T113 |
90362 |
239 |
0 |
0 |
T120 |
181112 |
437 |
0 |
0 |
T142 |
18572 |
19 |
0 |
0 |
T143 |
6011 |
23 |
0 |
0 |
T144 |
33683 |
113 |
0 |
0 |
T145 |
70075 |
224 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2710 |
0 |
0 |
T80 |
4814 |
5 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
15 |
0 |
0 |
T112 |
10109 |
9 |
0 |
0 |
T113 |
90362 |
248 |
0 |
0 |
T120 |
181112 |
438 |
0 |
0 |
T142 |
18572 |
44 |
0 |
0 |
T143 |
6011 |
15 |
0 |
0 |
T144 |
33683 |
49 |
0 |
0 |
T145 |
70075 |
84 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
3802 |
0 |
0 |
T80 |
4814 |
2 |
0 |
0 |
T81 |
4982 |
12 |
0 |
0 |
T91 |
8482 |
1 |
0 |
0 |
T103 |
16413 |
47 |
0 |
0 |
T112 |
10109 |
33 |
0 |
0 |
T113 |
90362 |
231 |
0 |
0 |
T120 |
181112 |
470 |
0 |
0 |
T142 |
18572 |
26 |
0 |
0 |
T143 |
6011 |
3 |
0 |
0 |
T144 |
33683 |
72 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2987 |
0 |
0 |
T80 |
4814 |
6 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
30 |
0 |
0 |
T112 |
10109 |
22 |
0 |
0 |
T113 |
90362 |
221 |
0 |
0 |
T120 |
181112 |
466 |
0 |
0 |
T142 |
18572 |
41 |
0 |
0 |
T143 |
6011 |
12 |
0 |
0 |
T144 |
33683 |
72 |
0 |
0 |
T145 |
70075 |
117 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2907 |
0 |
0 |
T80 |
4814 |
6 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T91 |
8482 |
6 |
0 |
0 |
T103 |
16413 |
27 |
0 |
0 |
T112 |
10109 |
13 |
0 |
0 |
T113 |
90362 |
245 |
0 |
0 |
T120 |
181112 |
464 |
0 |
0 |
T142 |
18572 |
13 |
0 |
0 |
T143 |
6011 |
12 |
0 |
0 |
T144 |
33683 |
28 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2771 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
9 |
0 |
0 |
T103 |
16413 |
16 |
0 |
0 |
T112 |
10109 |
19 |
0 |
0 |
T113 |
90362 |
224 |
0 |
0 |
T120 |
181112 |
455 |
0 |
0 |
T142 |
18572 |
39 |
0 |
0 |
T143 |
6011 |
4 |
0 |
0 |
T144 |
33683 |
43 |
0 |
0 |
T145 |
70075 |
72 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2776 |
0 |
0 |
T80 |
4814 |
10 |
0 |
0 |
T81 |
4982 |
5 |
0 |
0 |
T103 |
16413 |
12 |
0 |
0 |
T112 |
10109 |
16 |
0 |
0 |
T113 |
90362 |
214 |
0 |
0 |
T120 |
181112 |
503 |
0 |
0 |
T142 |
18572 |
48 |
0 |
0 |
T143 |
6011 |
13 |
0 |
0 |
T144 |
33683 |
39 |
0 |
0 |
T145 |
70075 |
88 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2791 |
0 |
0 |
T80 |
4814 |
19 |
0 |
0 |
T81 |
4982 |
19 |
0 |
0 |
T103 |
16413 |
29 |
0 |
0 |
T112 |
10109 |
13 |
0 |
0 |
T113 |
90362 |
228 |
0 |
0 |
T120 |
181112 |
455 |
0 |
0 |
T142 |
18572 |
56 |
0 |
0 |
T143 |
6011 |
2 |
0 |
0 |
T144 |
33683 |
34 |
0 |
0 |
T145 |
70075 |
79 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2853 |
0 |
0 |
T80 |
4814 |
18 |
0 |
0 |
T81 |
4982 |
11 |
0 |
0 |
T103 |
16413 |
19 |
0 |
0 |
T112 |
10109 |
7 |
0 |
0 |
T113 |
90362 |
268 |
0 |
0 |
T120 |
181112 |
533 |
0 |
0 |
T142 |
18572 |
8 |
0 |
0 |
T143 |
6011 |
5 |
0 |
0 |
T144 |
33683 |
44 |
0 |
0 |
T145 |
70075 |
64 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
344058805 |
2701 |
0 |
0 |
T80 |
4814 |
12 |
0 |
0 |
T81 |
4982 |
13 |
0 |
0 |
T103 |
16413 |
17 |
0 |
0 |
T112 |
10109 |
13 |
0 |
0 |
T113 |
90362 |
239 |
0 |
0 |
T120 |
181112 |
417 |
0 |
0 |
T142 |
18572 |
17 |
0 |
0 |
T143 |
6011 |
2 |
0 |
0 |
T144 |
33683 |
25 |
0 |
0 |
T145 |
70075 |
97 |
0 |
0 |