Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	455	1			T3	5		T6	8		T11	11
all_values[1]	455	1			T3	5		T6	8		T11	11
all_values[2]	455	1			T3	5		T6	8		T11	11
all_values[3]	455	1			T3	5		T6	8		T11	11
all_values[4]	455	1			T3	5		T6	8		T11	11
all_values[5]	455	1			T3	5		T6	8		T11	11
all_values[6]	455	1			T3	5		T6	8		T11	11
all_values[7]	455	1			T3	5		T6	8		T11	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1920

1

T3

17

T6

27

T11

42

auto[1]

1720

1

T3

23

T6

37

T11

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2187

1

T3

19

T6

42

T11

43

auto[1]

1453

1

T3

21

T6

22

T11

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	163	1			T3	1		T6	3		T11	4
all_values[0]	auto[0]	auto[1]	90	1			T3	2		T12	3		T67	2
all_values[0]	auto[1]	auto[0]	125	1			T3	1		T6	3		T11	2
all_values[0]	auto[1]	auto[1]	77	1			T3	1		T6	2		T11	5
all_values[1]	auto[0]	auto[0]	143	1			T3	2		T6	3		T11	1
all_values[1]	auto[0]	auto[1]	102	1			T3	2		T6	2		T11	4
all_values[1]	auto[1]	auto[0]	111	1			T3	1		T11	1		T12	1
all_values[1]	auto[1]	auto[1]	99	1			T6	3		T11	5		T12	3
all_values[2]	auto[0]	auto[0]	138	1			T3	1		T6	2		T11	2
all_values[2]	auto[0]	auto[1]	86	1			T3	2		T11	2		T12	1
all_values[2]	auto[1]	auto[0]	142	1			T3	2		T6	5		T11	3
all_values[2]	auto[1]	auto[1]	89	1			T6	1		T11	4		T12	1
all_values[3]	auto[0]	auto[0]	136	1			T3	2		T6	1		T11	2
all_values[3]	auto[0]	auto[1]	93	1			T3	2		T6	2		T11	2
all_values[3]	auto[1]	auto[0]	137	1			T6	3		T11	4		T12	3
all_values[3]	auto[1]	auto[1]	89	1			T3	1		T6	2		T11	3
all_values[4]	auto[0]	auto[0]	122	1			T3	1		T6	1		T11	1
all_values[4]	auto[0]	auto[1]	100	1			T6	1		T11	6		T12	2
all_values[4]	auto[1]	auto[0]	128	1			T3	2		T6	4		T11	2
all_values[4]	auto[1]	auto[1]	105	1			T3	2		T6	2		T11	2
all_values[5]	auto[0]	auto[0]	157	1			T6	2		T11	3		T12	4
all_values[5]	auto[0]	auto[1]	86	1			T3	1		T6	1		T11	2
all_values[5]	auto[1]	auto[0]	133	1			T3	2		T6	4		T11	4
all_values[5]	auto[1]	auto[1]	79	1			T3	2		T6	1		T11	2
all_values[6]	auto[0]	auto[0]	147	1			T6	3		T11	3		T12	5
all_values[6]	auto[0]	auto[1]	90	1			T11	5		T12	2		T66	3
all_values[6]	auto[1]	auto[0]	124	1			T3	2		T6	4		T11	2
all_values[6]	auto[1]	auto[1]	94	1			T3	3		T6	1		T11	1
all_values[7]	auto[0]	auto[0]	180	1			T3	1		T6	3		T11	5
all_values[7]	auto[0]	auto[1]	87	1			T6	3		T12	2		T66	2
all_values[7]	auto[1]	auto[0]	101	1			T3	1		T6	1		T11	4
all_values[7]	auto[1]	auto[1]	87	1			T3	3		T6	1		T11	2