Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
59.33 70.94 74.27 75.00 0.00 76.99 100.00 18.12


Total tests in report: 175
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.80 55.80 70.47 70.47 71.28 71.28 82.92 82.92 0.00 0.00 76.58 76.58 82.00 82.00 7.38 7.38 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3522456439
58.44 2.63 70.47 0.00 71.47 0.19 83.37 0.46 0.00 0.00 76.63 0.05 98.25 16.25 8.86 1.49 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2139677120
59.96 1.52 70.76 0.30 72.25 0.78 85.65 2.28 0.00 0.00 76.95 0.32 98.25 0.00 15.84 6.98 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.833294795
60.48 0.52 70.78 0.02 73.24 0.98 86.79 1.14 0.00 0.00 76.99 0.03 98.50 0.25 17.03 1.19 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4209226477
60.72 0.24 70.93 0.15 73.29 0.05 86.79 0.00 0.00 0.00 76.99 0.00 100.00 1.50 17.03 0.00 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4251783623
60.86 0.15 70.93 0.00 74.16 0.87 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 17.18 0.15 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4120286740
60.93 0.07 70.93 0.00 74.16 0.00 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 17.67 0.50 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2342594007
60.97 0.04 70.93 0.00 74.16 0.00 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 17.92 0.25 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3058989339
60.99 0.02 70.93 0.00 74.24 0.09 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 17.97 0.05 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.212898482
61.00 0.01 70.94 0.01 74.24 0.00 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 18.02 0.05 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3638299359
61.00 0.01 70.94 0.00 74.24 0.00 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 18.07 0.05 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1125928308
61.01 0.01 70.94 0.00 74.24 0.00 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 18.12 0.05 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.545525862
61.01 0.01 70.94 0.00 74.27 0.02 86.79 0.00 0.00 0.00 76.99 0.00 100.00 0.00 18.12 0.00 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.614138733

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1807718171
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3368411606
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.909453318
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.281252371
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3002189053
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.821615426
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3605269861
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1261080182
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2024911104
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2634397415
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2577637286
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3225250874
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1644650206
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.4027135871
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1184146203
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4107460870
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2966706736
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3431522768
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.980632846
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1825325707
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2352592929
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1596235954
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3827846711
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.215457939
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1172051588
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3127331314
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1171516642
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3151903161
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.856563964
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2471376124
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3019838829
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2267572685
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1796033991
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3213285550
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1123375724
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2877423417
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1807558785
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4071837327
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2074739557
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1040209505
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.1046979836
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1105521661
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.846874098
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3927422074
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.146998832
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2489464609
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.2124863489
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1406142207
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1962014187
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2811466309
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.508075042
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.4099843311
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4178030198
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2666543562
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1883332457
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1611293496
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1681349172
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1672406835
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3132449693
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1823845453
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1965938069
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2981892208
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3369808340
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3796741704
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2985294545
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4000162943
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2850552326
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.319800695
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3114566943
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1818773122
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.999471947
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.854529346
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.79400607
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2376628812
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3867407223
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.580708291
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3564880093
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3622258607
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1646232716
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2963014332
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2041757527
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4138493972
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3693644544
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.2762259442
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3822961926
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.4283232846
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3579534597
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.4074583760
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.3917665631
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.4293557216
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1663559967
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1447385413
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2446126316
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2794362260
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3698493146
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3211993253
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.327908166
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.372782224
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1880813053
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1944341079
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1489620901
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1683011829
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2112862237
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1788507314
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2418076379
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.4160435084
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2436268693
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1551222806
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3796927298
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.1971702512
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2887042712
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.3361492875
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.642297881
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3336872836
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2880480240
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1614947936
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3437965764
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.53282295
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3301369972
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.492756091
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2984257612
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1687661089
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3719929212
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3582342640
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1573951028
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3037984323
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.4032730601
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3838002483
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3978587786
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3959741834
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2351654894
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1362578928
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.2297357449
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3337748343
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2137936440
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3527302605
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2738279531
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1444710157
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1763754176
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2985989879
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3336219748
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2754466284
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3636691890
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3035632461
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.13702316
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1083699361
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.930475271
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1033464138
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.988698007
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3775218957
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2006514693
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1806120814
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.4040295681
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.952858177
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2295242171
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3175940955
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1155931395
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.406348379
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1294328936
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3166966595
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.411623223
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1160443141



Total test records in report: 175
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3522456439 Aug 14 04:29:11 PM PDT 24 Aug 14 04:29:14 PM PDT 24 752345671 ps
T2 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3638299359 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:45 PM PDT 24 1962736663 ps
T3 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2436268693 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:32 PM PDT 24 19654151 ps
T6 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.642297881 Aug 14 04:29:33 PM PDT 24 Aug 14 04:29:34 PM PDT 24 41586885 ps
T10 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.281252371 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:14 PM PDT 24 132582519 ps
T7 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1184146203 Aug 14 04:29:14 PM PDT 24 Aug 14 04:29:16 PM PDT 24 81149664 ps
T4 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3636691890 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:23 PM PDT 24 417528120 ps
T13 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.508075042 Aug 14 04:29:34 PM PDT 24 Aug 14 04:29:35 PM PDT 24 64108827 ps
T14 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4178030198 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:23 PM PDT 24 45476905 ps
T11 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.833294795 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:37 PM PDT 24 21037876 ps
T24 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3622258607 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:21 PM PDT 24 65394217 ps
T5 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.909453318 Aug 14 04:29:14 PM PDT 24 Aug 14 04:29:16 PM PDT 24 39084736 ps
T12 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1046979836 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:27 PM PDT 24 13888019 ps
T25 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3213285550 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:23 PM PDT 24 41090718 ps
T8 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1823845453 Aug 14 04:29:32 PM PDT 24 Aug 14 04:29:34 PM PDT 24 85214388 ps
T9 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1763754176 Aug 14 04:29:03 PM PDT 24 Aug 14 04:29:10 PM PDT 24 107065587 ps
T26 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4209226477 Aug 14 04:29:50 PM PDT 24 Aug 14 04:29:57 PM PDT 24 358466986 ps
T15 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4120286740 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:25 PM PDT 24 83689523 ps
T27 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2880480240 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:38 PM PDT 24 1350911414 ps
T16 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3225250874 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:35 PM PDT 24 106393454 ps
T28 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3431522768 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:19 PM PDT 24 587307319 ps
T70 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2634397415 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:45 PM PDT 24 1237755873 ps
T17 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3301369972 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:32 PM PDT 24 161472570 ps
T40 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3698493146 Aug 14 04:29:16 PM PDT 24 Aug 14 04:29:17 PM PDT 24 41703265 ps
T29 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1806120814 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:14 PM PDT 24 85665959 ps
T18 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3564880093 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:23 PM PDT 24 66938249 ps
T71 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.492756091 Aug 14 04:29:06 PM PDT 24 Aug 14 04:29:07 PM PDT 24 33376253 ps
T51 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2794362260 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:44 PM PDT 24 7564433423 ps
T38 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.952858177 Aug 14 04:29:37 PM PDT 24 Aug 14 04:29:40 PM PDT 24 168988861 ps
T39 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1105521661 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:40 PM PDT 24 762099610 ps
T66 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3959741834 Aug 14 04:29:44 PM PDT 24 Aug 14 04:29:45 PM PDT 24 23928622 ps
T19 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1444710157 Aug 14 04:29:06 PM PDT 24 Aug 14 04:29:09 PM PDT 24 79503635 ps
T72 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2041757527 Aug 14 04:29:11 PM PDT 24 Aug 14 04:29:12 PM PDT 24 11520759 ps
T56 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1672406835 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:25 PM PDT 24 18725481 ps
T30 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3114566943 Aug 14 04:29:34 PM PDT 24 Aug 14 04:29:37 PM PDT 24 194393090 ps
T41 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.614138733 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:13 PM PDT 24 153963342 ps
T20 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1683011829 Aug 14 04:29:17 PM PDT 24 Aug 14 04:29:22 PM PDT 24 82365832 ps
T68 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3037984323 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:25 PM PDT 24 21157639 ps
T73 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1596235954 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:34 PM PDT 24 457689161 ps
T21 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2139677120 Aug 14 04:29:43 PM PDT 24 Aug 14 04:29:47 PM PDT 24 156726792 ps
T31 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1807718171 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:45 PM PDT 24 1807673497 ps
T67 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2342594007 Aug 14 04:29:24 PM PDT 24 Aug 14 04:29:25 PM PDT 24 82347454 ps
T69 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3822961926 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 14037747 ps
T59 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2112862237 Aug 14 04:29:17 PM PDT 24 Aug 14 04:29:29 PM PDT 24 203554335 ps
T74 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1971702512 Aug 14 04:29:27 PM PDT 24 Aug 14 04:29:27 PM PDT 24 30639457 ps
T75 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1123375724 Aug 14 04:29:17 PM PDT 24 Aug 14 04:29:18 PM PDT 24 31714837 ps
T22 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4138493972 Aug 14 04:29:02 PM PDT 24 Aug 14 04:29:05 PM PDT 24 265830546 ps
T76 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3579534597 Aug 14 04:29:44 PM PDT 24 Aug 14 04:29:45 PM PDT 24 44596955 ps
T77 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4040295681 Aug 14 04:29:35 PM PDT 24 Aug 14 04:29:36 PM PDT 24 29779456 ps
T23 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.988698007 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:28 PM PDT 24 460954888 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2577637286 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:58 PM PDT 24 3747397741 ps
T32 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1681349172 Aug 14 04:29:32 PM PDT 24 Aug 14 04:29:34 PM PDT 24 37336686 ps
T33 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4251783623 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:32 PM PDT 24 40601638 ps
T79 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.930475271 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:13 PM PDT 24 13801785 ps
T80 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3838002483 Aug 14 04:29:38 PM PDT 24 Aug 14 04:29:38 PM PDT 24 13145387 ps
T58 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2850552326 Aug 14 04:29:39 PM PDT 24 Aug 14 04:29:54 PM PDT 24 4434557711 ps
T49 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3035632461 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:29 PM PDT 24 97153270 ps
T52 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2877423417 Aug 14 04:29:24 PM PDT 24 Aug 14 04:29:26 PM PDT 24 59727265 ps
T50 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.13702316 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:24 PM PDT 24 238698966 ps
T81 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.319800695 Aug 14 04:29:24 PM PDT 24 Aug 14 04:29:27 PM PDT 24 266429263 ps
T44 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1807558785 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:32 PM PDT 24 206113162 ps
T36 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2963014332 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:20 PM PDT 24 17131524 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3002189053 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:22 PM PDT 24 54673577 ps
T57 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2666543562 Aug 14 04:29:13 PM PDT 24 Aug 14 04:29:16 PM PDT 24 149982773 ps
T46 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2024911104 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:25 PM PDT 24 70524005 ps
T83 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2887042712 Aug 14 04:29:41 PM PDT 24 Aug 14 04:29:42 PM PDT 24 13268535 ps
T84 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2754466284 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:21 PM PDT 24 21600340 ps
T62 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1125928308 Aug 14 04:29:02 PM PDT 24 Aug 14 04:29:09 PM PDT 24 961137259 ps
T45 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2985989879 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:28 PM PDT 24 307834374 ps
T85 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1155931395 Aug 14 04:29:29 PM PDT 24 Aug 14 04:29:33 PM PDT 24 53772363 ps
T86 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2351654894 Aug 14 04:29:29 PM PDT 24 Aug 14 04:29:30 PM PDT 24 13463560 ps
T34 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.406348379 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:20 PM PDT 24 190290741 ps
T65 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3058989339 Aug 14 04:29:39 PM PDT 24 Aug 14 04:29:50 PM PDT 24 201394307 ps
T87 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3151903161 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:32 PM PDT 24 612738707 ps
T47 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.411623223 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:23 PM PDT 24 61153435 ps
T53 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.856563964 Aug 14 04:29:23 PM PDT 24 Aug 14 04:29:26 PM PDT 24 224268692 ps
T63 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.79400607 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:32 PM PDT 24 408719237 ps
T88 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4160435084 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:32 PM PDT 24 20276145 ps
T89 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2762259442 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 225968339 ps
T43 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.846874098 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:25 PM PDT 24 201609762 ps
T90 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3867407223 Aug 14 04:29:11 PM PDT 24 Aug 14 04:29:23 PM PDT 24 739477560 ps
T35 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1040209505 Aug 14 04:29:23 PM PDT 24 Aug 14 04:29:24 PM PDT 24 52540551 ps
T91 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3527302605 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:40 PM PDT 24 54428446 ps
T92 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1944341079 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:23 PM PDT 24 55056143 ps
T93 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.146998832 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 187292197 ps
T60 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2811466309 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:34 PM PDT 24 2039871987 ps
T48 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3827846711 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:30 PM PDT 24 35724613 ps
T94 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4293557216 Aug 14 04:30:05 PM PDT 24 Aug 14 04:30:06 PM PDT 24 14581546 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.372782224 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:20 PM PDT 24 12558613 ps
T96 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.212898482 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:32 PM PDT 24 247196229 ps
T54 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1160443141 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:44 PM PDT 24 3759605357 ps
T64 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1965938069 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:50 PM PDT 24 558334634 ps
T55 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3693644544 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:46 PM PDT 24 677019204 ps
T97 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2074739557 Aug 14 04:29:35 PM PDT 24 Aug 14 04:29:38 PM PDT 24 42855605 ps
T98 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1171516642 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:20 PM PDT 24 14548315 ps
T99 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4107460870 Aug 14 04:29:16 PM PDT 24 Aug 14 04:29:17 PM PDT 24 13645879 ps
T100 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2418076379 Aug 14 04:29:37 PM PDT 24 Aug 14 04:29:37 PM PDT 24 13561716 ps
T101 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3175940955 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:29 PM PDT 24 327792163 ps
T102 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1883332457 Aug 14 04:29:27 PM PDT 24 Aug 14 04:29:43 PM PDT 24 803666937 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3211993253 Aug 14 04:29:06 PM PDT 24 Aug 14 04:29:08 PM PDT 24 210825731 ps
T104 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4000162943 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:46 PM PDT 24 2061370443 ps
T105 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1172051588 Aug 14 04:29:27 PM PDT 24 Aug 14 04:29:35 PM PDT 24 87997200 ps
T37 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1825325707 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:28 PM PDT 24 119540099 ps
T106 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1788507314 Aug 14 04:29:24 PM PDT 24 Aug 14 04:29:25 PM PDT 24 15241177 ps
T107 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3978587786 Aug 14 04:29:57 PM PDT 24 Aug 14 04:29:58 PM PDT 24 38899275 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3368411606 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:23 PM PDT 24 45229247 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.327908166 Aug 14 04:29:31 PM PDT 24 Aug 14 04:29:33 PM PDT 24 34925671 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1644650206 Aug 14 04:29:18 PM PDT 24 Aug 14 04:29:21 PM PDT 24 350549413 ps
T111 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3582342640 Aug 14 04:29:29 PM PDT 24 Aug 14 04:29:29 PM PDT 24 13592179 ps
T112 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.545525862 Aug 14 04:29:45 PM PDT 24 Aug 14 04:30:00 PM PDT 24 1223215776 ps
T113 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2738279531 Aug 14 04:29:18 PM PDT 24 Aug 14 04:29:19 PM PDT 24 83780001 ps
T114 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2297357449 Aug 14 04:29:32 PM PDT 24 Aug 14 04:29:33 PM PDT 24 22058191 ps
T115 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1818773122 Aug 14 04:29:33 PM PDT 24 Aug 14 04:29:34 PM PDT 24 11726807 ps
T116 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1261080182 Aug 14 04:29:13 PM PDT 24 Aug 14 04:29:18 PM PDT 24 422855917 ps
T117 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2489464609 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:27 PM PDT 24 70961160 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2295242171 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:23 PM PDT 24 184001536 ps
T119 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3361492875 Aug 14 04:29:41 PM PDT 24 Aug 14 04:29:42 PM PDT 24 90195683 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3719929212 Aug 14 04:29:12 PM PDT 24 Aug 14 04:29:21 PM PDT 24 766055357 ps
T121 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4032730601 Aug 14 04:29:51 PM PDT 24 Aug 14 04:29:52 PM PDT 24 12920456 ps
T42 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.580708291 Aug 14 04:29:02 PM PDT 24 Aug 14 04:29:04 PM PDT 24 41474139 ps
T122 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3127331314 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:23 PM PDT 24 339657422 ps
T123 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3166966595 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:27 PM PDT 24 28593760 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2376628812 Aug 14 04:29:06 PM PDT 24 Aug 14 04:29:27 PM PDT 24 309136503 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2446126316 Aug 14 04:29:06 PM PDT 24 Aug 14 04:29:20 PM PDT 24 825868032 ps
T61 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.215457939 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:55 PM PDT 24 848097604 ps
T126 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4099843311 Aug 14 04:29:26 PM PDT 24 Aug 14 04:29:27 PM PDT 24 14341310 ps
T127 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1611293496 Aug 14 04:29:43 PM PDT 24 Aug 14 04:29:47 PM PDT 24 64240395 ps
T128 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3927422074 Aug 14 04:29:29 PM PDT 24 Aug 14 04:29:42 PM PDT 24 704165143 ps
T129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3369808340 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:29 PM PDT 24 110378647 ps
T130 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2137936440 Aug 14 04:29:14 PM PDT 24 Aug 14 04:29:16 PM PDT 24 175126131 ps
T131 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1573951028 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 14783273 ps
T132 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4071837327 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:48 PM PDT 24 285860339 ps
T133 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2471376124 Aug 14 04:29:29 PM PDT 24 Aug 14 04:29:30 PM PDT 24 21045614 ps
T134 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.854529346 Aug 14 04:29:15 PM PDT 24 Aug 14 04:29:16 PM PDT 24 118170427 ps
T135 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3337748343 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:26 PM PDT 24 44197392 ps
T136 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1294328936 Aug 14 04:29:47 PM PDT 24 Aug 14 04:29:48 PM PDT 24 38942201 ps
T137 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.821615426 Aug 14 04:29:03 PM PDT 24 Aug 14 04:29:05 PM PDT 24 22752671 ps
T138 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3775218957 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:40 PM PDT 24 1169976633 ps
T139 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4283232846 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:26 PM PDT 24 16197343 ps
T140 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4074583760 Aug 14 04:29:27 PM PDT 24 Aug 14 04:29:28 PM PDT 24 17273500 ps
T141 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.980632846 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:28 PM PDT 24 54944993 ps
T142 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1447385413 Aug 14 04:29:21 PM PDT 24 Aug 14 04:29:22 PM PDT 24 39708055 ps
T143 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3019838829 Aug 14 04:29:18 PM PDT 24 Aug 14 04:29:20 PM PDT 24 218423582 ps
T144 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2966706736 Aug 14 04:29:09 PM PDT 24 Aug 14 04:29:13 PM PDT 24 3691044094 ps
T145 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2984257612 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 228155391 ps
T146 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3132449693 Aug 14 04:29:11 PM PDT 24 Aug 14 04:29:14 PM PDT 24 108062003 ps
T147 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1551222806 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:31 PM PDT 24 34139894 ps
T148 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1663559967 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:41 PM PDT 24 15381633 ps
T149 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3336219748 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:42 PM PDT 24 81887456 ps
T150 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2352592929 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:25 PM PDT 24 14825593 ps
T151 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1406142207 Aug 14 04:29:41 PM PDT 24 Aug 14 04:29:46 PM PDT 24 58940916 ps
T152 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1880813053 Aug 14 04:29:05 PM PDT 24 Aug 14 04:29:07 PM PDT 24 29106658 ps
T153 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3796927298 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:20 PM PDT 24 13995044 ps
T154 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2981892208 Aug 14 04:29:19 PM PDT 24 Aug 14 04:29:22 PM PDT 24 49444559 ps
T155 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.999471947 Aug 14 04:29:34 PM PDT 24 Aug 14 04:29:37 PM PDT 24 212295917 ps
T156 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3917665631 Aug 14 04:29:33 PM PDT 24 Aug 14 04:29:34 PM PDT 24 40752747 ps
T157 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4027135871 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:23 PM PDT 24 38076787 ps
T158 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2124863489 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:37 PM PDT 24 11843359 ps
T159 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2006514693 Aug 14 04:29:51 PM PDT 24 Aug 14 04:29:54 PM PDT 24 171611940 ps
T160 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1614947936 Aug 14 04:29:17 PM PDT 24 Aug 14 04:29:20 PM PDT 24 52846228 ps
T161 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1083699361 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:30 PM PDT 24 62409407 ps
T162 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1962014187 Aug 14 04:29:24 PM PDT 24 Aug 14 04:29:26 PM PDT 24 87287111 ps
T163 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1796033991 Aug 14 04:29:28 PM PDT 24 Aug 14 04:29:32 PM PDT 24 577849611 ps
T164 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1687661089 Aug 14 04:29:17 PM PDT 24 Aug 14 04:29:19 PM PDT 24 68645015 ps
T165 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1362578928 Aug 14 04:29:49 PM PDT 24 Aug 14 04:29:50 PM PDT 24 50229244 ps
T166 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3605269861 Aug 14 04:29:22 PM PDT 24 Aug 14 04:29:22 PM PDT 24 10829349 ps
T167 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.53282295 Aug 14 04:29:07 PM PDT 24 Aug 14 04:29:08 PM PDT 24 25494967 ps
T168 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1489620901 Aug 14 04:29:25 PM PDT 24 Aug 14 04:29:28 PM PDT 24 371932186 ps
T169 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1033464138 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:43 PM PDT 24 227087636 ps
T170 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1646232716 Aug 14 04:29:23 PM PDT 24 Aug 14 04:29:24 PM PDT 24 29499567 ps
T171 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2267572685 Aug 14 04:29:30 PM PDT 24 Aug 14 04:29:34 PM PDT 24 166270738 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3437965764 Aug 14 04:29:13 PM PDT 24 Aug 14 04:29:15 PM PDT 24 85290478 ps
T173 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2985294545 Aug 14 04:29:34 PM PDT 24 Aug 14 04:29:37 PM PDT 24 101841518 ps
T174 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3336872836 Aug 14 04:29:18 PM PDT 24 Aug 14 04:29:37 PM PDT 24 1307601332 ps
T175 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3796741704 Aug 14 04:29:45 PM PDT 24 Aug 14 04:29:46 PM PDT 24 13870495 ps

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3522456439
Short name T1
Test name
Test status
Simulation time 752345671 ps
CPU time 2.77 seconds
Started Aug 14 04:29:11 PM PDT 24
Finished Aug 14 04:29:14 PM PDT 24
Peak memory 214984 kb
Host smart-1ea06b24-0caf-40a4-b507-a499b92428c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522456439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3522456439
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2139677120
Short name T21
Test name
Test status
Simulation time 156726792 ps
CPU time 3.73 seconds
Started Aug 14 04:29:43 PM PDT 24
Finished Aug 14 04:29:47 PM PDT 24
Peak memory 217168 kb
Host smart-b950cc48-e66b-4271-bbdc-8fec1816ec2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139677120 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2139677120
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.833294795
Short name T11
Test name
Test status
Simulation time 21037876 ps
CPU time 0.73 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 203948 kb
Host smart-2c2649e6-5f4a-4d2d-93eb-ad1467ff409c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833294795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.833294795
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4209226477
Short name T26
Test name
Test status
Simulation time 358466986 ps
CPU time 7.64 seconds
Started Aug 14 04:29:50 PM PDT 24
Finished Aug 14 04:29:57 PM PDT 24
Peak memory 215064 kb
Host smart-03d7490d-c72c-443c-8d50-f650fd3006ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209226477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4209226477
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4251783623
Short name T33
Test name
Test status
Simulation time 40601638 ps
CPU time 0.9 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 206716 kb
Host smart-0f65f9cb-8fdc-43bb-b258-83907046046c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251783623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4251783623
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4120286740
Short name T15
Test name
Test status
Simulation time 83689523 ps
CPU time 4.5 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 215220 kb
Host smart-ac5d55c3-beef-45a6-a957-a5d9676716e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120286740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
120286740
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2342594007
Short name T67
Test name
Test status
Simulation time 82347454 ps
CPU time 0.74 seconds
Started Aug 14 04:29:24 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 203640 kb
Host smart-4db5630e-e896-49ef-b218-97f5e1670141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342594007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2342594007
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3058989339
Short name T65
Test name
Test status
Simulation time 201394307 ps
CPU time 11.44 seconds
Started Aug 14 04:29:39 PM PDT 24
Finished Aug 14 04:29:50 PM PDT 24
Peak memory 215104 kb
Host smart-13f2fa7d-acc0-4259-a550-66336e503a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058989339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3058989339
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.212898482
Short name T96
Test name
Test status
Simulation time 247196229 ps
CPU time 6.01 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 215176 kb
Host smart-166132c4-5ea0-47dd-b6b1-960adbf1b3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212898482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.212898482
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3638299359
Short name T2
Test name
Test status
Simulation time 1962736663 ps
CPU time 26.4 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:45 PM PDT 24
Peak memory 206756 kb
Host smart-af850448-85c7-4362-a318-02e256f5bda6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638299359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3638299359
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1125928308
Short name T62
Test name
Test status
Simulation time 961137259 ps
CPU time 7.05 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:09 PM PDT 24
Peak memory 215652 kb
Host smart-c424951d-2005-437c-81d5-f26785b509d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125928308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1125928308
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.545525862
Short name T112
Test name
Test status
Simulation time 1223215776 ps
CPU time 15.18 seconds
Started Aug 14 04:29:45 PM PDT 24
Finished Aug 14 04:30:00 PM PDT 24
Peak memory 215320 kb
Host smart-c052bc84-e6c8-486f-b03b-3843dd227d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545525862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.545525862
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.614138733
Short name T41
Test name
Test status
Simulation time 153963342 ps
CPU time 1.51 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:13 PM PDT 24
Peak memory 206696 kb
Host smart-726703f1-4e5b-4ff9-8d18-5e0473b6f5ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614138733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.614138733
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1807718171
Short name T31
Test name
Test status
Simulation time 1807673497 ps
CPU time 23.57 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:45 PM PDT 24
Peak memory 206880 kb
Host smart-392910d5-c320-4cba-9899-e67963a86985
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807718171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1807718171
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3368411606
Short name T108
Test name
Test status
Simulation time 45229247 ps
CPU time 1.37 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 215968 kb
Host smart-5862415b-d13c-45e6-9d50-13a778daf448
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368411606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3368411606
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.909453318
Short name T5
Test name
Test status
Simulation time 39084736 ps
CPU time 1.78 seconds
Started Aug 14 04:29:14 PM PDT 24
Finished Aug 14 04:29:16 PM PDT 24
Peak memory 216148 kb
Host smart-57abff34-606d-484f-9416-20df6eef381c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909453318 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.909453318
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.281252371
Short name T10
Test name
Test status
Simulation time 132582519 ps
CPU time 2.28 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:14 PM PDT 24
Peak memory 214360 kb
Host smart-40741435-f124-468d-a838-2fa180f6c515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281252371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.281252371
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3002189053
Short name T82
Test name
Test status
Simulation time 54673577 ps
CPU time 0.76 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:22 PM PDT 24
Peak memory 203936 kb
Host smart-84e7b8a9-64a9-425e-ad65-c14f6d49b8f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002189053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
002189053
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.821615426
Short name T137
Test name
Test status
Simulation time 22752671 ps
CPU time 1.59 seconds
Started Aug 14 04:29:03 PM PDT 24
Finished Aug 14 04:29:05 PM PDT 24
Peak memory 215028 kb
Host smart-5e7c02a1-70e3-4aa7-85f0-253e9c65df6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821615426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.821615426
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3605269861
Short name T166
Test name
Test status
Simulation time 10829349 ps
CPU time 0.66 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:22 PM PDT 24
Peak memory 203484 kb
Host smart-0d50075c-82bf-4f8d-99b3-23bee097c758
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605269861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3605269861
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1261080182
Short name T116
Test name
Test status
Simulation time 422855917 ps
CPU time 4.33 seconds
Started Aug 14 04:29:13 PM PDT 24
Finished Aug 14 04:29:18 PM PDT 24
Peak memory 215044 kb
Host smart-4896d0db-a66b-4dd6-90de-53e72bf3bbf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261080182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1261080182
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2024911104
Short name T46
Test name
Test status
Simulation time 70524005 ps
CPU time 4.62 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 215208 kb
Host smart-695eced3-4eb9-4a9a-beac-aaba8ff80625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024911104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
024911104
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2634397415
Short name T70
Test name
Test status
Simulation time 1237755873 ps
CPU time 15.13 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:45 PM PDT 24
Peak memory 214964 kb
Host smart-871dc0cb-b897-47ee-98ce-ef909cc55e3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634397415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2634397415
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2577637286
Short name T78
Test name
Test status
Simulation time 3747397741 ps
CPU time 35.9 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:58 PM PDT 24
Peak memory 206788 kb
Host smart-5b8e9345-5954-4bb3-8733-76796e3395d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577637286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2577637286
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3225250874
Short name T16
Test name
Test status
Simulation time 106393454 ps
CPU time 3.55 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:35 PM PDT 24
Peak memory 217032 kb
Host smart-8b501080-d64e-4f2b-902d-2c95381c59b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225250874 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3225250874
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1644650206
Short name T110
Test name
Test status
Simulation time 350549413 ps
CPU time 2.43 seconds
Started Aug 14 04:29:18 PM PDT 24
Finished Aug 14 04:29:21 PM PDT 24
Peak memory 215120 kb
Host smart-570d1412-5b91-4b0f-b745-d0ded27e1e2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644650206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
644650206
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4027135871
Short name T157
Test name
Test status
Simulation time 38076787 ps
CPU time 0.7 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 203920 kb
Host smart-62b2582a-cd5f-4249-b6c1-4a8e79e5e475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027135871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
027135871
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1184146203
Short name T7
Test name
Test status
Simulation time 81149664 ps
CPU time 1.62 seconds
Started Aug 14 04:29:14 PM PDT 24
Finished Aug 14 04:29:16 PM PDT 24
Peak memory 215012 kb
Host smart-d5927816-9fea-4911-97a3-4fef66ea92aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184146203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1184146203
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4107460870
Short name T99
Test name
Test status
Simulation time 13645879 ps
CPU time 0.65 seconds
Started Aug 14 04:29:16 PM PDT 24
Finished Aug 14 04:29:17 PM PDT 24
Peak memory 203484 kb
Host smart-70af53b3-448e-4c3e-81b2-1f3681dfcb16
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107460870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4107460870
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2966706736
Short name T144
Test name
Test status
Simulation time 3691044094 ps
CPU time 3.87 seconds
Started Aug 14 04:29:09 PM PDT 24
Finished Aug 14 04:29:13 PM PDT 24
Peak memory 215028 kb
Host smart-966741a1-e647-47f8-9123-bbcf14c4c76e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966706736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2966706736
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3431522768
Short name T28
Test name
Test status
Simulation time 587307319 ps
CPU time 7.2 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:19 PM PDT 24
Peak memory 215456 kb
Host smart-b587d320-c03c-4f80-b286-9ae1e077f6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431522768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3431522768
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.980632846
Short name T141
Test name
Test status
Simulation time 54944993 ps
CPU time 3.26 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 217420 kb
Host smart-77c5c5ba-5bf5-40a2-94bf-e82941f50701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980632846 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.980632846
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1825325707
Short name T37
Test name
Test status
Simulation time 119540099 ps
CPU time 1.82 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 207028 kb
Host smart-afb55028-c48a-40b4-9e05-a7d88d1ed79b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825325707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1825325707
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2352592929
Short name T150
Test name
Test status
Simulation time 14825593 ps
CPU time 0.66 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 203664 kb
Host smart-64aa652c-314b-4605-845d-de05523aabab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352592929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2352592929
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1596235954
Short name T73
Test name
Test status
Simulation time 457689161 ps
CPU time 2.94 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 214952 kb
Host smart-dd843fca-b98e-4e90-bd1e-01bb3175c357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596235954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1596235954
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3827846711
Short name T48
Test name
Test status
Simulation time 35724613 ps
CPU time 2.29 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:30 PM PDT 24
Peak memory 216252 kb
Host smart-f91618b0-2cdb-452b-a387-b851efd208a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827846711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3827846711
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.215457939
Short name T61
Test name
Test status
Simulation time 848097604 ps
CPU time 19.33 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:55 PM PDT 24
Peak memory 214976 kb
Host smart-a834245b-c490-4234-abab-eb07e35f0495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215457939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.215457939
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1172051588
Short name T105
Test name
Test status
Simulation time 87997200 ps
CPU time 2.59 seconds
Started Aug 14 04:29:27 PM PDT 24
Finished Aug 14 04:29:35 PM PDT 24
Peak memory 217468 kb
Host smart-6eea876a-9d1f-4b0d-8ebc-1e7cc968a94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172051588 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1172051588
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3127331314
Short name T122
Test name
Test status
Simulation time 339657422 ps
CPU time 2.33 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 206828 kb
Host smart-63009a8e-a0ad-4a4c-840a-2ad145cde504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127331314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3127331314
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1171516642
Short name T98
Test name
Test status
Simulation time 14548315 ps
CPU time 0.74 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 203936 kb
Host smart-f57dc531-6606-4970-86fe-2765ef3abfe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171516642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1171516642
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3151903161
Short name T87
Test name
Test status
Simulation time 612738707 ps
CPU time 4.06 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 214936 kb
Host smart-f9b4bb38-5260-489d-8083-0e8ec6ed66ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151903161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3151903161
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.856563964
Short name T53
Test name
Test status
Simulation time 224268692 ps
CPU time 2.56 seconds
Started Aug 14 04:29:23 PM PDT 24
Finished Aug 14 04:29:26 PM PDT 24
Peak memory 216716 kb
Host smart-56f47793-1dd3-4084-b1fa-a79b480eb6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856563964 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.856563964
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2471376124
Short name T133
Test name
Test status
Simulation time 21045614 ps
CPU time 1.19 seconds
Started Aug 14 04:29:29 PM PDT 24
Finished Aug 14 04:29:30 PM PDT 24
Peak memory 215000 kb
Host smart-32a7d9e7-7bdc-4935-9a7f-96209c6fe136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471376124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2471376124
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3019838829
Short name T143
Test name
Test status
Simulation time 218423582 ps
CPU time 1.74 seconds
Started Aug 14 04:29:18 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 215004 kb
Host smart-5c183719-76b1-4b6c-9c8b-3ce24ee1a005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019838829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3019838829
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2267572685
Short name T171
Test name
Test status
Simulation time 166270738 ps
CPU time 3.37 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 215216 kb
Host smart-da34b0e0-3f25-4008-b232-dd1890906d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267572685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2267572685
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1796033991
Short name T163
Test name
Test status
Simulation time 577849611 ps
CPU time 3.39 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 217336 kb
Host smart-5365f6aa-b9d0-4a2f-9826-13d83443a13b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796033991 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1796033991
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3213285550
Short name T25
Test name
Test status
Simulation time 41090718 ps
CPU time 2.34 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 214952 kb
Host smart-e7933c74-0e06-4ae8-85dd-49d965186653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213285550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3213285550
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1123375724
Short name T75
Test name
Test status
Simulation time 31714837 ps
CPU time 0.73 seconds
Started Aug 14 04:29:17 PM PDT 24
Finished Aug 14 04:29:18 PM PDT 24
Peak memory 203912 kb
Host smart-b3dacb33-2572-4945-843c-f94bd29cdc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123375724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1123375724
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2877423417
Short name T52
Test name
Test status
Simulation time 59727265 ps
CPU time 1.51 seconds
Started Aug 14 04:29:24 PM PDT 24
Finished Aug 14 04:29:26 PM PDT 24
Peak memory 214992 kb
Host smart-3795f3ad-7b40-47a9-86f5-8ad1ff4369a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877423417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2877423417
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1807558785
Short name T44
Test name
Test status
Simulation time 206113162 ps
CPU time 1.5 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 215152 kb
Host smart-dd874b10-69ea-4651-b2db-237d6ddac611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807558785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1807558785
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4071837327
Short name T132
Test name
Test status
Simulation time 285860339 ps
CPU time 7.59 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:48 PM PDT 24
Peak memory 215020 kb
Host smart-65cc412c-031e-4a96-a8fd-17c77bea9707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071837327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4071837327
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2074739557
Short name T97
Test name
Test status
Simulation time 42855605 ps
CPU time 2.65 seconds
Started Aug 14 04:29:35 PM PDT 24
Finished Aug 14 04:29:38 PM PDT 24
Peak memory 217540 kb
Host smart-df44b226-3ca7-495a-ad1c-312e7b4852f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074739557 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2074739557
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1040209505
Short name T35
Test name
Test status
Simulation time 52540551 ps
CPU time 1.39 seconds
Started Aug 14 04:29:23 PM PDT 24
Finished Aug 14 04:29:24 PM PDT 24
Peak memory 206752 kb
Host smart-a3bd3f04-5bd3-4bf4-bb89-84273a0f426a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040209505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1040209505
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1046979836
Short name T12
Test name
Test status
Simulation time 13888019 ps
CPU time 0.74 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 203644 kb
Host smart-a74d71ef-ede0-49d9-b7ef-3432fe2824e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046979836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1046979836
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1105521661
Short name T39
Test name
Test status
Simulation time 762099610 ps
CPU time 3.63 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:40 PM PDT 24
Peak memory 214536 kb
Host smart-4db0fc18-355b-450a-a805-08177b2156af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105521661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1105521661
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.846874098
Short name T43
Test name
Test status
Simulation time 201609762 ps
CPU time 4.36 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 215212 kb
Host smart-9d64d8b2-d863-4d72-91b3-f9f85b12a108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846874098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.846874098
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3927422074
Short name T128
Test name
Test status
Simulation time 704165143 ps
CPU time 13.26 seconds
Started Aug 14 04:29:29 PM PDT 24
Finished Aug 14 04:29:42 PM PDT 24
Peak memory 215120 kb
Host smart-faa94708-d3c7-4d86-9966-be8c13721b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927422074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3927422074
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.146998832
Short name T93
Test name
Test status
Simulation time 187292197 ps
CPU time 1.72 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 215064 kb
Host smart-e2e49e1b-4ca3-4773-96d8-3617fc4cabd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146998832 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.146998832
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2489464609
Short name T117
Test name
Test status
Simulation time 70961160 ps
CPU time 2 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 214960 kb
Host smart-5722358f-c9fe-4b84-b0d1-3bc5143e3891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489464609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2489464609
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2124863489
Short name T158
Test name
Test status
Simulation time 11843359 ps
CPU time 0.72 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 203540 kb
Host smart-5f3d12b7-1612-4b0f-a45f-705c707cf0d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124863489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2124863489
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1406142207
Short name T151
Test name
Test status
Simulation time 58940916 ps
CPU time 1.66 seconds
Started Aug 14 04:29:41 PM PDT 24
Finished Aug 14 04:29:46 PM PDT 24
Peak memory 206804 kb
Host smart-6ac7b391-48bb-4755-932f-d7e3ed1835a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406142207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1406142207
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1962014187
Short name T162
Test name
Test status
Simulation time 87287111 ps
CPU time 2.11 seconds
Started Aug 14 04:29:24 PM PDT 24
Finished Aug 14 04:29:26 PM PDT 24
Peak memory 215248 kb
Host smart-e5661491-ccd3-4b12-8990-c2426345dfac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962014187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1962014187
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2811466309
Short name T60
Test name
Test status
Simulation time 2039871987 ps
CPU time 12.69 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 215632 kb
Host smart-3c49f8ed-8ed4-4f08-b4f3-660960b9b76e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811466309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2811466309
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.508075042
Short name T13
Test name
Test status
Simulation time 64108827 ps
CPU time 1.27 seconds
Started Aug 14 04:29:34 PM PDT 24
Finished Aug 14 04:29:35 PM PDT 24
Peak memory 206720 kb
Host smart-2d36de33-0477-4bbb-b14d-199920b9ead3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508075042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.508075042
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4099843311
Short name T126
Test name
Test status
Simulation time 14341310 ps
CPU time 0.7 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 203644 kb
Host smart-2e51d560-89fe-4801-839b-8ace34f2ac48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099843311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4099843311
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4178030198
Short name T14
Test name
Test status
Simulation time 45476905 ps
CPU time 2.76 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 215012 kb
Host smart-0979e6cf-3ee9-434a-a5e5-9899396673be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178030198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4178030198
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2666543562
Short name T57
Test name
Test status
Simulation time 149982773 ps
CPU time 2.05 seconds
Started Aug 14 04:29:13 PM PDT 24
Finished Aug 14 04:29:16 PM PDT 24
Peak memory 215196 kb
Host smart-ba95a20d-ac6a-41e5-b450-71808e152821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666543562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2666543562
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1883332457
Short name T102
Test name
Test status
Simulation time 803666937 ps
CPU time 15.85 seconds
Started Aug 14 04:29:27 PM PDT 24
Finished Aug 14 04:29:43 PM PDT 24
Peak memory 215064 kb
Host smart-bcfe8adc-88c1-45a5-afcb-896a27500673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883332457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1883332457
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1611293496
Short name T127
Test name
Test status
Simulation time 64240395 ps
CPU time 3.5 seconds
Started Aug 14 04:29:43 PM PDT 24
Finished Aug 14 04:29:47 PM PDT 24
Peak memory 217844 kb
Host smart-de9447b3-222c-46c0-bd38-ee53c8e5c50b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611293496 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1611293496
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1681349172
Short name T32
Test name
Test status
Simulation time 37336686 ps
CPU time 2.18 seconds
Started Aug 14 04:29:32 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 206988 kb
Host smart-e5a95e1f-52db-439f-b2fd-6ffb0c42bbb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681349172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1681349172
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1672406835
Short name T56
Test name
Test status
Simulation time 18725481 ps
CPU time 0.72 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 203628 kb
Host smart-c8f9c7fc-8e2b-456f-a387-aa65667f0d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672406835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1672406835
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3132449693
Short name T146
Test name
Test status
Simulation time 108062003 ps
CPU time 2.94 seconds
Started Aug 14 04:29:11 PM PDT 24
Finished Aug 14 04:29:14 PM PDT 24
Peak memory 215048 kb
Host smart-03649cda-77fd-4571-b1aa-9c574bfdc190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132449693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3132449693
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1823845453
Short name T8
Test name
Test status
Simulation time 85214388 ps
CPU time 2.46 seconds
Started Aug 14 04:29:32 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 215204 kb
Host smart-c611e8d9-45ee-473c-8093-985ee2dadf37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823845453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1823845453
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1965938069
Short name T64
Test name
Test status
Simulation time 558334634 ps
CPU time 13.37 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:50 PM PDT 24
Peak memory 215108 kb
Host smart-5df63547-bfd8-4753-a4fc-af907a8b548a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965938069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1965938069
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2981892208
Short name T154
Test name
Test status
Simulation time 49444559 ps
CPU time 3.23 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:22 PM PDT 24
Peak memory 217816 kb
Host smart-5ced9633-1bd8-4cc2-b440-e5053f9a2d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981892208 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2981892208
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3369808340
Short name T129
Test name
Test status
Simulation time 110378647 ps
CPU time 1.64 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 214976 kb
Host smart-09565d43-c6f1-46f1-b61c-27732b703e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369808340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3369808340
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3796741704
Short name T175
Test name
Test status
Simulation time 13870495 ps
CPU time 0.75 seconds
Started Aug 14 04:29:45 PM PDT 24
Finished Aug 14 04:29:46 PM PDT 24
Peak memory 203656 kb
Host smart-30e1f20f-d8dd-4bff-9590-f4a0574b07cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796741704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3796741704
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2985294545
Short name T173
Test name
Test status
Simulation time 101841518 ps
CPU time 2.69 seconds
Started Aug 14 04:29:34 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 215008 kb
Host smart-51f90065-0f25-4ccb-a28c-7ddc6fb2c18d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985294545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2985294545
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4000162943
Short name T104
Test name
Test status
Simulation time 2061370443 ps
CPU time 6.45 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:46 PM PDT 24
Peak memory 215316 kb
Host smart-1ca3c91e-a78b-4de9-b137-74c2d066a664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000162943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4000162943
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2850552326
Short name T58
Test name
Test status
Simulation time 4434557711 ps
CPU time 14.71 seconds
Started Aug 14 04:29:39 PM PDT 24
Finished Aug 14 04:29:54 PM PDT 24
Peak memory 215120 kb
Host smart-74865f61-686f-4c39-95a3-6781822c9641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850552326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2850552326
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.319800695
Short name T81
Test name
Test status
Simulation time 266429263 ps
CPU time 3.62 seconds
Started Aug 14 04:29:24 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 217828 kb
Host smart-c443175e-9b17-4a28-ab24-1f5acbecd366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319800695 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.319800695
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3114566943
Short name T30
Test name
Test status
Simulation time 194393090 ps
CPU time 2.21 seconds
Started Aug 14 04:29:34 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 214952 kb
Host smart-e0348dd0-6ff3-4313-ab2f-e17f1ed7ffa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114566943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3114566943
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1818773122
Short name T115
Test name
Test status
Simulation time 11726807 ps
CPU time 0.73 seconds
Started Aug 14 04:29:33 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 203636 kb
Host smart-6346b522-1840-4fb8-b802-f9f18498697d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818773122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1818773122
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.999471947
Short name T155
Test name
Test status
Simulation time 212295917 ps
CPU time 2.84 seconds
Started Aug 14 04:29:34 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 214992 kb
Host smart-739fb39f-b56c-4854-bdf7-7b0a150c3130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999471947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.999471947
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.854529346
Short name T134
Test name
Test status
Simulation time 118170427 ps
CPU time 1.87 seconds
Started Aug 14 04:29:15 PM PDT 24
Finished Aug 14 04:29:16 PM PDT 24
Peak memory 215352 kb
Host smart-ab47ed09-d3ab-4ecc-955b-bb09f1391da3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854529346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.854529346
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.79400607
Short name T63
Test name
Test status
Simulation time 408719237 ps
CPU time 6.61 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 215160 kb
Host smart-c0cb7d2b-26d0-40d1-954d-08dd83e294fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79400607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_
tl_intg_err.79400607
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2376628812
Short name T124
Test name
Test status
Simulation time 309136503 ps
CPU time 21.09 seconds
Started Aug 14 04:29:06 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 206968 kb
Host smart-d99ed04c-655b-4a1f-8a13-14254f049281
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376628812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2376628812
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3867407223
Short name T90
Test name
Test status
Simulation time 739477560 ps
CPU time 12.11 seconds
Started Aug 14 04:29:11 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 207036 kb
Host smart-3e346b07-19f2-4077-9580-e3d6aaae73d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867407223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3867407223
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.580708291
Short name T42
Test name
Test status
Simulation time 41474139 ps
CPU time 1.36 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:04 PM PDT 24
Peak memory 206848 kb
Host smart-4f17c115-faa6-4c04-9766-cc5462cfd335
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580708291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.580708291
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3564880093
Short name T18
Test name
Test status
Simulation time 66938249 ps
CPU time 2.43 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 217576 kb
Host smart-cfe4fe0b-9019-45e8-9246-3c40ffc179ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564880093 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3564880093
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3622258607
Short name T24
Test name
Test status
Simulation time 65394217 ps
CPU time 1.75 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:21 PM PDT 24
Peak memory 214980 kb
Host smart-dedb39a6-013a-4a76-8ef4-ee4e143d279a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622258607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
622258607
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1646232716
Short name T170
Test name
Test status
Simulation time 29499567 ps
CPU time 0.76 seconds
Started Aug 14 04:29:23 PM PDT 24
Finished Aug 14 04:29:24 PM PDT 24
Peak memory 203604 kb
Host smart-86838e55-ffe5-4dd6-a055-2d3bd1b5746c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646232716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
646232716
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2963014332
Short name T36
Test name
Test status
Simulation time 17131524 ps
CPU time 1.29 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 214964 kb
Host smart-f4c4ffdb-5edd-4e7c-be4b-c2ff85545d7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963014332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2963014332
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2041757527
Short name T72
Test name
Test status
Simulation time 11520759 ps
CPU time 0.7 seconds
Started Aug 14 04:29:11 PM PDT 24
Finished Aug 14 04:29:12 PM PDT 24
Peak memory 203464 kb
Host smart-a779df7e-34c9-4ae0-ade5-25b469722433
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041757527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2041757527
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4138493972
Short name T22
Test name
Test status
Simulation time 265830546 ps
CPU time 2.19 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:05 PM PDT 24
Peak memory 215276 kb
Host smart-29f357df-ce05-4c7f-af5a-3630b2a72590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138493972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
138493972
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3693644544
Short name T55
Test name
Test status
Simulation time 677019204 ps
CPU time 14.26 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:46 PM PDT 24
Peak memory 215600 kb
Host smart-3d5b01d3-7d6c-4523-85ea-12215c17eb66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693644544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3693644544
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2762259442
Short name T89
Test name
Test status
Simulation time 225968339 ps
CPU time 0.72 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 203644 kb
Host smart-f069cd41-0278-40fc-afc2-93e40e9330b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762259442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2762259442
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3822961926
Short name T69
Test name
Test status
Simulation time 14037747 ps
CPU time 0.7 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 203956 kb
Host smart-61b14055-3041-43e5-84bb-d3c6e7946a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822961926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3822961926
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4283232846
Short name T139
Test name
Test status
Simulation time 16197343 ps
CPU time 0.73 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:26 PM PDT 24
Peak memory 203580 kb
Host smart-20ac919f-d4c7-4904-baa7-6d781064debc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283232846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4283232846
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3579534597
Short name T76
Test name
Test status
Simulation time 44596955 ps
CPU time 0.71 seconds
Started Aug 14 04:29:44 PM PDT 24
Finished Aug 14 04:29:45 PM PDT 24
Peak memory 203676 kb
Host smart-d1929755-06f5-488b-853a-7aa6512e5ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579534597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3579534597
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4074583760
Short name T140
Test name
Test status
Simulation time 17273500 ps
CPU time 0.72 seconds
Started Aug 14 04:29:27 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 203656 kb
Host smart-437a493d-585e-4ae0-88eb-9d4a04d80131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074583760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4074583760
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3917665631
Short name T156
Test name
Test status
Simulation time 40752747 ps
CPU time 0.79 seconds
Started Aug 14 04:29:33 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 203648 kb
Host smart-f4f8b405-9f27-4160-8df8-166b54e56960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917665631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3917665631
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4293557216
Short name T94
Test name
Test status
Simulation time 14581546 ps
CPU time 0.76 seconds
Started Aug 14 04:30:05 PM PDT 24
Finished Aug 14 04:30:06 PM PDT 24
Peak memory 203604 kb
Host smart-e8d7d061-5396-473f-b6b9-9cd40d7636a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293557216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4293557216
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1663559967
Short name T148
Test name
Test status
Simulation time 15381633 ps
CPU time 0.68 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:41 PM PDT 24
Peak memory 203616 kb
Host smart-f50239e9-af89-4c7d-ac20-7ab59952a948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663559967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1663559967
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1447385413
Short name T142
Test name
Test status
Simulation time 39708055 ps
CPU time 0.71 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:22 PM PDT 24
Peak memory 203636 kb
Host smart-88f6219c-1b76-4b68-ac69-9fe449448bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447385413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1447385413
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2446126316
Short name T125
Test name
Test status
Simulation time 825868032 ps
CPU time 13.91 seconds
Started Aug 14 04:29:06 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 215068 kb
Host smart-eb29e1f9-03c7-4534-8e5d-8748b8dcea2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446126316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2446126316
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2794362260
Short name T51
Test name
Test status
Simulation time 7564433423 ps
CPU time 13.06 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:44 PM PDT 24
Peak memory 215028 kb
Host smart-061dbf84-2828-4d7d-bc7b-3b173c6f392e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794362260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2794362260
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3698493146
Short name T40
Test name
Test status
Simulation time 41703265 ps
CPU time 0.93 seconds
Started Aug 14 04:29:16 PM PDT 24
Finished Aug 14 04:29:17 PM PDT 24
Peak memory 206580 kb
Host smart-bd0db710-accb-4954-8ba9-e7be73266413
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698493146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3698493146
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3211993253
Short name T103
Test name
Test status
Simulation time 210825731 ps
CPU time 1.63 seconds
Started Aug 14 04:29:06 PM PDT 24
Finished Aug 14 04:29:08 PM PDT 24
Peak memory 215168 kb
Host smart-a059e5f6-e4c7-41cf-910d-7db51abdb8af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211993253 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3211993253
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.327908166
Short name T109
Test name
Test status
Simulation time 34925671 ps
CPU time 2.2 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:33 PM PDT 24
Peak memory 206764 kb
Host smart-e784414a-432c-4769-bbee-e1804ecbeb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327908166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.327908166
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.372782224
Short name T95
Test name
Test status
Simulation time 12558613 ps
CPU time 0.67 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 203660 kb
Host smart-f2a05a39-451b-43c2-a53c-85874582457d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372782224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.372782224
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1880813053
Short name T152
Test name
Test status
Simulation time 29106658 ps
CPU time 1.98 seconds
Started Aug 14 04:29:05 PM PDT 24
Finished Aug 14 04:29:07 PM PDT 24
Peak memory 214940 kb
Host smart-404061ba-3340-4ec9-866b-0905b0c2b9b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880813053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1880813053
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1944341079
Short name T92
Test name
Test status
Simulation time 55056143 ps
CPU time 0.67 seconds
Started Aug 14 04:29:22 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 203492 kb
Host smart-7e7dfae3-8832-42ff-bcfe-968a93550823
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944341079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1944341079
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1489620901
Short name T168
Test name
Test status
Simulation time 371932186 ps
CPU time 2.92 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 215068 kb
Host smart-073b49e2-f08b-4b84-b0f2-315b7e7633d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489620901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1489620901
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1683011829
Short name T20
Test name
Test status
Simulation time 82365832 ps
CPU time 4.93 seconds
Started Aug 14 04:29:17 PM PDT 24
Finished Aug 14 04:29:22 PM PDT 24
Peak memory 215252 kb
Host smart-8623cdd8-42f9-4e0c-9021-64e8ec549d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683011829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
683011829
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2112862237
Short name T59
Test name
Test status
Simulation time 203554335 ps
CPU time 11.65 seconds
Started Aug 14 04:29:17 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 214992 kb
Host smart-1b5fe53b-60ed-41f4-a536-733a3fe39267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112862237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2112862237
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1788507314
Short name T106
Test name
Test status
Simulation time 15241177 ps
CPU time 0.76 seconds
Started Aug 14 04:29:24 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 203648 kb
Host smart-5da20709-89b2-4586-9cf1-172837dad0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788507314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1788507314
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2418076379
Short name T100
Test name
Test status
Simulation time 13561716 ps
CPU time 0.69 seconds
Started Aug 14 04:29:37 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 203916 kb
Host smart-170aab2f-008c-4352-a9bf-6695575efd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418076379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2418076379
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4160435084
Short name T88
Test name
Test status
Simulation time 20276145 ps
CPU time 0.69 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 203540 kb
Host smart-c640a7df-0f67-48dc-8ae1-c37d778ba824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160435084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4160435084
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2436268693
Short name T3
Test name
Test status
Simulation time 19654151 ps
CPU time 0.67 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 204024 kb
Host smart-5e4b7372-794d-4531-9435-da1bc43e4d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436268693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2436268693
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1551222806
Short name T147
Test name
Test status
Simulation time 34139894 ps
CPU time 0.75 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 203644 kb
Host smart-c5899c2d-ffb2-46c4-a2ec-577e56e9fc68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551222806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1551222806
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3796927298
Short name T153
Test name
Test status
Simulation time 13995044 ps
CPU time 0.74 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 203644 kb
Host smart-b9ba4121-e2b1-431e-88cc-acdae506f02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796927298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3796927298
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1971702512
Short name T74
Test name
Test status
Simulation time 30639457 ps
CPU time 0.77 seconds
Started Aug 14 04:29:27 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 203996 kb
Host smart-597452cb-0777-4560-92d3-7c7b6b3b46c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971702512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1971702512
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2887042712
Short name T83
Test name
Test status
Simulation time 13268535 ps
CPU time 0.72 seconds
Started Aug 14 04:29:41 PM PDT 24
Finished Aug 14 04:29:42 PM PDT 24
Peak memory 203636 kb
Host smart-a0778a2c-51c7-4e1c-9c96-3cadca4a7a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887042712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2887042712
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3361492875
Short name T119
Test name
Test status
Simulation time 90195683 ps
CPU time 0.66 seconds
Started Aug 14 04:29:41 PM PDT 24
Finished Aug 14 04:29:42 PM PDT 24
Peak memory 203988 kb
Host smart-e205416c-65b4-4554-9c54-329f8d9a0108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361492875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3361492875
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.642297881
Short name T6
Test name
Test status
Simulation time 41586885 ps
CPU time 0.77 seconds
Started Aug 14 04:29:33 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 203644 kb
Host smart-26ba4a73-a1b6-4ca8-a449-ff1dcc1f0da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642297881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.642297881
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3336872836
Short name T174
Test name
Test status
Simulation time 1307601332 ps
CPU time 19.22 seconds
Started Aug 14 04:29:18 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 214976 kb
Host smart-501e48b9-bc2e-492c-97af-fcd1eb23bce7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336872836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3336872836
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2880480240
Short name T27
Test name
Test status
Simulation time 1350911414 ps
CPU time 19.38 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:38 PM PDT 24
Peak memory 206784 kb
Host smart-b6c21c57-33f4-4d9b-b0a2-023610489a25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880480240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2880480240
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1614947936
Short name T160
Test name
Test status
Simulation time 52846228 ps
CPU time 3.48 seconds
Started Aug 14 04:29:17 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 217640 kb
Host smart-9732c096-e0fc-46b0-993c-b5aef474f0c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614947936 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1614947936
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3437965764
Short name T172
Test name
Test status
Simulation time 85290478 ps
CPU time 1.75 seconds
Started Aug 14 04:29:13 PM PDT 24
Finished Aug 14 04:29:15 PM PDT 24
Peak memory 219188 kb
Host smart-8875c6a3-e27d-4c2b-bb7c-c3a36f5005c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437965764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
437965764
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.53282295
Short name T167
Test name
Test status
Simulation time 25494967 ps
CPU time 0.76 seconds
Started Aug 14 04:29:07 PM PDT 24
Finished Aug 14 04:29:08 PM PDT 24
Peak memory 203948 kb
Host smart-c9c52a78-902e-4348-9573-20746a8de60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53282295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.53282295
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3301369972
Short name T17
Test name
Test status
Simulation time 161472570 ps
CPU time 1.65 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 215040 kb
Host smart-abf609d6-e702-4cc4-8fe2-7e3be8fad65d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301369972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3301369972
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.492756091
Short name T71
Test name
Test status
Simulation time 33376253 ps
CPU time 0.68 seconds
Started Aug 14 04:29:06 PM PDT 24
Finished Aug 14 04:29:07 PM PDT 24
Peak memory 203476 kb
Host smart-01b6a74f-6726-4bd0-a62c-d524ee505c02
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492756091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.492756091
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2984257612
Short name T145
Test name
Test status
Simulation time 228155391 ps
CPU time 1.74 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 214984 kb
Host smart-765e5b28-3adc-479e-acae-01c4ed49a247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984257612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2984257612
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1687661089
Short name T164
Test name
Test status
Simulation time 68645015 ps
CPU time 2.13 seconds
Started Aug 14 04:29:17 PM PDT 24
Finished Aug 14 04:29:19 PM PDT 24
Peak memory 215264 kb
Host smart-e6d0e951-7777-46ca-8002-1421f4264066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687661089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
687661089
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3719929212
Short name T120
Test name
Test status
Simulation time 766055357 ps
CPU time 8.81 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:21 PM PDT 24
Peak memory 215624 kb
Host smart-6a232fdf-f28c-499d-b1fa-90449db20fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719929212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3719929212
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3582342640
Short name T111
Test name
Test status
Simulation time 13592179 ps
CPU time 0.7 seconds
Started Aug 14 04:29:29 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 203988 kb
Host smart-81385564-5e4f-4307-b06c-8ff8e0d265d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582342640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3582342640
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1573951028
Short name T131
Test name
Test status
Simulation time 14783273 ps
CPU time 0.71 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 203500 kb
Host smart-e31a4100-7b74-4d93-b49f-e4f15b18bfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573951028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1573951028
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3037984323
Short name T68
Test name
Test status
Simulation time 21157639 ps
CPU time 0.68 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:25 PM PDT 24
Peak memory 203584 kb
Host smart-36d62869-7329-4db5-aa71-f6c725d4f422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037984323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3037984323
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4032730601
Short name T121
Test name
Test status
Simulation time 12920456 ps
CPU time 0.69 seconds
Started Aug 14 04:29:51 PM PDT 24
Finished Aug 14 04:29:52 PM PDT 24
Peak memory 203612 kb
Host smart-6133cb5a-b2a6-4c32-a097-53cd0605d3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032730601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4032730601
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3838002483
Short name T80
Test name
Test status
Simulation time 13145387 ps
CPU time 0.74 seconds
Started Aug 14 04:29:38 PM PDT 24
Finished Aug 14 04:29:38 PM PDT 24
Peak memory 203500 kb
Host smart-7b489e0e-9413-4cf5-80c4-94c07d3249e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838002483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3838002483
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3978587786
Short name T107
Test name
Test status
Simulation time 38899275 ps
CPU time 0.71 seconds
Started Aug 14 04:29:57 PM PDT 24
Finished Aug 14 04:29:58 PM PDT 24
Peak memory 203600 kb
Host smart-fce26c4f-7137-4fbb-97ca-75f79ed93953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978587786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3978587786
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3959741834
Short name T66
Test name
Test status
Simulation time 23928622 ps
CPU time 0.76 seconds
Started Aug 14 04:29:44 PM PDT 24
Finished Aug 14 04:29:45 PM PDT 24
Peak memory 203668 kb
Host smart-f0a2a267-f58a-4515-8dc1-0e1c57c719b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959741834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3959741834
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2351654894
Short name T86
Test name
Test status
Simulation time 13463560 ps
CPU time 0.72 seconds
Started Aug 14 04:29:29 PM PDT 24
Finished Aug 14 04:29:30 PM PDT 24
Peak memory 203680 kb
Host smart-b67b4dc2-bbca-4b88-b731-75f6739a70f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351654894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2351654894
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1362578928
Short name T165
Test name
Test status
Simulation time 50229244 ps
CPU time 0.73 seconds
Started Aug 14 04:29:49 PM PDT 24
Finished Aug 14 04:29:50 PM PDT 24
Peak memory 203640 kb
Host smart-27035dbe-3a65-4502-89e1-ae430a308d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362578928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1362578928
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2297357449
Short name T114
Test name
Test status
Simulation time 22058191 ps
CPU time 0.71 seconds
Started Aug 14 04:29:32 PM PDT 24
Finished Aug 14 04:29:33 PM PDT 24
Peak memory 203912 kb
Host smart-bc72c8c6-de1b-4784-befa-e625c95c732c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297357449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2297357449
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3337748343
Short name T135
Test name
Test status
Simulation time 44197392 ps
CPU time 1.6 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:26 PM PDT 24
Peak memory 215232 kb
Host smart-0318f916-51af-45a1-8a58-5ce9b2920d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337748343 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3337748343
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2137936440
Short name T130
Test name
Test status
Simulation time 175126131 ps
CPU time 1.8 seconds
Started Aug 14 04:29:14 PM PDT 24
Finished Aug 14 04:29:16 PM PDT 24
Peak memory 215000 kb
Host smart-ed0557d6-ca06-42ee-9887-c31e19e2f7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137936440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
137936440
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3527302605
Short name T91
Test name
Test status
Simulation time 54428446 ps
CPU time 0.75 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:40 PM PDT 24
Peak memory 203644 kb
Host smart-57dfcc31-c347-4510-aea8-8ef2946becca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527302605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
527302605
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2738279531
Short name T113
Test name
Test status
Simulation time 83780001 ps
CPU time 1.54 seconds
Started Aug 14 04:29:18 PM PDT 24
Finished Aug 14 04:29:19 PM PDT 24
Peak memory 215640 kb
Host smart-7f3f5a64-5e9c-43fc-9363-7a9816112c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738279531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2738279531
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1444710157
Short name T19
Test name
Test status
Simulation time 79503635 ps
CPU time 2.05 seconds
Started Aug 14 04:29:06 PM PDT 24
Finished Aug 14 04:29:09 PM PDT 24
Peak memory 215164 kb
Host smart-59816610-fdef-47e8-a752-75257daa15b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444710157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
444710157
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1763754176
Short name T9
Test name
Test status
Simulation time 107065587 ps
CPU time 6.67 seconds
Started Aug 14 04:29:03 PM PDT 24
Finished Aug 14 04:29:10 PM PDT 24
Peak memory 214984 kb
Host smart-ccf8e0b1-e0cd-4225-bbb1-ec42edc94787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763754176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1763754176
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2985989879
Short name T45
Test name
Test status
Simulation time 307834374 ps
CPU time 1.62 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 215032 kb
Host smart-b3912f9b-5f8d-49fc-8918-5e912617a7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985989879 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2985989879
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3336219748
Short name T149
Test name
Test status
Simulation time 81887456 ps
CPU time 1.33 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:42 PM PDT 24
Peak memory 206604 kb
Host smart-b383d824-9922-4afb-a027-ef2629f49532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336219748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
336219748
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2754466284
Short name T84
Test name
Test status
Simulation time 21600340 ps
CPU time 0.75 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:21 PM PDT 24
Peak memory 203616 kb
Host smart-0aabbe27-73a2-45e6-ab70-ab9e6ec70e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754466284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
754466284
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3636691890
Short name T4
Test name
Test status
Simulation time 417528120 ps
CPU time 4.08 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 215004 kb
Host smart-298856ab-686f-476f-bd23-9f5f9e05d798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636691890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3636691890
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3035632461
Short name T49
Test name
Test status
Simulation time 97153270 ps
CPU time 1.74 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 215104 kb
Host smart-43a7fb63-7eda-454e-8a2b-45c109269349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035632461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
035632461
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.13702316
Short name T50
Test name
Test status
Simulation time 238698966 ps
CPU time 3.51 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:24 PM PDT 24
Peak memory 217796 kb
Host smart-f898b7d2-83a4-4968-a4cb-47c993c36649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702316 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.13702316
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1083699361
Short name T161
Test name
Test status
Simulation time 62409407 ps
CPU time 1.8 seconds
Started Aug 14 04:29:28 PM PDT 24
Finished Aug 14 04:29:30 PM PDT 24
Peak memory 215020 kb
Host smart-2f5cde13-1a77-4d14-9592-4811d0e570ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083699361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
083699361
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.930475271
Short name T79
Test name
Test status
Simulation time 13801785 ps
CPU time 0.74 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:13 PM PDT 24
Peak memory 203184 kb
Host smart-6920b23d-5b22-42b9-8924-e596e8a0bd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930475271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.930475271
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1033464138
Short name T169
Test name
Test status
Simulation time 227087636 ps
CPU time 1.77 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:43 PM PDT 24
Peak memory 214608 kb
Host smart-8442dcde-2fd0-4ee9-89d9-72f8df819933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033464138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1033464138
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.988698007
Short name T23
Test name
Test status
Simulation time 460954888 ps
CPU time 2.94 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:28 PM PDT 24
Peak memory 215364 kb
Host smart-ac25c88f-e29c-481d-90de-eb1fd99b4b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988698007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.988698007
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3775218957
Short name T138
Test name
Test status
Simulation time 1169976633 ps
CPU time 19.62 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:40 PM PDT 24
Peak memory 215712 kb
Host smart-6702958a-5f90-40ea-be92-f4e1a79a6a46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775218957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3775218957
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2006514693
Short name T159
Test name
Test status
Simulation time 171611940 ps
CPU time 2.58 seconds
Started Aug 14 04:29:51 PM PDT 24
Finished Aug 14 04:29:54 PM PDT 24
Peak memory 216124 kb
Host smart-799f5977-f216-40be-b0f7-a1a7f539cfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006514693 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2006514693
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1806120814
Short name T29
Test name
Test status
Simulation time 85665959 ps
CPU time 2.05 seconds
Started Aug 14 04:29:12 PM PDT 24
Finished Aug 14 04:29:14 PM PDT 24
Peak memory 214936 kb
Host smart-dc82a1aa-ab18-45e6-b986-9319f48054e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806120814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
806120814
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4040295681
Short name T77
Test name
Test status
Simulation time 29779456 ps
CPU time 0.75 seconds
Started Aug 14 04:29:35 PM PDT 24
Finished Aug 14 04:29:36 PM PDT 24
Peak memory 203652 kb
Host smart-60d3fe64-0a4f-44d7-9871-d5bef0559e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040295681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
040295681
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.952858177
Short name T38
Test name
Test status
Simulation time 168988861 ps
CPU time 2.96 seconds
Started Aug 14 04:29:37 PM PDT 24
Finished Aug 14 04:29:40 PM PDT 24
Peak memory 214948 kb
Host smart-ea76c222-3d8b-40ec-8237-219e40aaafc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952858177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.952858177
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2295242171
Short name T118
Test name
Test status
Simulation time 184001536 ps
CPU time 2.69 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 215180 kb
Host smart-d7dbbb5e-7268-4c18-8414-e157c559797b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295242171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
295242171
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3175940955
Short name T101
Test name
Test status
Simulation time 327792163 ps
CPU time 7.23 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 215332 kb
Host smart-3c63832a-c0c9-4c9b-9906-b3baf8312685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175940955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3175940955
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1155931395
Short name T85
Test name
Test status
Simulation time 53772363 ps
CPU time 3.32 seconds
Started Aug 14 04:29:29 PM PDT 24
Finished Aug 14 04:29:33 PM PDT 24
Peak memory 216920 kb
Host smart-24eb2940-e77e-4ced-82b1-5b186858d3b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155931395 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1155931395
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.406348379
Short name T34
Test name
Test status
Simulation time 190290741 ps
CPU time 1.13 seconds
Started Aug 14 04:29:19 PM PDT 24
Finished Aug 14 04:29:20 PM PDT 24
Peak memory 206756 kb
Host smart-1492f1de-4321-44cc-a8db-4fb0cd3f5614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406348379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.406348379
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1294328936
Short name T136
Test name
Test status
Simulation time 38942201 ps
CPU time 0.73 seconds
Started Aug 14 04:29:47 PM PDT 24
Finished Aug 14 04:29:48 PM PDT 24
Peak memory 203624 kb
Host smart-55fe8d4c-14db-4747-a167-14084f25417f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294328936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
294328936
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3166966595
Short name T123
Test name
Test status
Simulation time 28593760 ps
CPU time 1.67 seconds
Started Aug 14 04:29:25 PM PDT 24
Finished Aug 14 04:29:27 PM PDT 24
Peak memory 214980 kb
Host smart-301e2a4e-3b79-43a8-b9f2-22dcb0c818d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166966595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3166966595
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.411623223
Short name T47
Test name
Test status
Simulation time 61153435 ps
CPU time 1.7 seconds
Started Aug 14 04:29:21 PM PDT 24
Finished Aug 14 04:29:23 PM PDT 24
Peak memory 215420 kb
Host smart-7e4e4332-c681-4487-9f32-69dd7a96adf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411623223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.411623223
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1160443141
Short name T54
Test name
Test status
Simulation time 3759605357 ps
CPU time 18.43 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:44 PM PDT 24
Peak memory 215028 kb
Host smart-80aef10f-3d05-446f-8de2-50fa9e124611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160443141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1160443141
Directory /workspace/9.spi_device_tl_intg_err/latest
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