Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
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Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 5 0 0.00
Crosses 6 6 0 0.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 3 0 0.00 100 1 1 0
cp_tpm_enabled 2 2 0 0.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 6 0 0.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 3 0 0.00


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1
auto[FlashMode] 0 1 1
auto[PassthroughMode] 0 1 1



Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_tpm_enabled

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 6 0 0.00 6


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
* * -- -- 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%