Group : spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 10 0 0.00
Crosses 4 4 0 0.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mailbox_en 2 2 0 0.00 100 1 1 2
cp_rx_order 2 2 0 0.00 100 1 1 2
cp_tx_order 2 2 0 0.00 100 1 1 2
rx_order 2 2 0 0.00 100 1 1 2
tx_order 2 2 0 0.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_order 4 4 0 0.00 100 1 1 0


Summary for Variable cp_mailbox_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_mailbox_en

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_tx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for tx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cr_order

Samples crossed: tx_order rx_order
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cr_order

Uncovered bins
tx_orderrx_orderCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%