Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	38	0	0.00
Crosses	84	84	0	0.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	4	0	0.00	100	1	1	0
cp_addr_swap_en	2	2	0	0.00	100	1	1	2
cp_busy	2	2	0	0.00	100	1	1	2
cp_dummy_cycles	9	9	0	0.00	100	1	1	0
cp_is_flash	2	2	0	0.00	100	1	1	2
cp_is_write	2	2	0	0.00	100	1	1	0
cp_num_lanes	2	2	0	0.00	100	1	1	0
cp_opcode	11	11	0	0.00	100	1	1	0
cp_payload_swap_en	2	2	0	0.00	100	1	1	2
cp_upload	2	2	0	0.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	48	0	0.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	36	0	0.00	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	4	0	0.00

Automatically Generated Bins for cp_addr_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[SpiFlashAddrDisabled]	0	1	1
auto[SpiFlashAddrCfg]	0	1	1
auto[SpiFlashAddr3b]	0	1	1
auto[SpiFlashAddr4b]	0	1	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_addr_swap_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_busy

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	9	0	0.00

User Defined Bins for cp_dummy_cycles

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1
values[1]	0	1	1
values[2]	0	1	1
values[3]	0	1	1
values[4]	0	1	1
values[5]	0	1	1
values[6]	0	1	1
values[7]	0	1	1
values[8]	0	1	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_flash

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	2	0	0.00

User Defined Bins for cp_is_write

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read	0	1	1
write	0	1	1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	2	0	0.00

User Defined Bins for cp_num_lanes

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valids[0x0]	0	1	1
valids[0x1]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	11	0	0.00

User Defined Bins for cp_opcode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
internal_process_ops[0x9f]	0	1	1
internal_process_ops[0x5a]	0	1	1
internal_process_ops[0x05]	0	1	1
internal_process_ops[0x35]	0	1	1
internal_process_ops[0x15]	0	1	1
internal_process_ops[0x03]	0	1	1
internal_process_ops[0x0b]	0	1	1
internal_process_ops[0x3b]	0	1	1
internal_process_ops[0x6b]	0	1	1
internal_process_ops[0xbb]	0	1	1
internal_process_ops[0xeb]	0	1	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_payload_swap_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	48	0	0.00	48
Automatically Generated Cross Bins	48	48	0	0.00	48
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
*	[read]	*	*	[auto[0]]	--	--	16
*	[write]	*	*	*	--	--	32

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	36	0	0.00	36

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	*	*	--	--	36