Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	16	0	0.00
Crosses	72	72	0	0.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	2	0	0.00	100	1	1	2
cp_is_host_read	2	2	0	0.00	100	1	1	2
cp_other_status	8	8	0	0.00	100	1	1	8
cp_sw_read_while_csb_active	2	2	0	0.00	100	1	1	2
cp_wel_bit	2	2	0	0.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	64	0	0.00	100	1	1	0
cr_busyXwelXcsb	8	8	0	0.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_busy_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_host_read

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	8	0	0.00

Automatically Generated Bins for cp_other_status

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:524287] - auto[3670016:4194303]]	--	--	8

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_wel_bit

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for cr_all_except_csb

Uncovered bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	NUMBER	STATUS
*	*	*	*	--	--	64

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	8	0	0.00	8

Automatically Generated Cross Bins for cr_busyXwelXcsb

Uncovered bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	NUMBER	STATUS
*	*	*	--	--	8