Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	455	1			T3	5		T6	8		T11	11
all_pins[1]	455	1			T3	5		T6	8		T11	11
all_pins[2]	455	1			T3	5		T6	8		T11	11
all_pins[3]	455	1			T3	5		T6	8		T11	11
all_pins[4]	455	1			T3	5		T6	8		T11	11
all_pins[5]	455	1			T3	5		T6	8		T11	11
all_pins[6]	455	1			T3	5		T6	8		T11	11
all_pins[7]	455	1			T3	5		T6	8		T11	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2921	1			T3	28		T6	51		T11	64
values[0x1]	719	1			T3	12		T6	13		T11	24
transitions[0x0=>0x1]	527	1			T3	5		T6	10		T11	15
transitions[0x1=>0x0]	538	1			T3	6		T6	10		T11	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	378	1			T3	4		T6	6		T11	6
all_pins[0]	values[0x1]	77	1			T3	1		T6	2		T11	5
all_pins[0]	transitions[0x0=>0x1]	55	1			T3	1		T6	2		T11	2
all_pins[0]	transitions[0x1=>0x0]	77	1			T6	3		T11	2		T12	3
all_pins[1]	values[0x0]	356	1			T3	5		T6	5		T11	6
all_pins[1]	values[0x1]	99	1			T6	3		T11	5		T12	3
all_pins[1]	transitions[0x0=>0x1]	71	1			T6	2		T11	3		T12	2
all_pins[1]	transitions[0x1=>0x0]	61	1			T11	2		T56	3		T67	2
all_pins[2]	values[0x0]	366	1			T3	5		T6	7		T11	7
all_pins[2]	values[0x1]	89	1			T6	1		T11	4		T12	1
all_pins[2]	transitions[0x0=>0x1]	63	1			T6	1		T11	1		T12	1
all_pins[2]	transitions[0x1=>0x0]	63	1			T3	1		T6	2		T56	2
all_pins[3]	values[0x0]	366	1			T3	4		T6	6		T11	8
all_pins[3]	values[0x1]	89	1			T3	1		T6	2		T11	3
all_pins[3]	transitions[0x0=>0x1]	64	1			T3	1		T6	1		T11	3
all_pins[3]	transitions[0x1=>0x0]	80	1			T3	2		T6	1		T11	2
all_pins[4]	values[0x0]	350	1			T3	3		T6	6		T11	9
all_pins[4]	values[0x1]	105	1			T3	2		T6	2		T11	2
all_pins[4]	transitions[0x0=>0x1]	81	1			T3	1		T6	1		T11	2
all_pins[4]	transitions[0x1=>0x0]	55	1			T3	1		T11	2		T12	1
all_pins[5]	values[0x0]	376	1			T3	3		T6	7		T11	9
all_pins[5]	values[0x1]	79	1			T3	2		T6	1		T11	2
all_pins[5]	transitions[0x0=>0x1]	56	1			T6	1		T11	2		T12	1
all_pins[5]	transitions[0x1=>0x0]	71	1			T3	1		T6	1		T11	1
all_pins[6]	values[0x0]	361	1			T3	2		T6	7		T11	10
all_pins[6]	values[0x1]	94	1			T3	3		T6	1		T11	1
all_pins[6]	transitions[0x0=>0x1]	73	1			T3	1		T6	1		T11	1
all_pins[6]	transitions[0x1=>0x0]	66	1			T3	1		T6	1		T11	2
all_pins[7]	values[0x0]	368	1			T3	2		T6	7		T11	9
all_pins[7]	values[0x1]	87	1			T3	3		T6	1		T11	2
all_pins[7]	transitions[0x0=>0x1]	64	1			T3	1		T6	1		T11	1
all_pins[7]	transitions[0x1=>0x0]	65	1			T6	2		T11	4		T12	2