Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	18	0	0.00
Crosses	512	512	0	0.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_hw_reg_dis	2	2	0	0.00	100	1	1	2
cp_invalid_locality	2	2	0	0.00	100	1	1	2
cp_is_hw_reg_offset	2	2	0	0.00	100	1	1	2
cp_is_in_tpm_region	2	2	0	0.00	100	1	1	2
cp_is_valid_locality	2	2	0	0.00	100	1	1	2
cp_is_word_aligned	2	2	0	0.00	100	1	1	2
cp_is_write	2	2	0	0.00	100	1	1	2
cp_tpm_mode	2	2	0	0.00	100	1	1	0
cp_tpm_reg_chk_dis	2	2	0	0.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	512	512	0	0.00	100	1	1	0

Summary for Variable cp_hw_reg_dis

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_hw_reg_dis

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_invalid_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_invalid_locality

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_hw_reg_offset

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_hw_reg_offset

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_in_tpm_region

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_in_tpm_region

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_valid_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_valid_locality

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_word_aligned

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_word_aligned

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_write

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_tpm_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_tpm_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[TpmFifoMode]	0	1	1
auto[TpmCrbMode]	0	1	1

---

Summary for Variable cp_tpm_reg_chk_dis

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_tpm_reg_chk_dis

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cr_all

Samples crossed: cp_tpm_mode cp_hw_reg_dis cp_tpm_reg_chk_dis cp_invalid_locality cp_is_write cp_is_in_tpm_region cp_is_valid_locality cp_is_hw_reg_offset cp_is_word_aligned

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	512	512	0	0.00	512

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tpm_mode

cp_hw_reg_dis

cp_tpm_reg_chk_dis

cp_invalid_locality

cp_is_write

cp_is_in_tpm_region

cp_is_valid_locality

cp_is_hw_reg_offset

cp_is_word_aligned

COUNT

AT LEAST

NUMBER

STATUS

*

*

*

*

*

*

*

*

*

--

--

512