Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	386	1			T3	4		T6	7		T11	10
all_values[1]	386	1			T3	4		T6	7		T11	10
all_values[2]	386	1			T3	4		T6	7		T11	10
all_values[3]	386	1			T3	4		T6	7		T11	10
all_values[4]	386	1			T3	4		T6	7		T11	10
all_values[5]	386	1			T3	4		T6	7		T11	10
all_values[6]	386	1			T3	4		T6	7		T11	10
all_values[7]	386	1			T3	4		T6	7		T11	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1664

1

T3

16

T6

31

T11

41

auto[1]

1424

1

T3

16

T6

25

T11

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1228

1

T3

8

T6

26

T11

26

auto[1]

1860

1

T3

24

T6

30

T11

54

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1745

1

T3

16

T6

36

T11

44

auto[1]

1343

1

T3

16

T6

20

T11

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	84	1			T6	2		T11	4		T66	5
all_values[0]	auto[0]	auto[0]	auto[1]	43	1			T3	1		T11	1		T67	1
all_values[0]	auto[0]	auto[1]	auto[0]	72	1			T3	1		T6	2		T12	1
all_values[0]	auto[0]	auto[1]	auto[1]	29	1			T6	1		T11	2		T12	1
all_values[0]	auto[1]	auto[0]	auto[1]	98	1			T3	1		T6	1		T11	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1			T3	1		T6	1		T11	2
all_values[1]	auto[0]	auto[0]	auto[0]	75	1			T3	2		T6	1		T11	1
all_values[1]	auto[0]	auto[0]	auto[1]	35	1			T3	1		T6	1		T11	2
all_values[1]	auto[0]	auto[1]	auto[0]	58	1			T66	1		T56	2		T68	1
all_values[1]	auto[0]	auto[1]	auto[1]	37	1			T6	2		T11	2		T12	1
all_values[1]	auto[1]	auto[0]	auto[1]	98	1			T3	1		T6	2		T11	3
all_values[1]	auto[1]	auto[1]	auto[1]	83	1			T6	1		T11	2		T66	3
all_values[2]	auto[0]	auto[0]	auto[0]	69	1			T6	2		T11	2		T12	3
all_values[2]	auto[0]	auto[0]	auto[1]	35	1			T3	1		T11	1		T66	2
all_values[2]	auto[0]	auto[1]	auto[0]	83	1			T3	2		T6	3		T12	1
all_values[2]	auto[0]	auto[1]	auto[1]	35	1			T11	2		T56	1		T69	1
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T3	1		T6	2		T11	2
all_values[2]	auto[1]	auto[1]	auto[1]	82	1			T11	3		T12	1		T66	1
all_values[3]	auto[0]	auto[0]	auto[0]	67	1			T3	1		T6	1		T11	1
all_values[3]	auto[0]	auto[0]	auto[1]	39	1			T3	2		T6	2		T11	1
all_values[3]	auto[0]	auto[1]	auto[0]	76	1			T6	1		T11	1		T12	2
all_values[3]	auto[0]	auto[1]	auto[1]	37	1			T6	1		T11	3		T66	1
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T3	1		T6	1		T11	1
all_values[3]	auto[1]	auto[1]	auto[1]	76	1			T6	1		T11	3		T66	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1			T3	1		T6	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[1]	45	1			T6	1		T11	2		T66	1
all_values[4]	auto[0]	auto[1]	auto[0]	62	1			T6	1		T12	1		T68	1
all_values[4]	auto[0]	auto[1]	auto[1]	41	1			T3	1		T11	1		T66	2
all_values[4]	auto[1]	auto[0]	auto[1]	101	1			T3	1		T6	2		T11	3
all_values[4]	auto[1]	auto[1]	auto[1]	76	1			T3	1		T6	2		T11	3
all_values[5]	auto[0]	auto[0]	auto[0]	120	1			T6	3		T11	2		T12	3
all_values[5]	auto[0]	auto[1]	auto[0]	101	1			T3	1		T6	2		T11	4
all_values[5]	auto[1]	auto[0]	auto[1]	82	1			T3	2		T6	1		T11	2
all_values[5]	auto[1]	auto[1]	auto[1]	83	1			T3	1		T6	1		T11	2
all_values[6]	auto[0]	auto[0]	auto[0]	86	1			T6	2		T11	1		T12	2
all_values[6]	auto[0]	auto[0]	auto[1]	35	1			T11	1		T12	2		T56	1
all_values[6]	auto[0]	auto[1]	auto[0]	69	1			T6	3		T11	2		T12	1
all_values[6]	auto[0]	auto[1]	auto[1]	36	1			T3	1		T66	3		T67	1
all_values[6]	auto[1]	auto[0]	auto[1]	88	1			T11	4		T12	1		T66	4
all_values[6]	auto[1]	auto[1]	auto[1]	72	1			T3	3		T6	2		T11	2
all_values[7]	auto[0]	auto[0]	auto[0]	93	1			T6	2		T11	4		T12	3
all_values[7]	auto[0]	auto[0]	auto[1]	36	1			T6	2		T67	1		T69	1
all_values[7]	auto[0]	auto[1]	auto[0]	52	1			T11	3		T66	1		T68	2
all_values[7]	auto[0]	auto[1]	auto[1]	34	1			T3	1		T66	3		T68	1
all_values[7]	auto[1]	auto[0]	auto[1]	101	1			T6	2		T11	1		T12	4
all_values[7]	auto[1]	auto[1]	auto[1]	70	1			T3	3		T6	1		T11	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal