Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	11	0	0.00
Crosses	30	30	0	0.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	2	0	0.00	100	1	1	2
cp_is_hw_return	2	2	0	0.00	100	1	1	2
cp_is_write	2	2	0	0.00	100	1	1	2
cp_locality	5	5	0	0.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	30	0	0.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_active

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_hw_return

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_is_write

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	5	0	0.00

User Defined Bins for cp_locality

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid[0]	0	1	1
valid[1]	0	1	1
valid[2]	0	1	1
valid[3]	0	1	1
valid[4]	0	1	1

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Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	30	0	0.00	30
Automatically Generated Cross Bins	30	30	0	0.00	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Element holes

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	*	*	--	--	20
[auto[1]]	*	*	[auto[0]]	--	--	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal