Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3490266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4279423

1

T1

1328

T2

1

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4228540	1			T1	912		T2	1		T3	47
values[0x0]	1769674	1			T1	419		T4	4		T5	3
values[0x1]	1771475	1			T1	461		T4	5		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2481892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5287797

1

T1

1415

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25612	1			T1	3		T10	7		T11	2
valid_sources[0x01]	31998	1			T1	19		T6	1		T13	3
valid_sources[0x02]	27211	1			T1	17		T10	1		T13	6
valid_sources[0x03]	31218	1			T1	6		T10	3		T13	6
valid_sources[0x04]	31459	1			T10	3		T13	3		T38	3
valid_sources[0x05]	36504	1			T1	12		T13	4		T38	4
valid_sources[0x06]	30078	1			T1	5		T6	2		T13	4
valid_sources[0x07]	27647	1			T9	3		T10	1		T38	7
valid_sources[0x08]	28445	1			T1	2		T10	1		T13	1
valid_sources[0x09]	31771	1			T1	1		T13	3		T38	4
valid_sources[0x0a]	32834	1			T1	11		T6	2		T9	18
valid_sources[0x0b]	26975	1			T1	3		T9	2		T10	1
valid_sources[0x0c]	32016	1			T13	7		T38	2		T17	1
valid_sources[0x0d]	27523	1			T1	19		T3	6		T10	2
valid_sources[0x0e]	30134	1			T1	3		T10	5		T13	8
valid_sources[0x0f]	26978	1			T1	10		T9	22		T10	11
valid_sources[0x10]	26987	1			T1	23		T10	5		T13	3
valid_sources[0x11]	29211	1			T1	8		T13	7		T38	3
valid_sources[0x12]	28242	1			T1	5		T6	3		T10	1
valid_sources[0x13]	28197	1			T10	2		T13	5		T38	4
valid_sources[0x14]	29880	1			T1	2		T13	3		T38	5
valid_sources[0x15]	28308	1			T1	2		T3	1		T10	3
valid_sources[0x16]	32539	1			T1	16		T10	1		T13	6
valid_sources[0x17]	29938	1			T13	3		T38	4		T18	15
valid_sources[0x18]	28325	1			T1	6		T2	1		T9	4
valid_sources[0x19]	29198	1			T1	4		T6	2		T10	3
valid_sources[0x1a]	29970	1			T9	73		T10	1		T13	2
valid_sources[0x1b]	27371	1			T1	24		T10	2		T13	2
valid_sources[0x1c]	37287	1			T5	1		T10	18		T13	5
valid_sources[0x1d]	36335	1			T10	4		T13	7		T38	9
valid_sources[0x1e]	41750	1			T1	2		T10	10		T13	2
valid_sources[0x1f]	47181	1			T1	7		T9	7		T10	9
valid_sources[0x20]	28349	1			T1	13		T10	6		T13	3
valid_sources[0x21]	28866	1			T10	5		T13	2		T38	3
valid_sources[0x22]	28789	1			T1	3		T10	5		T13	2
valid_sources[0x23]	31534	1			T1	2		T10	14		T13	3
valid_sources[0x24]	26284	1			T10	9		T13	4		T38	8
valid_sources[0x25]	29158	1			T1	5		T10	5		T13	3
valid_sources[0x26]	28481	1			T1	9		T10	14		T13	5
valid_sources[0x27]	30638	1			T1	40		T10	13		T13	3
valid_sources[0x28]	29523	1			T1	7		T3	2		T10	5
valid_sources[0x29]	30621	1			T1	16		T6	9		T10	3
valid_sources[0x2a]	27734	1			T6	3		T10	10		T13	5
valid_sources[0x2b]	33157	1			T1	25		T6	2		T10	25
valid_sources[0x2c]	31189	1			T1	8		T3	15		T10	2
valid_sources[0x2d]	25745	1			T1	11		T13	2		T38	5
valid_sources[0x2e]	66583	1			T1	1		T10	4		T13	5
valid_sources[0x2f]	32718	1			T1	1		T9	21		T13	7
valid_sources[0x30]	28553	1			T1	7		T9	3		T13	4
valid_sources[0x31]	30803	1			T1	3		T10	7		T13	3
valid_sources[0x32]	27195	1			T9	28		T10	6		T11	2
valid_sources[0x33]	31776	1			T10	6		T13	3		T38	2
valid_sources[0x34]	27222	1			T1	1		T38	3		T18	17
valid_sources[0x35]	28410	1			T13	5		T38	10		T17	8
valid_sources[0x36]	29885	1			T1	10		T13	5		T38	4
valid_sources[0x37]	27757	1			T10	5		T13	6		T38	4
valid_sources[0x38]	30330	1			T1	8		T10	10		T13	4
valid_sources[0x39]	27224	1			T10	4		T13	2		T38	3
valid_sources[0x3a]	27068	1			T6	2		T13	7		T38	5
valid_sources[0x3b]	26750	1			T1	1		T10	4		T13	5
valid_sources[0x3c]	37394	1			T1	1		T6	2		T10	4
valid_sources[0x3d]	30785	1			T1	10		T10	4		T11	1
valid_sources[0x3e]	36573	1			T1	14		T10	2		T11	2
valid_sources[0x3f]	27028	1			T10	7		T11	1		T13	3
valid_sources[0x40]	29141	1			T1	11		T9	58		T13	2
valid_sources[0x41]	28357	1			T1	22		T13	1		T38	2
valid_sources[0x42]	31308	1			T1	5		T6	7		T10	7
valid_sources[0x43]	28949	1			T1	1		T9	22		T10	1
valid_sources[0x44]	30839	1			T13	5		T38	2		T17	1
valid_sources[0x45]	33347	1			T6	1		T13	4		T14	2
valid_sources[0x46]	27660	1			T1	11		T10	6		T13	1
valid_sources[0x47]	28128	1			T1	6		T10	5		T13	2
valid_sources[0x48]	29775	1			T9	7		T13	4		T25	2
valid_sources[0x49]	29132	1			T1	6		T4	11		T13	4
valid_sources[0x4a]	37816	1			T1	4		T10	2		T11	2
valid_sources[0x4b]	30175	1			T1	9		T10	1		T11	2
valid_sources[0x4c]	30706	1			T1	4		T10	4		T13	6
valid_sources[0x4d]	31469	1			T10	11		T38	1		T17	2
valid_sources[0x4e]	25851	1			T10	5		T13	4		T38	2
valid_sources[0x4f]	28744	1			T1	4		T13	4		T38	1
valid_sources[0x50]	28957	1			T1	1		T10	6		T13	2
valid_sources[0x51]	27258	1			T1	1		T10	4		T13	6
valid_sources[0x52]	28758	1			T1	10		T10	7		T13	4
valid_sources[0x53]	27236	1			T1	7		T9	10		T10	17
valid_sources[0x54]	28665	1			T1	1		T10	7		T13	5
valid_sources[0x55]	26884	1			T1	9		T13	1		T38	2
valid_sources[0x56]	28481	1			T1	3		T13	5		T38	5
valid_sources[0x57]	27620	1			T1	2		T13	4		T38	3
valid_sources[0x58]	28415	1			T1	25		T13	3		T38	4
valid_sources[0x59]	26989	1			T1	2		T10	8		T11	1
valid_sources[0x5a]	29006	1			T1	3		T9	56		T13	2
valid_sources[0x5b]	29634	1			T10	2		T11	2		T13	4
valid_sources[0x5c]	27545	1			T6	4		T10	17		T13	5
valid_sources[0x5d]	28824	1			T10	2		T13	2		T38	3
valid_sources[0x5e]	27534	1			T1	22		T10	3		T11	1
valid_sources[0x5f]	26219	1			T10	4		T13	6		T38	4
valid_sources[0x60]	28733	1			T1	2		T3	7		T10	3
valid_sources[0x61]	28599	1			T1	1		T13	1		T38	5
valid_sources[0x62]	29380	1			T1	10		T10	1		T13	3
valid_sources[0x63]	26634	1			T1	8		T10	5		T13	6
valid_sources[0x64]	28742	1			T10	1		T13	3		T38	1
valid_sources[0x65]	29103	1			T1	6		T10	3		T13	1
valid_sources[0x66]	31679	1			T1	5		T10	3		T13	4
valid_sources[0x67]	28736	1			T1	13		T9	4		T10	5
valid_sources[0x68]	33725	1			T1	11		T10	1		T13	4
valid_sources[0x69]	27588	1			T6	3		T9	99		T13	4
valid_sources[0x6a]	28200	1			T1	6		T6	2		T10	2
valid_sources[0x6b]	26570	1			T1	25		T10	3		T13	5
valid_sources[0x6c]	28640	1			T1	19		T9	19		T10	16
valid_sources[0x6d]	25378	1			T1	18		T13	5		T38	6
valid_sources[0x6e]	27289	1			T1	14		T10	2		T45	2
valid_sources[0x6f]	27618	1			T1	6		T10	3		T13	3
valid_sources[0x70]	32046	1			T1	8		T10	6		T38	3
valid_sources[0x71]	28039	1			T1	16		T6	1		T10	12
valid_sources[0x72]	32708	1			T1	5		T6	1		T9	45
valid_sources[0x73]	27729	1			T1	14		T13	3		T38	2
valid_sources[0x74]	41878	1			T1	5		T10	15		T13	3
valid_sources[0x75]	42977	1			T1	13		T38	2		T17	3
valid_sources[0x76]	26359	1			T1	4		T3	12		T10	4
valid_sources[0x77]	29004	1			T1	29		T10	1		T11	1
valid_sources[0x78]	27321	1			T1	10		T6	3		T9	15
valid_sources[0x79]	25984	1			T1	28		T13	4		T38	1
valid_sources[0x7a]	28832	1			T1	6		T13	3		T15	2014
valid_sources[0x7b]	28836	1			T10	2		T13	4		T38	5
valid_sources[0x7c]	29607	1			T1	9		T10	3		T13	3
valid_sources[0x7d]	28059	1			T1	5		T10	8		T13	4
valid_sources[0x7e]	29752	1			T1	11		T10	12		T13	4
valid_sources[0x7f]	29084	1			T1	3		T13	5		T38	6
valid_sources[0x80]	28688	1			T6	1		T13	6		T38	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063554

1

T1

452

T2

1

T4

1

values[0x0]

all_enables

biggest_size

1618883

1

T1

419

T4

4

T5

2

values[0x1]

all_enables

biggest_size

1596986

1

T1

457

T4

2

T5

2