Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3511310

1

T1

464

T3

47

T4

4

full_word

4280635

1

T1

1328

T2

1

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7791505	1			T1	1792		T2	1		T3	47
auto[TlIntgErrCmd]	144	1			T98	13		T123	2		T125	7
auto[TlIntgErrData]	129	1			T98	10		T123	2		T125	5
auto[TlIntgErrBoth]	167	1			T98	7		T123	6		T125	18

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4232935

1

T1

912

T2

1

T3

47

auto[1]

3559010

1

T1

880

T4

9

T5

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3168867	1			T1	460		T3	47		T4	1
auto[TlIntgErrNone]	partial	auto[1]	342046	1			T1	4		T4	3		T5	3
auto[TlIntgErrNone]	full_word	auto[0]	1063877	1			T1	452		T2	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3216715	1			T1	876		T4	6		T5	4
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T98	2		T123	2		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T98	7		T125	5		T202	4
auto[TlIntgErrCmd]	full_word	auto[0]	11	1			T98	2		T125	1		T202	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T98	2		T204	1		T205	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T98	4		T123	1		T125	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T98	5		T125	2		T202	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T206	1		T207	1		T208	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T98	1		T123	1		T202	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T98	3		T123	3		T125	5
auto[TlIntgErrBoth]	partial	auto[1]	96	1			T98	4		T123	3		T125	13
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T202	1		T177	2		T207	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T209	1		T210	1		T211	1