Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	2974593	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	2974593	0	0
T1	96744	832	0	0
T2	1000	0	0	0
T3	1004	0	0	0
T4	1032	0	0	0
T5	1369	0	0	0
T6	27379	0	0	0
T7	5315	0	0	0
T8	16114	0	0	0
T9	2955	832	0	0
T10	12149	832	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	1663	0	0
T17	0	1664	0	0
T18	0	1666	0	0
T19	0	832	0	0
T38	0	1672	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	3234150	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	3234150	0	0
T1	96744	2680	0	0
T2	1000	0	0	0
T3	1004	0	0	0
T4	1032	0	0	0
T5	1369	0	0	0
T6	27379	0	0	0
T7	5315	0	0	0
T8	16114	0	0	0
T9	2955	832	0	0
T10	12149	832	0	0
T13	0	3731	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	833	0	0
T18	0	835	0	0
T19	0	832	0	0
T38	0	841	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	192980	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	192980	0	0
T8	16114	67	0	0
T9	2955	0	0	0
T10	12149	0	0	0
T11	972	0	0	0
T12	3590	0	0	0
T13	45652	0	0	0
T14	1205	0	0	0
T15	49138	0	0	0
T22	0	339	0	0
T24	0	639	0	0
T25	986	0	0	0
T30	0	779	0	0
T31	0	690	0	0
T32	0	1345	0	0
T41	0	136	0	0
T42	0	385	0	0
T43	0	893	0	0
T44	0	259	0	0
T45	840	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	447065	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	447065	0	0
T8	16114	255	0	0
T9	2955	0	0	0
T10	12149	0	0	0
T11	972	0	0	0
T12	3590	0	0	0
T13	45652	0	0	0
T14	1205	0	0	0
T15	49138	0	0	0
T22	0	339	0	0
T24	0	1992	0	0
T25	986	0	0	0
T30	0	779	0	0
T31	0	3030	0	0
T32	0	1344	0	0
T41	0	136	0	0
T42	0	385	0	0
T43	0	893	0	0
T44	0	259	0	0
T45	840	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	6097823	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	6097823	0	0
T1	96744	960	0	0
T2	1000	1	0	0
T3	1004	47	0	0
T4	1032	11	0	0
T5	1369	8	0	0
T6	27379	121	0	0
T7	5315	3	0	0
T8	16114	1108	0	0
T9	2955	60	0	0
T10	12149	182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444927349	13082015	0	0
DepthKnown_A	444927349	444792782	0	0
RvalidKnown_A	444927349	444792782	0	0
WreadyKnown_A	444927349	444792782	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	13082015	0	0
T1	96744	2885	0	0
T2	1000	2	0	0
T3	1004	47	0	0
T4	1032	11	0	0
T5	1369	8	0	0
T6	27379	121	0	0
T7	5315	3	0	0
T8	16114	5017	0	0
T9	2955	60	0	0
T10	12149	182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444927349	444792782	0	0
T1	96744	96651	0	0
T2	1000	915	0	0
T3	1004	933	0	0
T4	1032	963	0	0
T5	1369	1273	0	0
T6	27379	27329	0	0
T7	5315	5252	0	0
T8	16114	16051	0	0
T9	2955	2863	0	0
T10	12149	12050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0