Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3439642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4143875

1

T1

27

T2

1

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4152062	1			T1	1		T2	67		T3	1
values[0x0]	1715479	1			T1	13		T4	20		T5	61
values[0x1]	1715976	1			T1	21		T4	11		T5	71

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2442921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5140596

1

T1

31

T2

27

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27883	1			T7	3		T11	18		T13	24
valid_sources[0x01]	26596	1			T7	1		T11	11		T12	2
valid_sources[0x02]	27092	1			T7	2		T11	11		T13	32
valid_sources[0x03]	50920	1			T7	2		T11	12		T13	24
valid_sources[0x04]	28512	1			T7	5		T11	8		T12	2
valid_sources[0x05]	26325	1			T7	2		T11	13		T13	33
valid_sources[0x06]	26766	1			T7	4		T11	13		T13	15
valid_sources[0x07]	27798	1			T7	1		T11	13		T13	30
valid_sources[0x08]	36792	1			T7	6		T11	25		T13	35
valid_sources[0x09]	27289	1			T7	3		T11	8		T12	2
valid_sources[0x0a]	26069	1			T7	1		T11	8		T13	36
valid_sources[0x0b]	27921	1			T4	10		T11	15		T12	1
valid_sources[0x0c]	28924	1			T7	3		T11	5		T13	25
valid_sources[0x0d]	29294	1			T11	12		T13	18		T37	15
valid_sources[0x0e]	68026	1			T7	5		T9	3		T11	9
valid_sources[0x0f]	33463	1			T11	9		T13	24		T37	3
valid_sources[0x10]	26329	1			T7	1		T9	1		T11	15
valid_sources[0x11]	27337	1			T1	1		T4	5		T11	9
valid_sources[0x12]	27928	1			T7	3		T9	2		T11	3
valid_sources[0x13]	25920	1			T7	3		T11	7		T13	19
valid_sources[0x14]	28163	1			T7	4		T11	17		T12	1
valid_sources[0x15]	27172	1			T7	6		T9	2		T11	3
valid_sources[0x16]	27434	1			T7	9		T11	8		T13	26
valid_sources[0x17]	27573	1			T7	3		T11	11		T12	1
valid_sources[0x18]	26101	1			T7	9		T11	8		T13	35
valid_sources[0x19]	38066	1			T7	2		T11	11		T13	29
valid_sources[0x1a]	29527	1			T7	1		T9	1		T11	13
valid_sources[0x1b]	27441	1			T1	1		T7	5		T11	14
valid_sources[0x1c]	27090	1			T7	2		T8	186		T11	20
valid_sources[0x1d]	29144	1			T7	2		T11	6		T13	20
valid_sources[0x1e]	27937	1			T7	5		T11	17		T12	1
valid_sources[0x1f]	30032	1			T7	2		T11	7		T13	36
valid_sources[0x20]	28839	1			T7	4		T11	5		T13	30
valid_sources[0x21]	27613	1			T7	8		T9	2		T11	4
valid_sources[0x22]	29135	1			T4	2		T7	2		T11	8
valid_sources[0x23]	25690	1			T7	3		T11	13		T13	32
valid_sources[0x24]	26670	1			T1	1		T7	2		T11	9
valid_sources[0x25]	26129	1			T7	11		T11	11		T13	21
valid_sources[0x26]	26811	1			T7	8		T11	3		T12	1
valid_sources[0x27]	27282	1			T7	8		T11	11		T13	23
valid_sources[0x28]	26948	1			T11	18		T13	16		T37	4
valid_sources[0x29]	25461	1			T7	5		T11	10		T13	31
valid_sources[0x2a]	29209	1			T1	1		T11	14		T13	34
valid_sources[0x2b]	33760	1			T9	5		T11	4		T13	36
valid_sources[0x2c]	28939	1			T11	11		T13	34		T15	3
valid_sources[0x2d]	37996	1			T7	13		T11	12		T13	38
valid_sources[0x2e]	27795	1			T7	2		T11	12		T13	31
valid_sources[0x2f]	26988	1			T7	3		T11	4		T12	2
valid_sources[0x30]	30111	1			T7	17		T11	19		T13	19
valid_sources[0x31]	29113	1			T7	2		T11	3		T13	18
valid_sources[0x32]	29807	1			T7	4		T9	2		T11	6
valid_sources[0x33]	27882	1			T7	3		T11	7		T13	23
valid_sources[0x34]	28420	1			T7	2		T11	9		T12	1
valid_sources[0x35]	27911	1			T7	1		T11	13		T13	20
valid_sources[0x36]	27539	1			T7	2		T9	3		T11	8
valid_sources[0x37]	25819	1			T1	1		T11	15		T13	28
valid_sources[0x38]	29564	1			T9	1		T11	11		T12	1
valid_sources[0x39]	27011	1			T1	1		T7	3		T11	4
valid_sources[0x3a]	32805	1			T7	9		T11	14		T13	30
valid_sources[0x3b]	28707	1			T7	5		T11	11		T13	23
valid_sources[0x3c]	28833	1			T1	1		T7	3		T11	7
valid_sources[0x3d]	27334	1			T7	7		T11	5		T12	1
valid_sources[0x3e]	26780	1			T1	1		T11	11		T13	23
valid_sources[0x3f]	26870	1			T7	1		T9	1		T11	8
valid_sources[0x40]	28446	1			T7	14		T11	10		T13	29
valid_sources[0x41]	30630	1			T7	14		T11	4		T12	2
valid_sources[0x42]	29061	1			T7	5		T9	1		T11	3
valid_sources[0x43]	27451	1			T7	2		T11	5		T12	1
valid_sources[0x44]	26262	1			T7	1		T11	12		T13	27
valid_sources[0x45]	26847	1			T7	9		T11	10		T13	35
valid_sources[0x46]	28652	1			T7	4		T11	14		T13	12
valid_sources[0x47]	56271	1			T7	3		T11	6		T12	1
valid_sources[0x48]	29877	1			T7	4		T11	4		T13	24
valid_sources[0x49]	31810	1			T7	5		T11	5		T13	23
valid_sources[0x4a]	27074	1			T1	2		T7	14		T11	9
valid_sources[0x4b]	39074	1			T7	8		T11	8		T13	22
valid_sources[0x4c]	27360	1			T7	8		T9	2		T11	5
valid_sources[0x4d]	28860	1			T1	1		T7	2		T11	3
valid_sources[0x4e]	31122	1			T7	1		T11	9		T13	30
valid_sources[0x4f]	26917	1			T7	2		T9	1		T11	18
valid_sources[0x50]	27986	1			T7	2		T11	17		T13	29
valid_sources[0x51]	26695	1			T7	8		T11	7		T12	1
valid_sources[0x52]	28303	1			T1	1		T7	3		T11	10
valid_sources[0x53]	28729	1			T7	5		T11	8		T13	20
valid_sources[0x54]	36282	1			T4	2		T11	7		T13	23
valid_sources[0x55]	28183	1			T7	5		T9	1		T11	1
valid_sources[0x56]	27499	1			T7	4		T11	11		T36	1
valid_sources[0x57]	31395	1			T7	3		T11	4		T13	26
valid_sources[0x58]	27317	1			T7	4		T11	13		T13	18
valid_sources[0x59]	28963	1			T7	5		T11	15		T12	1
valid_sources[0x5a]	29678	1			T7	2		T11	19		T13	15
valid_sources[0x5b]	26557	1			T7	10		T11	7		T12	2
valid_sources[0x5c]	27903	1			T7	4		T11	15		T13	18
valid_sources[0x5d]	28424	1			T9	2		T11	7		T13	31
valid_sources[0x5e]	28841	1			T7	3		T11	8		T12	1
valid_sources[0x5f]	30510	1			T11	7		T13	17		T15	8
valid_sources[0x60]	26385	1			T1	1		T7	12		T9	2
valid_sources[0x61]	27299	1			T9	3		T11	5		T12	1
valid_sources[0x62]	26894	1			T7	12		T11	7		T13	39
valid_sources[0x63]	28428	1			T7	4		T11	10		T13	19
valid_sources[0x64]	29371	1			T7	2		T11	13		T13	34
valid_sources[0x65]	27190	1			T7	1		T11	8		T13	15
valid_sources[0x66]	33256	1			T7	2		T11	7		T13	18
valid_sources[0x67]	29699	1			T7	1		T11	5		T13	24
valid_sources[0x68]	28401	1			T1	1		T7	7		T11	6
valid_sources[0x69]	28685	1			T7	4		T11	11		T12	1
valid_sources[0x6a]	30351	1			T1	1		T7	3		T11	16
valid_sources[0x6b]	28118	1			T7	1		T11	7		T13	49
valid_sources[0x6c]	27548	1			T11	13		T12	2		T13	20
valid_sources[0x6d]	29413	1			T7	3		T11	6		T13	31
valid_sources[0x6e]	26352	1			T1	2		T7	2		T11	15
valid_sources[0x6f]	31110	1			T9	1		T11	6		T13	33
valid_sources[0x70]	29157	1			T7	1		T11	13		T13	22
valid_sources[0x71]	33086	1			T7	21		T9	1		T11	11
valid_sources[0x72]	30387	1			T7	5		T11	2		T13	19
valid_sources[0x73]	27763	1			T7	2		T11	8		T12	2
valid_sources[0x74]	28555	1			T11	17		T13	24		T15	3
valid_sources[0x75]	32984	1			T7	4		T11	5		T13	25
valid_sources[0x76]	29963	1			T7	4		T9	1		T11	12
valid_sources[0x77]	29486	1			T7	4		T9	1		T11	9
valid_sources[0x78]	26255	1			T7	1		T11	5		T13	39
valid_sources[0x79]	30566	1			T7	5		T9	1		T11	15
valid_sources[0x7a]	25488	1			T11	10		T13	14		T37	8
valid_sources[0x7b]	30972	1			T9	3		T11	5		T13	20
valid_sources[0x7c]	32646	1			T7	3		T11	25		T13	32
valid_sources[0x7d]	32653	1			T7	2		T9	2		T11	7
valid_sources[0x7e]	31010	1			T7	3		T9	4		T11	13
valid_sources[0x7f]	28237	1			T11	1		T12	1		T13	24
valid_sources[0x80]	28924	1			T7	1		T9	3		T11	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1033038

1

T1

1

T2

1

T4

1

values[0x0]

all_enables

biggest_size

1567851

1

T1

12

T4

15

T5

45

values[0x1]

all_enables

biggest_size

1542986

1

T1

14

T4

8

T5

53