Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3465166

1

T1

8

T2

66

T3

1

full_word

4145423

1

T1

27

T2

1

T4

24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7610179	1			T1	35		T2	67		T3	1
auto[TlIntgErrCmd]	155	1			T96	4		T117	7		T118	2
auto[TlIntgErrData]	133	1			T96	4		T117	7		T118	2
auto[TlIntgErrBoth]	122	1			T96	2		T117	6		T118	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4157265

1

T1

1

T2

67

T3

1

auto[1]

3453324

1

T1

34

T4

31

T5

132

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3123678	1			T2	66		T3	1		T5	92
auto[TlIntgErrNone]	partial	auto[1]	341123	1			T1	8		T4	8		T5	34
auto[TlIntgErrNone]	full_word	auto[0]	1033398	1			T1	1		T2	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3111980	1			T1	26		T4	23		T5	98
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T96	2		T117	1		T118	2
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T96	2		T117	5		T326	8
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T117	1		T332	1		T327	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T326	1		T329	1		T333	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T96	3		T117	4		T326	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T96	1		T117	2		T118	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T117	1		T326	1		T333	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T326	1		T329	1		T327	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T117	2		T118	4		T326	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T96	1		T117	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T96	1		T117	3		T327	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T118	1		T334	1		T335	1