Line Coverage for Module :
spi_p2s
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 34 | 34 | 100.00 |
| ALWAYS | 58 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| ALWAYS | 98 | 5 | 5 | 100.00 |
| ALWAYS | 110 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| ALWAYS | 134 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
| ALWAYS | 170 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 179 | 1 | 1 | 100.00 |
| ALWAYS | 183 | 5 | 5 | 100.00 |
57 always_comb begin
58 1/1 out_enable = 4'b 0000; // default
Tests: T1 T2 T3
59
60 1/1 unique case (io_mode)
Tests: T1 T2 T3
61 SingleIO: begin
62 1/1 out_enable = {2'b 00, data_valid_i, 1'b 0};
Tests: T1 T2 T3
63 end
64
65 DualIO: begin
66 1/1 out_enable = {2'b 00, {2{data_valid_i}}};
Tests: T1 T2 T3
67 end
68
69 QuadIO: begin
70 1/1 out_enable = {4{data_valid_i}};
Tests: T1 T2 T3
71 end
72
73 default: begin
74 out_enable = 4'b 0000;
75 end
76 endcase
77 end
78
79 1/1 assign s_en_o = (csb_i) ? 4'b 0000 : out_enable ;
Tests: T1 T2 T3
80
81 // `data_sent`
82 // Popping signal is a little bit tricky if p2s supports Quad IO
83 // The sent signal cannot be sent at the end of the beat, as it does not have
84 // enought time to affect the FIFO.
85 //
86 // If the sent signal asserted at the first beat, at the very first byte of
87 // SPI has no time to assert valid signal. So the sent signal does not affect
88 // the FIFO. So the logic sends first byte twice.
89 //
90 // This won't affect in Flash mode as in Flash/Passthrough mode, first byte is
91 // always SPI command. It does not send anything on the SPI bus.
92 //
93 // So, the logic generating `sent` signal looks not straightforward. It tries
94 // assert second last beat. So, in SingleIO (right after reset always), it
95 // asserts at 7th beat. Then the mode could be changed to Dual/ Quad.
96
97 always_comb begin
98 1/1 data_sent_o = 1'b 0;
Tests: T1 T2 T3
99
100 1/1 unique case (io_mode)
Tests: T1 T2 T3
101 1/1 SingleIO: data_sent_o = (cnt == 6);
Tests: T1 T2 T3
102 1/1 DualIO: data_sent_o = (cnt == 2);
Tests: T6 T7 T8
103 1/1 QuadIO: data_sent_o = (cnt == 0);
Tests: T17 T21 T22
104 default: data_sent_o = '0;
105 endcase
106 end
107
108 // data shift
109 always_ff @(posedge clk_i) begin
110 1/1 unique case (io_mode)
Tests: T1 T2 T3
111 SingleIO: begin
112 1/1 out_shift <= (order_i) ? {1'b0, out_shift_d[7:1]} : {out_shift_d[6:0], 1'b0};
Tests: T1 T2 T3
113 end
114
115 DualIO: begin
116 1/1 out_shift <= (order_i) ? {2'b0, out_shift_d[7:2]} : {out_shift_d[5:0], 2'b0};
Tests: T1 T2 T3
117 end
118
119 QuadIO: begin
120 1/1 out_shift <= (order_i) ? {4'b0, out_shift_d[7:4]} : {out_shift_d[3:0], 4'b0};
Tests: T1 T2 T3
121 end
122
123 default: begin
124 out_shift <= out_shift_d;
125 end
126 endcase
127 end
128
129 // out_shift_d
130 1/1 assign out_shift_d = (first_beat) ? data_i : out_shift;
Tests: T1 T2 T3
131
132 // SPI out
133 always_comb begin
134 1/1 s_o = 4'b 0000;
Tests: T1 T2 T3
135
136 1/1 unique case (io_mode)
Tests: T1 T2 T3
137 SingleIO: begin
138 1/1 s_o[1] = (order_i) ? ((!first_beat) ? out_shift[0] : data_i[0])
Tests: T1 T2 T3
139 : ((!first_beat) ? out_shift[7] : data_i[7]);
140 end
141
142 DualIO: begin
143 1/1 s_o[1:0] = (order_i) ? ((!first_beat) ? out_shift[1:0] : data_i[1:0])
Tests: T1 T2 T3
144 : ((!first_beat) ? out_shift[7:6] : data_i[7:6]);
145 end
146
147 QuadIO: begin
148 1/1 s_o = (order_i) ? ((!first_beat) ? out_shift[3:0] : data_i[3:0])
Tests: T1 T2 T3
149 : ((!first_beat) ? out_shift[7:4] : data_i[7:4]);
150 end
151
152 default: begin
153 s_o = 4'b 0000;
154 end
155 endcase
156 end
157
158 // io_mode
159 // io_mode reset value is SingleIO (as described in assumption)
160 // Previously, logic updated io_mode at every byte. It was to make io_mode
161 // safer. However, as `io_mode_i` is updated at @iSCK (from spi_device top),
162 // and also spi_p2s logic runs only when `data_valid_i` is high, the need of
163 // latching logic disapears.
164 //
165 // Now, the logic uses `io_mode_i` directly.
166 1/1 assign io_mode = io_mode_i;
Tests: T1 T2 T3
167
168 // cnt
169 always_ff @(posedge clk_i or negedge rst_ni) begin
170 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
171 1/1 cnt <= BitWidth'(0);
Tests: T1 T2 T3
172 1/1 end else if (last_beat) begin
Tests: T6 T7 T8
173 1/1 cnt <= BitWidth'(0);
Tests: T6 T7 T8
174 1/1 end else if (data_valid_i) begin
Tests: T6 T7 T8
175 1/1 cnt <= cnt + 1'b 1;
Tests: T6 T7 T8
176 end
MISSING_ELSE
177 end
178
179 1/1 assign first_beat = (cnt == '0);
Tests: T1 T2 T3
180
181 // Last beat depends on the mode
182 always_comb begin
183 1/1 last_beat = 1'b 0;
Tests: T1 T2 T3
184
185 1/1 unique case (io_mode)
Tests: T1 T2 T3
186 1/1 SingleIO: last_beat = (cnt == BitWidth'('h7));
Tests: T1 T2 T3
187 1/1 DualIO: last_beat = (cnt == BitWidth'('h3));
Tests: T6 T7 T8
188 1/1 QuadIO: last_beat = (cnt == BitWidth'('h1));
Tests: T17 T21 T22
189 default: last_beat = 1'b0;
Cond Coverage for Module :
spi_p2s
| Total | Covered | Percent |
|---|
| Conditions | 42 | 30 | 71.43 |
| Logical | 42 | 30 | 71.43 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 79
EXPRESSION (csb_i ? 4'b0 : out_enable)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T6,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (cnt == 3'h6)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T22,T23 |
LINE 102
EXPRESSION (cnt == 3'h2)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T6,T7,T8 |
LINE 103
EXPRESSION (cnt == 3'b0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T21,T22 |
| 1 | Covered | T17,T21,T22 |
LINE 112
EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Not Covered | |
LINE 116
EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Not Covered | |
LINE 120
EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T21,T22 |
| 1 | Not Covered | |
LINE 130
EXPRESSION (first_beat ? data_i : out_shift)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 138
SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 138
SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T22,T23 |
LINE 143
EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 143
SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 143
SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T6,T7,T8 |
LINE 148
EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 148
SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 148
SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T21,T22 |
| 1 | Covered | T17,T21,T22 |
LINE 179
EXPRESSION (cnt == '0)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 186
EXPRESSION (cnt == 3'('h00000007))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T22,T23 |
LINE 187
EXPRESSION (cnt == 3'('h00000003))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T6,T7,T8 |
LINE 188
EXPRESSION (cnt == 3'('b1))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T21,T22 |
| 1 | Covered | T17,T21,T22 |
Branch Coverage for Module :
spi_p2s
| Line No. | Total | Covered | Percent |
| Branches |
|
40 |
29 |
72.50 |
| TERNARY |
79 |
2 |
2 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| CASE |
60 |
4 |
4 |
100.00 |
| CASE |
100 |
4 |
3 |
75.00 |
| CASE |
110 |
7 |
4 |
57.14 |
| CASE |
136 |
13 |
7 |
53.85 |
| IF |
170 |
4 |
4 |
100.00 |
| CASE |
185 |
4 |
3 |
75.00 |
79 assign s_en_o = (csb_i) ? 4'b 0000 : out_enable ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T6,T7 |
130 assign out_shift_d = (first_beat) ? data_i : out_shift;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T6,T7,T8 |
60 unique case (io_mode)
-1-
61 SingleIO: begin
62 out_enable = {2'b 00, data_valid_i, 1'b 0};
==>
63 end
64
65 DualIO: begin
66 out_enable = {2'b 00, {2{data_valid_i}}};
==>
67 end
68
69 QuadIO: begin
70 out_enable = {4{data_valid_i}};
==>
71 end
72
73 default: begin
74 out_enable = 4'b 0000;
==>
Branches:
| -1- | Status | Tests |
| SingleIO |
Covered |
T1,T2,T3 |
| DualIO |
Covered |
T1,T2,T3 |
| QuadIO |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
100 unique case (io_mode)
-1-
101 SingleIO: data_sent_o = (cnt == 6);
==>
102 DualIO: data_sent_o = (cnt == 2);
==>
103 QuadIO: data_sent_o = (cnt == 0);
==>
104 default: data_sent_o = '0;
==>
Branches:
| -1- | Status | Tests |
| SingleIO |
Covered |
T1,T2,T3 |
| DualIO |
Covered |
T6,T7,T8 |
| QuadIO |
Covered |
T17,T21,T22 |
| default |
Not Covered |
|
110 unique case (io_mode)
-1-
111 SingleIO: begin
112 out_shift <= (order_i) ? {1'b0, out_shift_d[7:1]} : {out_shift_d[6:0], 1'b0};
-2-
==>
==>
113 end
114
115 DualIO: begin
116 out_shift <= (order_i) ? {2'b0, out_shift_d[7:2]} : {out_shift_d[5:0], 2'b0};
-3-
==>
==>
117 end
118
119 QuadIO: begin
120 out_shift <= (order_i) ? {4'b0, out_shift_d[7:4]} : {out_shift_d[3:0], 4'b0};
-4-
==>
==>
121 end
122
123 default: begin
124 out_shift <= out_shift_d;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| SingleIO |
1 |
- |
- |
Not Covered |
|
| SingleIO |
0 |
- |
- |
Covered |
T1,T4,T5 |
| DualIO |
- |
1 |
- |
Not Covered |
|
| DualIO |
- |
0 |
- |
Covered |
T6,T7,T8 |
| QuadIO |
- |
- |
1 |
Not Covered |
|
| QuadIO |
- |
- |
0 |
Covered |
T17,T21,T22 |
| default |
- |
- |
- |
Covered |
T1,T2,T3 |
136 unique case (io_mode)
-1-
137 SingleIO: begin
138 s_o[1] = (order_i) ? ((!first_beat) ? out_shift[0] : data_i[0])
-2- -3-
==>
==>
139 : ((!first_beat) ? out_shift[7] : data_i[7]);
-4-
==>
==>
140 end
141
142 DualIO: begin
143 s_o[1:0] = (order_i) ? ((!first_beat) ? out_shift[1:0] : data_i[1:0])
-5- -6-
==>
==>
144 : ((!first_beat) ? out_shift[7:6] : data_i[7:6]);
-7-
==>
==>
145 end
146
147 QuadIO: begin
148 s_o = (order_i) ? ((!first_beat) ? out_shift[3:0] : data_i[3:0])
-8- -9-
==>
==>
149 : ((!first_beat) ? out_shift[7:4] : data_i[7:4]);
-10-
==>
==>
150 end
151
152 default: begin
153 s_o = 4'b 0000;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
| SingleIO |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| SingleIO |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| SingleIO |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T17,T22,T23 |
| SingleIO |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| DualIO |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
Not Covered |
|
| DualIO |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Not Covered |
|
| DualIO |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
Covered |
T6,T7,T8 |
| DualIO |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
Covered |
T6,T7,T8 |
| QuadIO |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
Not Covered |
|
| QuadIO |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
Not Covered |
|
| QuadIO |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
Covered |
T17,T21,T22 |
| QuadIO |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
Covered |
T17,T21,T22 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
170 if (!rst_ni) begin
-1-
171 cnt <= BitWidth'(0);
==>
172 end else if (last_beat) begin
-2-
173 cnt <= BitWidth'(0);
==>
174 end else if (data_valid_i) begin
-3-
175 cnt <= cnt + 1'b 1;
==>
176 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T6,T7,T8 |
| 0 |
0 |
1 |
Covered |
T6,T7,T8 |
| 0 |
0 |
0 |
Covered |
T6,T7,T8 |
185 unique case (io_mode)
-1-
186 SingleIO: last_beat = (cnt == BitWidth'('h7));
==>
187 DualIO: last_beat = (cnt == BitWidth'('h3));
==>
188 QuadIO: last_beat = (cnt == BitWidth'('h1));
==>
189 default: last_beat = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| SingleIO |
Covered |
T1,T2,T3 |
| DualIO |
Covered |
T6,T7,T8 |
| QuadIO |
Covered |
T17,T21,T22 |
| default |
Not Covered |
|
Assert Coverage for Module :
spi_p2s
Assertion Details
IoModeChangeValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
149300643 |
7344 |
0 |
0 |
| T6 |
62334 |
5 |
0 |
0 |
| T7 |
1313 |
3 |
0 |
0 |
| T8 |
14008 |
8 |
0 |
0 |
| T9 |
1 |
0 |
0 |
0 |
| T10 |
1 |
0 |
0 |
0 |
| T11 |
72642 |
0 |
0 |
0 |
| T12 |
1 |
0 |
0 |
0 |
| T13 |
260476 |
0 |
0 |
0 |
| T14 |
422 |
0 |
0 |
0 |
| T16 |
0 |
1 |
0 |
0 |
| T17 |
0 |
5 |
0 |
0 |
| T19 |
0 |
5 |
0 |
0 |
| T21 |
0 |
5 |
0 |
0 |
| T22 |
0 |
6 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T24 |
0 |
10 |
0 |
0 |
| T36 |
1 |
0 |
0 |
0 |
IoModeDefault_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
149300643 |
19485 |
0 |
0 |
| T6 |
62334 |
2 |
0 |
0 |
| T7 |
1313 |
1 |
0 |
0 |
| T8 |
14008 |
1 |
0 |
0 |
| T9 |
1 |
0 |
0 |
0 |
| T10 |
1 |
0 |
0 |
0 |
| T11 |
72642 |
0 |
0 |
0 |
| T12 |
1 |
0 |
0 |
0 |
| T13 |
260476 |
0 |
0 |
0 |
| T14 |
422 |
0 |
0 |
0 |
| T16 |
0 |
5 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T19 |
0 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T24 |
0 |
1 |
0 |
0 |
| T36 |
1 |
0 |
0 |
0 |