Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	2832047	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	2832047	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	0	0	0
T12	1975	0	0	0
T13	163302	0	0	0
T14	2313	0	0	0
T16	0	1663	0	0
T17	0	832	0	0
T19	0	1666	0	0
T21	0	832	0	0
T22	0	832	0	0
T23	0	1663	0	0
T36	817	0	0	0
T37	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	3253407	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	3253407	0	0
T6	29503	832	0	0
T7	11627	3797	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	0	0	0
T12	1975	0	0	0
T13	163302	0	0	0
T14	2313	0	0	0
T16	0	832	0	0
T17	0	3648	0	0
T19	0	836	0	0
T21	0	832	0	0
T22	0	832	0	0
T23	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	193212	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	193212	0	0
T5	4139	35	0	0
T6	29503	0	0	0
T7	11627	0	0	0
T8	17002	0	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	341	0	0
T12	1975	0	0	0
T13	163302	898	0	0
T15	0	31	0	0
T36	817	0	0	0
T38	0	23	0	0
T42	0	256	0	0
T43	0	256	0	0
T44	0	4	0	0
T45	0	594	0	0
T46	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	482109	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	482109	0	0
T5	4139	35	0	0
T6	29503	0	0	0
T7	11627	0	0	0
T8	17002	0	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	1124	0	0
T12	1975	0	0	0
T13	163302	898	0	0
T15	0	31	0	0
T36	817	0	0	0
T38	0	23	0	0
T42	0	256	0	0
T43	0	1162	0	0
T44	0	17	0	0
T45	0	594	0	0
T46	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	5972087	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	5972087	0	0
T1	3076	35	0	0
T2	1305	67	0	0
T3	1321	1	0	0
T4	7566	32	0	0
T5	4139	232	0	0
T6	29503	71	0	0
T7	11627	106	0	0
T8	17002	783	0	0
T9	3090	85	0	0
T10	5714	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464757517	13279554	0	0
DepthKnown_A	464757517	464623494	0	0
RvalidKnown_A	464757517	464623494	0	0
WreadyKnown_A	464757517	464623494	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	13279554	0	0
T1	3076	35	0	0
T2	1305	67	0	0
T3	1321	1	0	0
T4	7566	32	0	0
T5	4139	232	0	0
T6	29503	71	0	0
T7	11627	475	0	0
T8	17002	782	0	0
T9	3090	85	0	0
T10	5714	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464757517	464623494	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0